GB2320834A - Image outline enhancing circuit - Google Patents

Abstract

A circuit for enhancing the outline of an image reproduced by a video signal Y in an image display apparatus such as a television receiver. The circuit includes a slope sense circuit 210 for sensing an amplitude transition of the video signal in order to generate a slope sensing signal SU corresponding to a degree and a period of the amplitude transition. A comparison circuit 220 compares the slope sensing signal with a reference signal to generate a control signal SC based on the comparison result. A delay circuit 232 delays the video signal for a predetermined period to generate an delayed signal DY2. A selective feedback circuit 230 selectively outputs 231 the delayed signal DY2 to the delay input in response to the control signal SC in order to feedback the delayed signal. A selective output circuit 240 outputs either the video signal Y or the delayed signal DY2 in response to the control signal SC, thereby generating an enhanced video signal PS.

Description

IMAGE OUTLINE ENHANCING CIRCUIT The present invention relates to a circuit for enhancing an image outline for use in an image display apparatus such as a television receiver, a videotape recorder or a video projector. More particularly, the present invention relates to an image outline enhancing circuit which can be used to enhance the outline of an image displayed by a video signal in order to improve a contour of the image.

It is known that the response of a video signal processing system, such as one found in a television receiver, may be subjectively improved by increasing the slope or "steepness" of a video signal amplitude transition. The response may also be improved by generating a signal "preshoot" just before an amplitude transition, and a signal "overshoot" just after the amplitude transition, so that an image outline displayed by the video signal is improved.

FIG. 1 is a block diagram for showing a conventional circuit for enhancing an image outline.

In FIG. 1, the circuit includes a first delay 121, a second delay 122, a third delay 123, a first adder 131, a second adder 132, a subtracter 141, and a 1/2-amplifier 15.

The first and second delay sections 121 and 122 delay video signals which are continuously inputted through an input terminal 101 for a predetermined period T, respectively. The delayed signals, which are produced by the first and second delay sections 121 and 122, are respectively outputted to the first adder 131 and the subtracter 151. The third delay 132 delays the delayed signals from the second delay 122 for the predetermined period T in order to generate a video signal delayed for period 2T. The second adder 132 adds the 2T period delayed video signal to a current video signal through the input terminal 101 so that the second adder 132 continuously generates added video signals, and the second adder 132 provides the added video signals to the 1/2-amplifier 151. The 1/2amplifier 151 1/2-amplifies the added video signals to generate 1/2-amplified signals. The 1/2-amplified signals generated by the 1/2- amplifier 151 are provided to the subtracter 141. The subtracter 141 subtracts the 1/2-amplified signals from the T period delayed video signals in order to generate subtracted signals, which are outputted to the first adder 131 as peaking signals. The first adder 131 adds the peaking signals from the subtracter 141 to the delayed video signal from the first delay 121, so that the first adder 131 generates peaked video signals.

According to the image outline enhancing circuit 100, the circuit derives the peaking signals from video signals which are continuously inputted through the input terminal 101, and adds the peaking signals to the video signals for peaking video signals, so that the circuit 100 enhances image outlines to be formed by the video signals.

However, in the image outline enhancing circuit 100, the generation of the preshoot before an amplitude transition and the overshoot after an amplitude transition makes it possible to cause an artificial contour compensation such as white and black at edges of the reproduced image.

In order to improve an image outline without introducing the preshoot and overshoot, one example of an image outline enhancing circuit is disclosed in U.S. Pat. No.5,293,541(issued to Shigehiro Ito, etc., on March 21, 1994). The circuit suggested by the above U.S. Patent enhances an outline of an image to be reproduced according to a video signal by modifying an amplitude transition time of the video signal. The circuit includes a control signal generation circuit, a plurality of subtracters, delay circuits, a composite circuit, and a signal selection circuit. The control signal generation circuit generates a control signal by combining subtracted signals provided from the subtracter. The subtracter generates the subtracted signals by subtracting a plurality of delayed signals provided from the delay circuits. The composite circuit combines the delayed signals to each other, thereby generating a plurality of combined signals. And, the signal selection circuit selectively outputs one of the plurality of combined signals in accordance with the control signal, such that the signal selection circuit generates enhanced video signals.

However, though the circuit improves an image outline without introducing the preshoot and overshoot, the circuit has problems that the circuit needs as many delay circuits and subtracters as possible for developing a plurality of delayed signals and control signals in order to effectively enhance the video signals, and this need of a great number of delay circuits and subtracters makes the construction of the circuit complicated.

For the foregoing reasons, there is need for an image outline enhancing circuit which has an uncomplicated construction without a reduction in efficiency with respect to the enhancing of the image outline.

It is an object of the present invention to provide an image outline enhancing circuit which has an uncomplicated construction without a reduction in efficiency of the image outline enhancement.

In order to achieve the object of the present invention, an image outline enhancing circuit according to one aspect of the present invention is provided, the image outline enhancing circuit comprising: a sense means for sensing an amplitude transition of the video signal in order to generate a slope sensing signal corresponding to a degree and a period of the amplitude transition; a comparison means for comparing the slope sensing signal with a reference signal in order to generate a control signal based on the comparison result; a delay means for delaying an input signal which is supplied for a predetermined period in order to generate a delayed signal; a selective feedback means for selectively outputting the delayed signal which is outputted from the delay means to the delay means as the input signal of the delay means in response to the control signal in order to feedback the delayed signal; and a selective output means for selectively outputting either the video signal or the delayed signal in response to the control signal in order to generate an enhanced video signal.

According to the present invention, the circuit has an uncomplicated construction without a reduction in efficiency of the image outline enhancement.

In order to achieve the object of the present invention, there is provided an image outline enhancing circuit according to other aspect of the present invention, the circuit comprises: a sense means for sensing the initial, end and middle periods to generate a sensing signal corresponding to each of the initial, end and middle periods and a degree of the amplitude transition; a first comparison means for comparing the sensing signal with a first reference signal in order to generate a first control signal based on the first comparison result; a second comparison means for comparing the sensing signal with a second reference signal in order to generate a second control signal based on the second comparison result; a first delay means for delaying the video signal for a predetermined period in order to generate a first delayed signal; a first selection means for selectively outputting either the video signal or the first delayed signal in response to the first control signal in order to generate a first selected signal; a second delay means for delaying the first selected signal for the predetermined period in order to generate a second delayed signal; a third delay means for delaying the second control signal for the predetermined period in order to synchronize the second control signal with the first selected signal, thereby generating a delayed control signal; and a second selection means for selecting either the video signal or the second delayed signal in response to the delayed control signal in order to generate a second selected signal as an enhanced video signal.

According to the present invention, the circuit has an uncomplicated construction without a reduction in efficiency with respect of the image outline enhancement.

Examples of embodiments of the present invention will now be described with reference to the drawings, in which: FIG. 1 is a block diagram for showing a conventional image outline enhancing circuit; FIG. 2 is a block diagram of an image outline enhancing circuit according to the first embodiment of the present invention; FIGs. 3A through 3K are waveform diagrams for showing the operations at several portions of the image outline enhancing circuit of FIG. 2; FIG. 4 is a block diagram of an image outline enhancing circuit according to the second embodiment of the present invention; and FIGs. 5A through 5K are waveform diagrams for showing the operations at several portions of the image outline enhancing circuit of FIG. 4.

A description will be given below in detail, with reference to the accompanying drawings, of the circuitry configuration and the operation of the circuitry according to one embodiment of the present invention.

First Embodiment FIG. 2 is a block diagram for showing an image enhancing circuit according to the first embodiment of the invention.

In FIG. 2, the image outline enhancing circuit 200 includes a slope sense circuit 210, a comparison circuit 220, a selective feedback circuit 230, and a selective output circuit 240.

The slope sense circuit 210 senses an amplitude transition of a video signal Y which is continuously inputted through an video signal input terminal 201, and generates a slope sensing signal SU corresponding to a degree and a period of the amplitude transition of the video signal Y. And, the slope sense circuit 210 provides the slope sensing signal SU to the comparison circuit 220.

The slope sense circuit 210 includes a first delay 211 and an subtracter 222 for sensing the amplitude of the video signal Y. The first delay 211 delays the video signal for a predetermined period to develop first delayed video signals Dyl. The subtracter 222 subtracts the video signal Y from the first delayed video signal DY1 to generate a subtracted signal SU, and provides the subtracted signal SU as the slope sensing signal SU to the comparison circuit 220.

The comparison circuit 220 generates a control signal SC by comparing the slope sensing signal SU, which is provided from the slope sense circuit 210, with a reference signal a. Preferably, the comparison circuit 220 compares an absolute value AS of the slope sensing signal SU with a magnitude of the reference signal a and generates the control signal SC in response to the comparison result.

The comparison circuit 220 includes an absolute value circuit(hereinafter, referred to as ABS circuit) 221 and a comparator 222 for generating the control signal SC.

The ABS circuit 221 develops the absolute value signal AS of the slope sensing signal SU, and outputs the absolute value signal AS to the comparator 222.

The comparator 222 compares the absolute value signal AS with the magnitude of the reference signal a which is provided from an exterior signal source(not shown in FIG. 2), and generates the control signal SC corresponding to the comparison result. The comparator 222 preferably generates a logic signal as the control signal. The comparator 222 generates a low logic signal when the absolute value signal AS is lower than the magnitude of the reference signal a, and to the contrary, a high logic signal when the absolute value signal AS is equal to or lower than the magnitude of the reference signal a, as the control signal.

The selective feedback circuit 230 selectively feedbacks an output signal which is outputted through an output terminal thereof to the input terminal thereof in response to the control signal SC, such that the selective feedback circuit 230 outputs the same video signal as a video signal inputted in the feedback.

The selective feedback circuit 230 includes a first switch 231 and a second delay 232. The first switch 231 has a first input terminal S1 connected with the video signal input terminal 201, a second input terminal S2 connected with the output terminal of the second delay 232, and an output terminal connected with an input terminal of the second delay 232. The first switch 231 is switched on either the first input terminal S1 or the second input terminal S2 in response to the control signal, and when the switch 231 is switched on the second input terminal S2, the switch 231 and the second delay 232 form a feedback loop. The second delay 232 delays an input signal provided by the first switch 231 for the predetermined period to develop a second delayed signal DY2, and outputs the second delayed signal DY2 to the selective output circuit 240.

The selective output circuit 240 is a second switch 240 which has a first input terminal S3 and a second input terminal S4. The first input terminal of the second switch is connected with the video signal input terminal 201, and the second input terminal S4 is connected with the output terminal of the second delay 232 of the selective feedback circuit 230. The second switch 240 is selectively switched on one of the first and second input terminals S3 and S4 thereof in response to the control signal from the comparator 222, thereby generating an enhanced video signal PS.

The operation of the image enhancing circuit 200 according to the second embodiment of the present invention will be described in detail below with reference to FIGs. 3A through 3F.

FIGs. 3A through 3F are waveform diagrams for showing the operations at several portions of the image enhancing circuit of FIG. 2.

When a video signal Y, as shown in FIG. 3A, passes through the video signal input terminal 201, the video signal Y is inputted into the first delay 211 of the slope sense circuit 210, a first input terminal S1 of the first switch 231 of the selective feedback circuit 230 and the first input terminal S3 of the second switch 240, respectively.

The first delay 211 of the slope sense circuit 210 delays the video signal Y for the predetermined period to generate a first delayed signal DY1, as shown in FIG. 3B, and provides the first delayed signal DY1 to the subtracter 212 of the slope sense circuit 210. Then, the subtracter 212 subtracts the video signal Y from the first delayed signal DY1 to generate a subtracted signal SU, as shown in FIG. 3C.

As aforementioned, the subtracted signal SU is used as the slope sensing signal SU, which is provided to the ABS circuit 221 of the control signal generation circuit 220.

The ABS circuit 221 of the control signal generation circuit 220 translates the slope sensing signal SU into an absolute value, as shown in FIG. 3D, and outputs the absolute value AS to the comparator 222. The comparator 222 compares the absolute value AS with the magnitude a of the reference signal to generate the control signal SC, as shown in FIG. 3E, and outputs the control signal SC to the first switch 231 and second switch 240, respectively. The comparator 222 generates a low logic signal when the absolute value is lower than the magnitude a of the reference signal, and to the contrary, a high logic signal when the absolute value is equal to or higher than the magnitude a of the reference signal, as the control signal.

The first switch 231 of the selective feedback circuit 230 is switched on the first input terminal S1 thereof when the control signal SC is the low logic signal, such that the video signal, which is inputted through the video signal input terminal 201, is outputted to the second delay 232.

At the same time, the second switch 240 is switched on the first input terminal S3 thereof when the control signal SC is the low logic signal, such that the video signal, which is inputted through the video signal input terminal to the first input terminal thereof, is outputted as the enhanced video signal without modifying the video signal, as shown in FIG. 3F.

When the control signal SU is the high logic signal, the first switch 231 and the second switch 240 are switched on the second input terminals S2 and S4 of them, respectively.

Then, the second input terminal S2 of the first switch 231 is connected with the output terminal of the second delay 232, such that the first switch 231 and the second delay 231 form a feedback loop. When the feedback loop is formed by the operation of the first switch 231, the output terminal of the second delay 232 is connected with the input terminal of the second delay 232, such that the second delay 232 continuously outputs the same feedbacked signal DY2 as the video signal which is lastly inputted through the first input terminal S1 of the first switch 231 as soon as the first switch 231 is switched on the second input terminal S2 thereof. And, at the same time, as the second switch 240, such as the first switch 231, is switched on the second input terminal S4 thereof, the second switch 240 outputs the feedbacked signal DY2 as the enhanced video signal PS, as shown in FIG.

3F.

Therefore, though the circuit has a simple construction, the circuit can enhance an outline of an image to be reproduced by a video signal without a reduction in efficiency of the image outline enhancement as well as introducing the preshoot and overshoot.

Second Embodiment FIG. 4 is a block diagram for showing an image enhancing circuit according to the second embodiment of the present invention.

In FIG. 4, the image outline enhancing circuit 400 includes a slope sense circuit 500, a first comparator 610, a second comparator 620, a first delay 711, a first switch 712, a second delay 721, a second switch 722, and a third delay 630.

The slope sense circuit 500 senses an amplitude transition of a video signal Y which is inputted through a video signal input terminal 401, and generates a slope sensing signal DFF corresponding to a period and a degree of the amplitude transition of the video signal Y.

Preferably, in order to generate a slope sensing signal DFF, the slope sense circuit 500 includes a fourth delay 510, a subtracter 520, an absolute value circuit 530, and a differential circuit 540.

The fourth delay 510 delays the video signal Y for a predetermined period to develop a first delayed signal DY1, and provides the first delayed signal DY1 to the subtracter 520.

The subtracter 520 subtracts the first delayed signal DY1 from the video signal provided through the video signal input terminal 401, such that the subtracter 520 generates a subtracted signal SU. The subtracted signal SU is provided to the absolute value circuit 530.

The absolute value circuit 530 translates the subtracted signal SU into an absolute value signal AB, and outputs the absolute value signal AB to the differential circuit 540.

The differential circuit 540 differentiates the absolute value signal AB to generate a differential signal DFF, and provides the differential signal DFF as the slope sensing signal DFF to the first comparator 610 and the second comparator 620, respectively.

The first comparator 610 compares the slope sensing signal DFF with a first reference signal -a to generate a first control signal C1 in response to the first comparison result, and provides the first control signal C1 to the first switch 710.

The second comparator 620 compares the slope sensing signal with a second reference signal a to generate a second control signal C2 in response to the second comparison result, and provides the second control signal C2 to the third delay 630.

The third delay 630 delays the second control signal C2 for the predetermined period to generate a delayed control signal DC2, and provides the delayed control signal DC2 to the second switch 722.

The first delay 711 delays the video signal Y which is inputted through the video signal input terminal 401 to generate a second delayed signal DY2, and provides the second delayed signal DY2 to a second input terminal S2 of the first switch 712.

The first switch 712 has a first input terminal S1 which is connected with the video signal input terminal 401, the second input terminal S2 which is connected with a output terminal of the first delay 711, and an output terminal which is connected with a first input terminal S3 of the second switch 722 and an input terminal of the second delay 721. The first switch 712 is switched on either the first input terminal S1 or the second input terminal S2 in response to the first control signal C1 from the first comparator 610, such that the first switch 712 generates a first selected video signal SE1, and provides the first selected signal SE1 to the second delay 721 and the first input terminal S3 of the second switch 722.

The second delay 721 delays the first selected signal SE1 for the predetermined period to generate a second delayed signal DSE, and provides the second delayed signal DSE to a second input terminal S4 of the second switch 722.

The second switch 722 is switched on either the first input terminal S3 or second input terminal S4 thereof in response to the delayed control signal DC2 which is provided from the third delay 630, such that the second switch 722 generates a second selected signal SE2 as an enhanced video signal SE2.

The operation of the image enhancing circuit 400 according to the second embodiment of the present invention will be described in detail below with reference to FIGs. 5A through 5K.

FIGs. 5A through 5K are waveform diagrams for showing the operations at several portions of the image enhancing circuit of FIG. 4.

In FIG. 4, when a video signal Y, as shown in FIG. SA, is inputted to the video signal input terminal 401, the video signal Y is provided to the first delay 711 and the fourth delay 510, respectively.

The first delay 711 and the fourth delay 510 delay the video signal Y for the predetermined period to generate the second delayed signal DY2 and the first delayed signal DY1, respectively, as shown in FIG. 5B.

The subtracter 520 subtracts the first delayed signal DY1 which is provided by the fourth delay 510 from the video signal Y to generate the subtracted signal SU, as shown in FIG. 3C, and outputs the subtracted signal SU to the absolute value circuit 530.

The absolute value circuit 530 translates the subtracted signal SU into an absolute value signal ABS, as shown in FIG. 3D, and provides the absolute value signal ABS to the differential circuit 540.

The differential circuit 540 differentiates the absolute value signal to generate a differential signal DFF, as shown in FIG. 3E, and provides the differential signal DFF to each of the first and second comparators 610 and 620.

The first comparator 610 compares the differential signal DFF with the first reference signal -a to generate a first control signal C1. The first comparator 610 preferably generates a logic signal as the first control signal C1, as shown in FIG. 3F. That is, the first comparator 610 generates a low logic signal when a voltage of the differential signal DFF is higher than a voltage of the first reference signal -a, and a high logic signal when the voltage of the differential signal DFF is lower than the voltage of the first reference signal -a.

The second comparator 620 compares the differential signal DFF with the second reference signal a to generate a second control signal C2. The second comparator 620 preferably generates a logic signal as the second control signal C2, as shown in FIG. 3G. That is, the second comparator 620 generates a low logic signal when a voltage of the differential signal DFF is lower than a voltage of the second reference signal a, and a high logic signal when the voltage of the differential signal DFF is higher than the voltage of the second reference signal a.

The first switch 712 is controlled by the first control signal C1. The first switch 712 is switched on the first input terminal S1 thereof when the first control signal C1 is the low logic signal, and the second input terminal S2 when the first control signal is the high logic signal, such that the first switch 712 generates a first selected signal SE1, as shown in FIG. 31. And, the first switch 712 provides the first selected signal SE1 to the second delay 721 and the first input terminal S3 of the second switch 722, respectively.

The second delay 721 delays the first selected signal which is provided from the first switch 712 for the predetermined period to generate a second delayed signal DSE, as shown in FIG. 3J, and outputs the second delayed signal DSE to the second input terminal S4 of the second switch 722.

In the meantime, the second control signal C2 is provided to and delayed by the third delay 630. The third delay 630 generates a delayed control signal DC2, as shown in FIG. 3H, and provides the delayed control signal DC2 to the second switch 722.

And, the second switch 722 is switched on the first input terminal S3 thereof when the delayed control signal DC2 is the low logic signal, and the second input terminal S4 when the delayed control signal DC2 is the high logic signal, such that the second switch 722 generates a second selected signal SE2 as the enhanced video signal SE2, as shown in FIG.

3K.

Therefore, the circuit 400 can enhance an outline of an image to be reproduced by a video signal without a reduction in efficiency of the image outline enhancement as well as introducing the preshoot and overshoot.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not respective, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and the range of equivalency of the claims are therefore intended to be embraced therein.

Claims (10)

1. A circuit for enhancing an outline of an image formed by a video signal which is continuously provided through an input terminal, said circuit comprising: a) sense means for sensing an amplitude transition of the video signal in order to generate a slope sensing signal corresponding to a degree and a period of the amplitude transition; b) comparison means for comparing the slope sensing signal with a reference signal in order to generate a control signal based on the comparison result; c) delay means for delaying an input signal which is supplied for a predetermined period in order to generate a delayed signal; d) selective feedback means for selectively outputting the delayed signal which is outputted from the delay means to the delay means as the input signal of the delay means in response to the control signal in order to feedback the delayed signal; and e) selective output means for selectively outputting either the video signal or the delayed signal in response to the control signal in order to generate an enhanced video signal.

2. A circuit as claimed in Claim 1, wherein said sense means includes a delay for delaying the video signal for the predetermined period in order to develop a first delayed video signal; and a subtracter for subtracting the video signal from the first delayed video signal in order to generate a subtracted signal as the slope sensing signal.

3. A circuit as claimed in Claim 1, or Claim 2, wherein said selective feedback means is a first switch which has a first input terminal, a second input terminal, and an output terminal, the first input terminal connected with the input terminal, the second input terminal connected with an output terminal of the delay means, and the output terminal connected with an input terminal of the delay means, wherein the first switch is switched on either the fist input terminal or the second input terminal thereof in response to the control signal, such that the first switch feedbacks the output signal of the delay means to the input terminal of the delay means.

4. A circuit as claimed in any of Claims 1 to 3, wherein said selective output means is a second switch which includes a first input terminal connected with the input terminal and a second input terminal connected with an output terminal of the delay means, wherein the second switch is selectively switched on either the first input terminal or the second input terminal thereof in response to the control signal provided from the comparison means, such that when the second switch generates the enhanced video signal.

5. A circuit for enhancing an outline of an image formed by a video signal which is continuously inputted through an video signal input terminal, said circuit comprising: a) sense means for sensing the initial, end and middle periods to generate a sensing signal corresponding to each of the initial, end and middle periods and a degree of the amplitude transition; b) first comparison means for comparing the sensing signal with a first reference signal in order to generate a first control signal based on the first comparison result; c) second comparison means for comparing the sensing signal with a second reference signal in order to generate a second control signal based on the second comparison result; d) first delay means for delaying the video signal for a predetermined period in order to generate a first delayed signal; e) first selection means for selectively outputting either the video signal or the first delayed signal in response to the first control signal in order to generate a first selected signal; f) second delay means for delaying the first selected signal for the predetermined period in order to generate a second delayed signal; g) third delay means for delaying the second control signal for the predetermined period in order to synchronize the second control signal with the first selected signal, thereby generating a delayed control signal; and h) second selection means for selecting either the video signal or the second delayed signal in response to the delayed control signal in order to generate an second selected signal as an enhanced video signal.

6. A circuit as claimed in Claim 5, said sense means includes an subtracter for subtracting the first delayed signal from the video signal; an absolute value circuit for translating a subtracted signal generated by the subtracter into an absolute value; and a differential circuit for differentiating the absolute value in order to generate a differential signal as the sensing signal.

7. A circuit as claimed in Claim 5 or 6, wherein said first comparison means generates a low logic signal when a voltage of the sensing signal is higher than a voltage of the first reference signal, and a high logic signal when the voltage of the sensing signal is lower than the voltage of the first reference signal.

8. A circuit as claimed in any one of Claims 5 to 7, wherein said first selection means selects the first delayed signal when the first control signal is the low logic signal, and the video signal when the first control signal is the high logic signal.

9. A circuit as claimed in any one of Claims 5 to 8, wherein said second selection means selects the second delayed signal when a voltage of the sensing signal is lower than a voltage of the second reference signal, and the first selected signal when the voltage of the sensing signal is higher than the voltage of the second reference signal.

10. A circuit substantially as hereinbefore described with reference to Figures 2 and 3 or Figures 4 and 5 of the accompanying drawings.