GB2318451A - Fabricating a semiconductor device - Google Patents

Fabricating a semiconductor device Download PDF

Info

Publication number
GB2318451A
GB2318451A GB9722208A GB9722208A GB2318451A GB 2318451 A GB2318451 A GB 2318451A GB 9722208 A GB9722208 A GB 9722208A GB 9722208 A GB9722208 A GB 9722208A GB 2318451 A GB2318451 A GB 2318451A
Authority
GB
United Kingdom
Prior art keywords
film
forming
phase growth
vapor phase
raw material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9722208A
Other versions
GB2318451B (en
GB9722208D0 (en
Inventor
Masanobu Zenke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of GB9722208D0 publication Critical patent/GB9722208D0/en
Publication of GB2318451A publication Critical patent/GB2318451A/en
Application granted granted Critical
Publication of GB2318451B publication Critical patent/GB2318451B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a method of forming an electrode 8 on a semiconductor substrate 1, in which a silicon layer 4,5,6 is formed on the substrate and then a silicide or metal film 7 is formed on the silicon layer by vapour phase growth, e.g. LP-CVD, using a metal halide containing gas, the silicon layer is formed to include an electrically conductive barrier film 5 to prevent diffusion of halogen atoms from the silicide or metal film into a gate oxide film 3. The barrier film 5 may be oxide or nitride, the layer 7 comprising tungsten or titanium silicide or tungsten or titanium metal. Examples of the metal halide containing gas include dichlorosilane and tungsten hexafluoride, silane and tungsten hexafluoride, tungsten hexafluoride or titanium tetrachloride. The silicon may be in an amorphous and/or polycrystalline state, and may be ion-implanted to make it conductive.

Description

TITLE OF THE INVENTION METHOD OF FABRICATING SEMICONDUCTOR DEVICE BACKGROUND OF THE INVENTION Field of the invention The present invention relates to a method of fabricating a semiconductor device, wherein diffusion of a halogen atom mixed in wiring such as a gate electrode is suppressed and variation in threshold voltage due to the diffusion can be suppressed.
Description of the prior art Recently a width of wiring has been decreased and a length thereof has been elongated in the trend toward higher integration of a semiconductor device. As a result a resistance of the wiring has been increased. Especially, in this connection, reduction in operational speed of transistor due to the increase in wiring resistance of the gate electrode has been a problem. In order to reduce the wiring resistance of the gate electrode, there has been employed a gate electrode having a two-layer structure in which a high melting point silicide film is deposited on a polycrystalline silicon film. In order to reduce a wiring resistance, a bit line of DRAM also has a two-layer structure of wiring like the gate electrode.
A method of forming a gate electrode having the twolayer structure is described as follows. The method comprises the steps of: forming a polycrystalline silicon film by a CVD method on a gate oxide film, or forming an amorphous silicon film on a gate oxide film and then annealing a film at about 650 OC to form a polycrystalline silicon film on the gate oxide film; and supplying silane (SiH4) gas and tungsten hexafluoride (WF6) gas as raw material gases into a CVD apparatus to form a tungsten silicide film on the polycrystalline silicon film by the CVD method, which is a thermal decomposition reaction.
Whereby the gate electrode having a two-layer structure is produced.
When a gate electrode is produced by the above mentioned method, however, fluorine atoms are incorporated in a tungsten silicide film at a high concentration of c about 10l6 (atom/cm3). Thereafter, the gate electrode is subjected to a heat treatment. On this occasion, fluorine atoms incorporated in the tungsten silicide film diffuse and a great number of fluorine atoms penetrate into and stay in a gate oxide film. For this reason, a thickness of the gate oxide film is increased and a threshold value of a transistor is varied, so that a fault that a reliability is degraded exists.
In order to prevent the diffusion of fluorine atoms, a method has been proposed that a provisional silicon film doped with phosphorus is formed on the tungsten silicide film and the fluorine atoms are diffused into the provisional silicon film (Japanese Unexamined Patent Publication No. Hei 6-267973). FIGs. 1A to 1D are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No. Hei 6-267973 in the order of steps. In the method of fabricating a semiconductor device described in the publication, the included steps are as follows. As shown in FIG. 1A, first of all, a silicon oxide film 52 for device isolation is formed on the surface of a p-type silicon substrate 51. A gate oxide film 53 is formed to a thickness roughly in the range of 6 to 20 nm in a area surrounded by the silicon oxide film 52. A polycrystalline silicon film 54 with a thickness of about 100 nm is formed on the gate oxide film 53 by a low pressure chemical vapor deposition method (LP-CVD) using silane gas. A tungsten silicide film 57 with a thickness of about 100 nm is formed on the polycrystalline silicon film 54 by the LP-CVD method using silane gas and tungsten hexafluoride gas. Phosphorus is ion-implanted at a dose roughly in the range of 10l4 to 10l5 (cm2) in the polycrystalline silicon film 54 after passing the tungsten silicide film 57 to make the polycrystalline silicon film 54 electrically conductive.
As shown in FIG. 1B, a polycrystalline silicon film or an amorphous silicon film as a provisional silicon film 55 is formed on the tungsten silicide film 57 by the LP-CVD method. Phosphorus is ion-implanted at a dose roughly in the range of 1016 to 10l7 (cam~2) in the provisional silicon film 55, wherein an amount of the dose is larger by two digits than that of the polycrystalline silicon film 54.
Then a heat treatment is conducted in a nitrogen atmosphere at a temperature in the range of 900 to 1000 OC for a period of time from 20 to 30 min, to diffuse fluorine atoms mixed in the tungsten silicide film 57 out into the provisional silicon film 55. As shown in FIG. lC, the provisional silicon film 55 is then selectively removed by a wet-etching method or a dry etching method.
As shown in FIG. 1D, a two-layer structured gate electrode 58 composed of the polycrystalline silicon film 54 and the tungsten silicide film 57 is formed by a lithography technique and a dry etching technique, which are both commonly used. Arsenic is ion-implanted in the ptype silicon substrate 51 with the use of the gate electrode 58 and the silicon oxide film 52 as a mask. A heat treatment is given to the ion-implanted substrate 51 to activate the arsenic and form source/drain regions 59.
Thereafter, an interlayer insulating film and wiring, not shown, are formed and thereby an n-channel MOSFET is completed.
According to the method of fabricating a semiconductor device, since the provisional silicon film 55 is removed after fluorine atoms are diffused in the provisional silicon film 55, diffusion of fluorine atoms into the gate oxide film 53 is suppressed. However, even with the method, prevention of the diffusion of fluorine atoms into the gate oxide film 53 is not sufficient. In the cases where a device becomes smaller and transistors constituting the device are also miniaturized as in 256M DRAM and 1G DRAM and the like, requirement for prevention of the fluorine diffusion is severer and the method can not satisfactorily be used. In the miniaturization in a device, it is very difficult to remove the provisional silicon film 55 without etching of a part of the tungsten silicide film 57. For this reason, there arises a problem that margins in process conditions are small. Moreover, since the steps of formation of a provisional silicon film and removal of the film are additionally required, the number of steps in process is increased.
A method has been proposed in order to prevent diffusion of fluorine atoms, in which a silicon dioxide film is formed on a tungsten silicide film and fluorine atoms are let to be diffused to the silicon dioxide film M.
(Japanese Unexamined Patent Publication No. Hei 4-336466).
FIGs. 2A to 2C are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No.
Hei 4-336466 in the order of the steps. In the method of fabricating a semiconductor device described in the publication, the included steps are as follows. First of all, as shown in FIG. 2A, a gate oxide film 62 is formed on the surface of a silicon semiconductor substrate 61 by a thermal oxidation method. A polycrystalline silicon film 63 is formed on the gate oxide film 62 by a CVD method. A tungsten silicide film 64 is formed on the polycrystalline silicon film 63 by the CVD method using silane gas and tungsten hexafluoride gas.
As shown in FIG. 2B, a gate electrode 65 is formed on the gate oxide film 62 in patterning the polycrystalline silicon film 63 and the tungsten silicide film 64. Arsenic is ion-implanted in the tungsten silicide film 64 and the polycrystalline silicon film 63 at a dose of the order of 5 x 1015 (cam~2) and thereby the polycrystalline silicon film 63 is made electrically conductive. On this occasion, the surface of the tungsten silicide film 64 is shifted into an amorphous state.
As shown in FIG. 2C, a silicon dioxide film 66 covering the gate electrode 65 completely is formed by the CVD method. Then a silicon nitride film 67 and a boron phosphorus glass film 68 are deposited in that order on the silicon dioxide film 66. A heat treatment is then given to the substrate in a water vapor atmosphere at 900 OC for 30 min. A heat treatment is conducted in a nitrogen atmosphere at 900 OC for 30 min following the heat-treatment in the water vapor atmosphere to diffuse fluorine atoms mixed in the tungsten silicide film 64 out into the silicon dioxide film 66.
According to the method of fabricating a semiconductor device, since the fluorine atoms have been diffused out into the silicon dioxide film 66, the diffusion of the fluorine atoms into the gate oxide film 62 is suppressed. However, even with the method, prevention of the diffusion of the fluorine atoms is not sufficient.
A method has been proposed in which an amorphous silicon film, an amorphous tungsten silicide film and oxidized silicon are successively formed in that order on a polycrystalline silicon film, so that fluorine atoms are segregated in a region remote from a gate oxide film (Japanese Unexamined Patent Publication No. Hei 6-104203).
FIGs. 3A to 3D are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No.
Hei 6-104203 in the order of steps. In the method described in the publication, first of all, as shown in FIG. 3A, a silicon oxide film 72 is formed on the surface of a silicon substrate 71 by a thermal oxidation method. A polycrystalline silicon film 73 with a thickness of about 100 nm is then formed on the silicon oxide film 72 by a CVD method.
As shown in FIG. 3B, ions of a element which is in the same group as silicon such as germanium is implanted and thereby a portion from the surface to a depth of about 50 nm of the polycrystalline silicon film 73 is converted to an amorphous state to form an amorphous silicon film 74.
As shown in FIG.3C, an amorphous tungsten silicide film 75 is formed on the amorphous silicon film 74 by a thermal deposition method using silane gas and tungsten hexafluoride gas.
An amorphous silicon oxide film is formed on the amorphous tungsten silicide'film 75 by the CVD method. The substrate 71 is then subjected to a heat treatment in a nitrogen atmosphere at a temperature between 800 to 900 CC for 30 min. As shown in FIG. 3D, solid phase growth is advanced from the polycrystalline silicon film 73 to the amorphous silicon film 74 to form a polycrystalline silicon film 76. The solid phase growth is continued to be advanced from the polycrystalline silicon film 76 to the amorphous tungsten silicide film 75 to form a polycrystalline tungsten silicide film 77. The solid phase growth is further continued to be advanced from the polycrystalline tungsten silicide film 77 to the amorphous silicon oxide film to form a polycrystalline silicon oxide film 78. In this occasion, fluorine atoms mixed in the amorphous tungsten silicide film 75 are segregated into the polycrystalline silicon oxide film 78 at a high concentration by the solid phase growth.
According to the method of fabricating a semiconductor device, the fluorine atoms in the tungsten silicide film 77 is segregated to a region remote from the gate oxide film 72. However, the method requires a step of forming an amorphous silicon oxide film and thereby the number of steps is increased. Moreover, even with the method, prevention of diffusion of the fluorine atoms is not sufficient.
There is employed a method in which dichlorosilane (SiH2Cl2) gas is used instead of silane (SiH4) gas in forming a tungsten silicide film and thereby the number of fluorine atoms in the tungsten silicide film is reduced.
While the number of fluorine atoms in the tungsten silicide film can be decreased, compared with the case where silane gas is used, the decrease is not sufficient, so that dichlorosilane gas cannot be applied to a device with a miniaturized structure.
There has been proposed a semiconductor device in which ions brought into the upper surface of a gate electrode by ion-implantation in order to form source/drain regions can be prevented from diffusion, though the device is not a device to suppress variation of a threshold value caused by diffusion of fluorine atoms in a tungsten silicide film into a gate oxide film (Japanese Unexamined Patent Publication No. Hei 4-246861). In a semiconductor device described in the publication, there is provided a gate electrode, comprising a polycrystalline silicon (SIPOS) film having a semi-insulating property which is mixed with oxygen, formed on a gate oxide film. A well is rl formed under the gate oxide film. Since a diffusion coefficient in a SIPOS film is smaller than that in a polycrystalline silicon film, it is prevented that an ion implanted in the upper surface of the gate electrode moves through the gate oxide film and reaches the well, when the ion is brought in the upper surface of the gate electrode.
As a result, variation of a threshold value is suppressed.
According to the semiconductor device, since an gate electrode with a semi-insulating property is employed, ion diffusion to a well is suppressed. However, compared with a gate electrode made of a polycrystalline silicon film, a resistance in the gate electrode is higher and thereby it cannot be applied to a device with a miniaturized structure.
Moreover, there is a problem that diffusion of fluorine atoms in the tungsten silicide film into the gate oxide film is not sufficiently prevented.
The above described problems also arise in the cases where a halogen atom other than fluorine such as chlorine and the like is employed. While diffusion of a halogen atom from a gate electrode to a gate insulating film has been described, a phenomenon similar to the case arises in wiring having a two-layer structure which is connected to source/drain regions of bit lines in DRAM. The reason why is that, in the trend of miniaturization in a device, a gap between wiring and a gate oxide film has been decreased and thereby halogen atoms in the wiring are easier to diffuse out to the gate oxide film.
SUMMARY OF THE INVENTION a.
It is an coject of at least t preferred embodiments of tse present invention to provide a mettd of fabricating a sanoonctor device with a Y\ reliability in which the device can be fabricated in a fewer steps with a sufficient process margin secured, wherein the device has wiring with a low resistance and variation of a threshold value of a transistor can be prevented.
A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a silicon layer on the semiconductor substrate; and forming a film of one selected from the group consisting of silicide films and metal films on the silicon layer, using a first raw material gas containing a metal halide gas by a vapor phase growth method. The silicon layer includes a first silicon film on the semiconductor substrate, a diffusion preventing film preventing passage of halogen atoms through the same film with electric conductivity on the first silicon film, and a second silicon film on the diffusion preventing layer.
The present invention is to form a silicon layer with a diffusion preventing film between a silicide film or a metal film and a semiconductor substrate. The diffusion preventing film has not only an electric conductivity but also an effect to prevent diffusion of a halogen atom and the like. Therefore, a semiconductor device with a good reliability and without variation of a threshold value of a transistor can be fabricated, even when a silicide film or metal film is formed using a metal halide as a raw 4 material. Even if wiring has a structure which is made of either a silicide film and a silicon layer or a metal film and a silicon layer in order to reduce its resistance, such wiring can be applied to a device with a miniaturized structure. Besides, since steps of formation of a film to fix atoms of an impurity such as fluorine atoms and its removal are not necessary, a semiconductor device can be fabricated in a fewer steps and with secured sufficient process margins, compared with conventional methods.
BRIEF DESCRIPTION OF THE DRAWINGS FIGs. 1A to 1D are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No. Hei 6-267973 in the order of steps.
FIGs. 2A to 2C are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No. Hei 4-336466 in the order of steps.
FIGs. 3A to 3D are sectional views showing a conventional method of fabricating a semiconductor device described in a publication of Japanese Unexamined Patent Publication No. Hei 6-104203 in the order of steps.
FIGs. 4A to 4D are sectional views showing a method of fabricating a semiconductor device according to a first embodiment of the present invention in the order of steps.
FIG. 5 is a graph showing the flow velocity of gas when a mixed gas containing oxygen gas is used.
FIG. 6 is a graph showing a relation between the time of heat treatment and the variation of a threshold value (Vt) on various gate electrodes.
FIG. 7 is a graph showing the flow velocity of gas when a mixed gas containing ammonia gas is used.
FIGs. 8A to 8E are sectional views showing a method of fabricating a semiconductor device according to a second embodiment of the present invention in the order of steps.
FIGs. 9A to 9D are sectional views showing a method of fabricating a semiconductor device according to a third embodiment of the present invention in the order of steps.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described by way of example only with reference to the accanenying drawings.
FIGs. 4A to 4D are sectional views showing a method of fabricating a semiconductor device according to a first embodiment of. the present invention in the order of steps.
FIG. 5 is a graph showing the flow velocity of gas when a mixed gas containing oxygen gas is used, wherein the axis of abscissas represents an elapsed time from a starting time of supply of silane gas and the axis of ordinate represents the flow velocity of gas. In FIG. 5, a time interval for ion-implantation has been omitted, a solid line shows a gas flow velocity of silane gas and a broken line shows a gas flow velocity of a mixed gas. In the embodiment, as shown in FIG. 4A, first of all, a silicon oxide film 2 for device isolation is formed on the surface of a p-type silicon substrate 1. A gate oxide film 3 is farmed in a region surrounded by the silicon oxide film 2 to a thickness roughly in the range of 6 to 20 nm. A first polycrystalline silicon film 4 with a thickness of about 50 nm is deposited on the gate oxide film 3 at a temperature of the p-type substrate 1 in the range of 600 to 700 OC by a low pressure chemical vapor deposition (LP-CVD) method.
On this occasion, as shown FIG. 5, silane gas is supplied at a flow velocity of about 1000 (sccm) for about 10 min into an LP-CVD apparatus. After the 10 min has passed, the supply of silane gas is terminated and phosphorus is ionimplanted at a dose roughly in the range of 1014 to 10l5 (cm 2) in the first polycrystalline silicon film 4 to make the first polycrystalline silicon film 4 electrically conductive.
The interior of the LP-CVD apparatus is sufficiently purged in a time interval of T1 And a mixed gas composed of 1 volume % of. O2 gas and the rest of inert gas such as He gas or Ar gas is supplied into the LP-CVD apparatus at a flow velocity of about 600 (sccm) for a time period of 1 to 10 min to make the interior of the LP-CVD apparatus changed to an oxidative atmosphere. In the oxidative atmosphere, the surface of the first polycrystalline silicon film 4 is oxidized and, as shown in FIG. 4B, an oxidized silicon film as a diffusion preventing film 5 is formed to a thickness in the range of several times as large as 0.1 nm to about 2 nm.
After the diffusion preventing film 5 is obtained, the supply of the mixed gas is terminated. In the following time interval T2, the interior of the LP-CVD apparatus is sufficiently purged. Thereafter, in a similar manner to the case where the first polycrystalline silicon film 4 is deposited, a second polycrystalline silicon film 6 with a thickness roughly in the range of 50 to 100 nm is deposited on the diffusion preventing film 5. Thus a silicon layer with a diffusion preventing film is constructed from the first polycrystalline silicon film 4, the diffusion preventing film 5 and the second polycrystalline silicon film 6.
A tungsten silicide film 7 with a thickness roughly in the 100 to 200 nm is deposited on the second polycrystalline silicon film 6 by the LP-CVD method using dichlorosilane (SiH2Cl2) gas and tungsten hexafluoride (WF6).
Phosphorus is ion-implanted at a dose roughly in the range of 1014 to 1015 (cam'2) in the second polycrystalline silicon film 6 to make the second polycrystalline silicon film 6 electrically conductive. In the operation of ionimplantation, it is important that an accelerating voltage is adjusted so as not to give a damage to the diffusion preventing film 5 due to colliding of a phosphorus ion to the film 5.
Thereafter, as shown in FIG. 4D, a photolithographic technique and a dry etching technique, both of which are conventional, are used for patterning of the tungsten silicide film 7, the second polycrystalline silicon film 6, the diffusion preventing film 5 and the first polycrystalline silicon film 4 to form an electrically conductive layer 8 for a gate electrode. Then arsenic is ion-implanted in the surface of the p-type substrate 1 with the use of the conductive layer 8 and the silicon oxide film 2 as a mask, and subsequently a heat treatment is given to activate arsenic ions and form source/drain regions 9 in the surface of the p-type substrate 1.
Thereafter, an interlayer insulating film, upper layer wiring and the like (not shown) are formed to complete a transistor.
In the embodiment, the diffusion preventing film 5 is formed between the first polycrystalline silicon film 4 and the second polycrystalline silicon film 6. The diffusion preventing film 5 is formed in such a manner that the surface of the first polycrystalline silicon film 4 is exposed to the oxidative atmosphere and silicon atoms in several atomic layers in the vicinity of the surface of the first polycrystalline silicon film 4 bond with oxygen atoms.
Therefore, the whole of the diffusion preventing film 5 is not only composed of Si-O bonds, but Si-Si bonds are also present in the diffusion preventing film 5. The diffusion preventing film 5 is not made of a stoichiometrically perfect oxide film and has a great number of defects therein, so that the film 5 has a low degree of an electrically insulating property. Moreover, a degree of oxidation is low and the film 5 has a film thickness as thin as a tunnel current can flow. As seen from the above description, while a current flows in the direction of thickness of the diffusion preventing film 5, a resistance of: the diffusion preventing film 5 is a little higher, a compared with a polycrystalline silicon film without a diffusion preventing film. However, the resistance can be sufficiently adjusted by introduced ions of phosphorus of into polycrystalline silicon films 4 and 6.
While the diffusion preventing film 5 has a low degree of an electrically insulating property and is stoichiometrically imperfect, the film 5 is an oxide film and still has a nature that acts as a diffusion barrier against atoms of an impurity such as halogen. Since the diffusion preventing film 5 is formed between the first polycrystalline silicon film 4 and the second polycrystalline silicon film 6, grains in the polycrystalline silicon films 4 and 6 are disconnected from each other by the diffusion preventing film 5, which exercises a barrier effect against grain boundary diffusion.
As described above, the diffusion preventing film 5 has not only an electrical conductivity but an effect of preventing diffusion of halogen atoms and the like. FIG. 6 is a graph showing a relation of the time of heat treatment with the variation of a threshold value (Vt) on various gate electrodes, wherein the axis of abscissas represents the time of heat treatment and the axis of ordinate represents the variation of a threshold value (Vt). A temperature of heat treatment is 800 OC. In FIG. 6, A indicates a semiconductor device fabricated in the first embodiment, B indicates a semiconductor device fabricated according to the method described in the publication of Japanese Unexamined Patent Publication No. Hei 6-267973 and C indicates a semiconductor device of a two-layer structure composed merely of a polycrystalline silicon film and a tungsten silicide film. As shown in FIG. 6, in the embodiment indicated at A, there is no variations of a threshold value (vt) over a long time of heat treatment, which gives a high reliability to the device. On the other hand, in the conventional examples indicated at B and C, as the time of heat treatment gets longer, the variation of a threshold becomes larger. Especially, in the case of a conventional device indicated at C, the variation of a threshold value (Vt) is tremendously larger.
In the embodiment, since there is no need for formation of a film to fix fluorine atoms on the tungsten silicide film 7, a semiconductor device can be fabricated in a fewer steps and process margins can be also sufficiently secured.
A mixed gas composed of 1 volume % of NH3 gas and the rest of an inert gas such as He or Ar may be used in formation of a diffusion preventing film. FIG. 7 is a graph showing the flow velocity of gas when a mixed gas containing ammonia gas is used, wherein the axis of abscissas represents the elapsed time from a starting time of supply of silane gas and the axis of ordinate represents the flow velocity of a gas. In FIG. 7, a time interval for ion-implantation has been omitted, a solid line shows a flow velocity of silane gas and a broken line shows a flow velocity of a mixed gas. Before a mixed gas containing NH3 gas is used, as shown in FIG. 7, the interior of the LP-CVD apparatus is sufficiently purged in a time interval of T, after supply of silane gas is terminated. After the purging, the mixed gas is supplied into the LP-CVD apparatus at a flow velocity of about 400 (sccm) for a time period of 1 to 10 min to convert an atmosphere of the interior of the apparatus to a nitriding atmosphere. In the nitriding atmosphere, the surface of the first polycrystalline silicon film 4 is nitrided to form a silicon nitride film of a thickness in the range of several times as large as 0.1 nm to about 2 nm as a diffusion preventing film. Then, the interior of the apparatus is again sufficiently purged in a time interval of T2. After the purging, the second polycrystalline silicon film is deposited on the diffusion preventing film. Thus formed diffusion preventing film has also not only an electric conductivity but an effect of preventing diffusion of halogen atoms and the like.
PH4 gas may be added to silane (Sin4) gas in order to directly introduce phosphorus ions into a polycrystalline silicon film when the polycrystalline silicon films 4 and 6 are formed. In this case, ion-implantation of phosphorus is not required after formation of a polycrystalline silicon film. Moreover, after formation of the polycrystalline silicon films 4 and 6 are effected, phosphorus ions may be brought into the films by diffusion of phosphorus ions using phosphorous oxytrichloride (POCl3) without ionimplantation of phosphorus. The polycrystalline silicon films 4 and 6 may be replaced with amorphous silicon films incorporated phosphorus ion and the amorphous silicon films are converted to polycrystalline silicon films in a later heat treatment for formation of an interlayer insulating film. In this case, grains formed in the heat treatment are disconnected from each other in a similar manner to the case where a polycrystalline silicon film is directly formed and grain boundary diffusion is prevented.
A second embodiment of the present invention will be described. FIGs. 8A to 8E are sectional views showing a method of fabricating a semiconductor device according to a second embodiment of the present invention in the order of steps. In the embodiment, first of all, as shown Fig. 8A, a silicon oxide film restricted to a particular one, but may be similar to the electrically conductive layer 8 formed in the first embodiment. Ion-implantation is conducted in the surface of the p-type semiconductor substrate 11 at a low concentration with the use of the gate electrode 18 and the silicon oxide film 12 as a mask. A spacer 21 is formed on a side of the gate electrode 18. Ion-implantation is conducted in the surface of the p-type semiconductor substrate 11 at a high concentration with the use of the gate electrode 18, the silicon oxide film 12 and the spacer 21 as a mask to form source/drain regions 19 in the surface of the p-type semiconductor substrate 11. A portion of the source/drain regions 19 under the space 21 is a region low in concentration. In next step, an interlayer insulating film 20 is formed all over the surface. A contact hole 22 is formed almost above the source/drain regions 19 by a photolithographic technique and a dry etching technique.
As shown in FIG. 8B, a first amorphous silicon film 14 in which phosphorus ions are incorporated is deposited to a thickness in the range of 50 to 100 nm all over the ptype silicon substrate 11 at a temperature of the substrate 11 between 500 and 550 OC by an LP-CVD method. Thereafter, the wafer is inserted again into an LP-CVD apparatus.
After deposition of the first amorphous silicon film 14, the wafer is cooled to a temperature near room temperature and subsequently taken out from an LP-CVD apparatus. The first amorphous silicon film 14 is exposed to the atmospheric air and a natural oxide film is formed on the surface of the first amorphous silicon film 14 as a diffusion preventing film 15, as shown in FIG. 8C. The wafer is inserted into the LP-CVD apparatus. A second amorphous silicon film 16 in which phosphorus ions are incorporated is deposited to a thickness roughly in the range of 50 to 100 nm on the diffusion preventing film 15 by the LP-CVD method. A silicon layer which contains a diffusion preventing film is formed of the first amorphous silicon film 14, the diffusion preventing film 15 and the second amorphous silicon film 16. If circumstances required, diffusion preventing films and amorphous silicon films iqcorporated phosphorus ion may be repeatedly formed.
As shown in FIG. 8D, a tungsten silicide film 17 is deposited to a thickness roughly in the range of 100 to 200 nm on the second amorphous silicon film 16 by the LP-CVD method using dichlorosilane (SiH2Cl2) gas and tungsten hexafluoride (WF8) gas. Phosphorus is then ion-implanted in the second amorphous silicon film 16 at a dose roughly in the range of 10l4 to 1018 (cm2) to decrease a resistance of the amorphous silicon film 16. It is important in the ionimplantation that an accelerating voltage is adjusted controlled so as not to give a damage to the diffusion preventing film 15 due to colliding of phosphorus ions to the diffusion preventing film 15.
Thereafter, as shown in FIG. 8E, patterning is performed on the tungsten silicide film 17, the second amorphous silicon film 16, the diffusion preventing film 15 and the first. amorphous silicon film 14 by a photolithographic technique and a dry etching technique, which are both commonly used, to form a electrically conductive layer 28 as upper layer wiring.
A device is completed by forming an interlayer insulating layer, wiring and the like, not shown, on the electrically conductive layer 28. The amorphous silicon films 14 and 16 are converted to polycrystalline silicon films in a heat treatment for formation of the interlayer insulating layer and the like.
In the embodiment, since the diffusion preventing film 15 is formed between the tungsten silicide film 17 and gate oxide film 13, fluorine atoms mixed in the tungsten silicide film 17 can be prevented from diffusing into the gate oxide film 13. Therefore, variation of a threshold value of a transistor can be avoided. Since polycrystalline silicon films are formed by giving a heat treatment to the amorphous silicon films 14 and 16, grain size becomes larger, compared with the case where a polycrystalline silicon film is directly formed. A resistance can be smaller with a larger grain size. Moreover, there is an effect that an amorphous silicon film can be formed to a smaller thickness, too.
In the first and second embodiments, while a tungsten silicide film is formed by an LP-CVD method, a tungsten film may be formed instead. As a method of forming a tungsten film, there is available an LP-CVD method using a mixed gas made of a mixture of tungsten hexafluoride gas and silane gas or a mixture of tungsten hexafluoride gas and hydrogen gas. In this case, it is not positively required to convert a tungsten film to a tungsten silicide film. Since coverage of a tungsten film is better than that of a tungsten silicide film, the former is more suitably applied to a finer contact hole.
In formation of a tungsten silicide film, the film may be formed using silane gas and tungsten hexafluoride gas by an LP-CVD method in a similar manner to the method described in the publication of Japanese Unexamined Patent Publication No. Hei 6-267973.
A third embodiment of the present invention will be described. FIGs. 9A to 9D are sectional views showing a method of fabricating a semiconductor device according to a third embodiment of the present invention in the order of steps. In the embodiment, as shown in FIG. 9A, first of all a silicon oxide film 32 for device isolation is formed on the surface of a p-type silicon substrate 31. A gate oxide film 33 with a thickness roughly of 6 to 20 nm is then formed in a region surrounded by the silicon oxide film 32.
A first amorphous silicon film 34 in which phosphorus ions are incorporated is deposited to a thickness in the range of 50 to 100 nm on the gate oxide film 33 by an LP-CVD method.
As shown in FIG. 9B, in a similar manner to the first embodiment, a diffusion preventing film 35 is formed on the surface of the first amorphous silicon film 34.
A second amorphous silicon film 36, in which phosphorus ions are incorporated, is, as shown in FIG. 9C, deposited to a thickness in the range of 50 to 100 nm on the diffusion preventing film 35 in a similar manner to the case where the first amorphous silicon 34 is deposited. A silicon layer having a diffusion preventing film is constructed from the first amorphous silicon film 34, the diffusion preventing film 35 and the second amorphous silicon film 36. A titanium film 37 is deposited to a thickness roughly in the range of 50 to 150 nm on the second amorphous silicon film 36 by a diode parallel plates plasma CVD method using titanium tetrachloride (TiC1,) gas and hydrogen (H2) gas. The operating conditions of the plasma CVD method are, for example, a temperature in the i , range of 500 to 600 OC, a high frequency of 450 kHz, an output power in the range of 300 to 500 W and a pressure in the apparatus of several hundreds of Pa.
As shown in FIG. 9D, The titanium film 37 is converted to a titanium silicide film 40 in a heat treatment conducted in an inert gas atmosphere made of an inert gas such as Ar gas, He gas, N2 gas or the like at a temperature in the range of 600 to 900 OC using a lamp annealer, a diffusion furnace or the like. Thereafter, under application a photolithographic technique and a dry etching technique, which are commonly used, patterning is conducted on the titanium silicide film 40, the second amorphous silicon film 36, the diffusion preventing film 35 and the first amorphous silicon film 34 to form an electrically conductive layer 38 for a gate electrode.
Arsenic is ion-implanted in the surface of the p-type semiconductor substrate 31 with the use of the conductive layer 38 and silicon oxide film 32 as a mask and a heat treatment is then given to activate arsenic ions and form source/drain regions 39 in the surface of the p-type semiconductor substrate 31.
Thereafter, an interlayer insulating film, wiring of the upper layer and the like, not shown, are formed and thereby a transistor is completed.
In the embodiment, since the diffusion preventing film 35 is formed between the titanium silicide film 40 and gate oxide film 33, chlorine atoms mixed in the titanium silicide film 40 can be prevented from diffusing into the I gate oxide film 33.
Since a resistance of the titanium silicide film is smaller than that of a tungsten silicide film, a resistance of wiring in this embodiment can be smaller than those in the first and second embodiments.
In the embodiment, while the titanium silicide film 40 is formed by effecting a heat treatment after formation of the titanium film 37, a titanium silicide film may be directly formed on the second amorphous silicon film 36. In the embodiment, the titanium film 37 is not required to be positively converted to a titanium silicide film.
In the embodiment, the diffusion preventing film may be made of a silicon nitride film in a similar manner to the first embodiment.
While in the first to third embodiments a silicon film adjoining the diffusion preventing film is made of either a polycrystalline silicon film or a amorphous silicon film in which phosphorus ions are incorporated, it should be noted that the invention is not restricted to these cases. As a silicon film adjoining the diffusion preventing film, there may be named an amorphous silicon film in which ions are not incorporated, a silicon film in a state between the amorphous state and the polycrystalline state and the like. The effect of the present invention can be also obtained in the use of one of such silicon films in which ions of boron or arsenic are incorporated.
An electrically conductive film formed on a silicon layer is not limited to one of a tungsten silicide film, a .
titanium silicide film, a tungsten film and a titanium silicide film but any film produced using a metal halide as raw material can exercise the effect of the present invention. For example, a tantalum (Ta) film may be formed using tantalum pentachloride (TaCl5) as raw material. A metal halide is not limited to a fluoride or a chloride.
For example, an iodide such as titanium iodide (TiI4) or the like may be used and other halides may be also used. In the cases where these raw materials are used, it can be prevented that atoms of an impurity such as fluorine atoms or chlorine atoms diffuse to the gate insulating film and diffusion layer, whereby a device with a good reliability can be obtained.
There is an effect that halogen atoms originated from a gas having a halogen atom which gas is a raw material gas other than a metal halide, for example dichlorosilane gas, is prevented from their diffusion, too. Moreover, there is an effect that diffusion of an impurity from a metal film and silicide film to a diffusion layer and silicon substrate is also prevented. Especially, in the second embodiment, diffusion from the tungsten silicide film 17 to the source/drain regions 19 is prevented and generation of a junction leakage current of the source/drain regions 19 which are diffusion layers is suppressed.
Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
The text of the abstract filed herewith is repeated here as part of the specification.
A gate insulating film is formed on a p-type silicon substrate. A first polycrystalline silicon film is deposited on the gate oxide film by an LP-CVD method. Phosphorus is ion-implanted in the first polycrystalline silicon film to make the first polycrystalline silicon film electrically conductive. A mixed gas containing oxygen gas is then supplied into an LP-CVD apparatus, to form an oxidative atmosphere in the apparatus to form an oxide film as a diffusion preventing film on the surface of the first polycrystalline silicon film. Thereafter, a second polycrystalline silicon film is deposited on the diffusion preventing film in a similar manner to the deposition of the first polycrystalline silicon film. A tungsten silicide film is deposited on the second polycrystalline silicon film by the LP-CVD method.
Phosphorus is ion-implanted in the second polycrystalline silicon film after passing through the tungsten silicide film, to make the second polycrystalline silicon film electrically conductive.

Claims (19)

What is claimed is:
1. A method of fabricating a semiconductor device comprising the steps of: forming a silicon layer on a semiconductor substrate, said silicon layer including a first silicon film on said semiconductor substrate: dn electrically conductive diffusion preventing film on said first silicon film, preventing passage of halogen atoms; a second silicon film on said diffusion preventing layer; and forming a film of one selected from the group consisting of silicide films and metal films on said silicon layer using a first raw material gas containing a metal halide gas by a vapor phase growth method.
2. A method of fabricating a semiconductor device according to claim 1, wherein the step of forming said silicon layer comprises the steps of: forming said first silicon film on said semiconductor substrate in a vapor phase growth apparatus, while a second raw material gas is supplied; supplying a third raw material gas containing oxygen gas into said vapor phase growth apparatus after the supply of said second raw material gas is stopped, to oxidize the surface of said first silicon film and thereby form said diffusion preventing film; and forming said second silicon film on said diffusion preventing film in said vapor phase growth apparatus after the supply of said third raw material gas is stopped, while a fourth raw material gas is supplied.
3. A method of fabricating a semiconductor device according to claim 1, wherein the step of forming said silicon layer comprises the steps of: forming said first silicon film on said semiconductor substrate in a vapor phase growth apparatus while a second raw material gas is supplied; supplying a third raw material gas containing ammonia gas into said vapor phase growth apparatus after the supply of said second raw material gas is stopped, to nitride the surface of said'first silicon film and thereby form said diffusion preventing film; and forming said second silicon film on said diffusion preventing film in said vapor phase growth apparatus after the supply of said third raw material gas is stopped, while a fourth raw material gas is supplied.
4. A method of fabricating a semiconductor device according to claim 1, wherein the step of forming said silicon layer comprises the steps of: forming said first silicon film on said semiconductor substrate in a vapor phase growth apparatus, while a second raw material gas is supplied; taking out said semiconductor substrate from said vapor phase growth apparatus after the supply of said second raw material gas is stopped, to expose said first silicon film to the atmospheric air and form said diffusion preventing film on the surface thereof by oxidation; and forming said second silicon film on said diffusion preventing film after said semiconductor substrate is inserted into a vapor phase growth apparatus, while a third raw material gas is supplied into said vapor phase growth apparatus.
5. A method of fabricating a semiconductor device according to claim 1, wherein said first raw material gas contains dichlorosilane gas and tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten silicide ,, film by a vapor'phase growth method.
6. A method of fabricating a semiconductor device according to claim 1, wherein said first raw material gas contains silane gas and tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten silicide film by a vapor phase growth method.
7. A method of fabricating a semiconductor device according to claim 1, wherein said first raw material gas contains titanium tetrachloride gas, and the step of forming said film by said vapor phase growth method has a step of forming a titanium silicide film by a vapor phase growth method.
8. A method of fabricating a semiconductor device according to claim 1, wherein said first raw material gas contains tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten film by a vapor phase growth method.
9. A method of fabricating a semiconductor device according to claim 1, wherein said first raw material gas contains titanium tetrachloride gas, and the step of forming said film by said vapor phase growth method has a step of forming a titanium film by a A vapor phase growth method.
10. A method of fabricating a semiconductor device according to claim 1, further comprising the step of patterning said silicon layer and said film formed by said vapor phase growth method to form a gate electrode.
11. A method of fabricating a semiconductor device according to claim 10, which further comprises the step of forming a gate oxide film on said semiconductor substrate before the step of forming said silicon layer.
12. A method of fabricating a semiconductor device according to claim 11, wherein the step of forming said silicon layer comprises the steps of: forming said first silicon film on said semiconductor substrate in a vapor phase growth apparatus, while a second raw material gas is supplied; supplying a third raw material gas containing oxygen gas into said vapor phase growth apparatus after the supply of said second raw material gas is stopped, to oxidize the surface of said first silicon film and thereby form said diffusion preventing film; and forming said second silicon film on said diffusion preventing film in said vapor phase growth apparatus after the supply of said third raw material gas is stopped, while a fourth raw material gas is supplied.
13. A method of fabricating a semiconductor device according to claim 11, wherein the step of forming said silicon layer comprises the steps of: forming said first silicon film on said semiconduqtor a a substrate in a vapor phase growth apparatus while a second raw material gas is supplied; supplying a third raw material gas containing ammonia gas into said vapor phase growth apparatus after the supply of said second raw material gas is stopped, to nitride the surface of said first silicon film and thereby form said diffusion preventing film; and forming said second silicon film on said diffusion preventing film in said vapor phase growth apparatus after the supply of said third raw material gas is stopped, while a fourth raw material gas is supplied.
14. A method of fabricating a semiconductor device according to claim 11, wherein said first raw material gas contains dichlorosilane gas and tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten silicide film by a vapor phase growth method.
15. A method of fabricating a semiconductor device according to claim 11, wherein said first raw material gas contains silane gas and tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten silicide film by a vapor phase growth method.
16. A method of fabricating a semiconductor device according to claim 11, wherein said first raw material gas contains titanium tetrachloride gas, and the step of forming said film by said vapor phase growth method has a step of forming a titanium silicide film by a vapor phase growth method.
17. A method of fabricating a semiconductor device according to claim 11, wherein said first raw material gas contains tungsten hexafluoride gas, and the step of forming said film by said vapor phase growth method has a step of forming a tungsten film by a vapor phase growth method.
18. A method of fabricating a semiconductor device according to claim 11, wherein said first raw material gas contains titanium tetrachloride gas, and the step of forming said film by said vapor phase growth method has a step of forming a titanium film by a vapor phase growth method.
19. A method of fabricating a semiconductor device substantially as herein described with reference to any of figures 4 to 9 of the accompanying drawings.
GB9722208A 1996-10-21 1997-10-21 Method of fabricating semiconductor device Expired - Fee Related GB2318451B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8277750A JPH10125617A (en) 1996-10-21 1996-10-21 Method of manufacturing semiconductor device

Publications (3)

Publication Number Publication Date
GB9722208D0 GB9722208D0 (en) 1997-12-17
GB2318451A true GB2318451A (en) 1998-04-22
GB2318451B GB2318451B (en) 1999-04-14

Family

ID=17587817

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9722208A Expired - Fee Related GB2318451B (en) 1996-10-21 1997-10-21 Method of fabricating semiconductor device

Country Status (3)

Country Link
JP (1) JPH10125617A (en)
KR (1) KR19980033022A (en)
GB (1) GB2318451B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2336717A (en) * 1998-04-20 1999-10-27 Nec Corp Gate electrode for a semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6376349B1 (en) * 2000-01-19 2002-04-23 Motorola, Inc. Process for forming a semiconductor device and a conductive structure
KR100370156B1 (en) * 2000-08-01 2003-01-30 주식회사 하이닉스반도체 method for manufacturing of semiconductor device
KR100426482B1 (en) * 2001-12-22 2004-04-14 주식회사 하이닉스반도체 Method of manufacturing a flash memory cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268027A1 (en) * 1986-11-17 1988-05-25 Spectrum CVD, Inc. Silicide to silicon bond
US5525540A (en) * 1993-12-13 1996-06-11 Nec Corporation Method for manufacturing silicon layer having impurity diffusion preventing layer
GB2314456A (en) * 1996-06-21 1997-12-24 Hyundai Electronics Ind Method of forming a polycide contact layer in a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268027A1 (en) * 1986-11-17 1988-05-25 Spectrum CVD, Inc. Silicide to silicon bond
US5525540A (en) * 1993-12-13 1996-06-11 Nec Corporation Method for manufacturing silicon layer having impurity diffusion preventing layer
GB2314456A (en) * 1996-06-21 1997-12-24 Hyundai Electronics Ind Method of forming a polycide contact layer in a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2336717A (en) * 1998-04-20 1999-10-27 Nec Corp Gate electrode for a semiconductor device
GB2336717B (en) * 1998-04-20 2000-11-08 Nec Corp Semiconductor device and method of making the same
US6297529B1 (en) 1998-04-20 2001-10-02 Nec Corporation Semiconductor device with multilayered gate structure

Also Published As

Publication number Publication date
KR19980033022A (en) 1998-07-25
GB2318451B (en) 1999-04-14
GB9722208D0 (en) 1997-12-17
JPH10125617A (en) 1998-05-15

Similar Documents

Publication Publication Date Title
US6562730B2 (en) Barrier in gate stack for improved gate dielectric integrity
US6784508B2 (en) Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
EP1349207B1 (en) Semiconductor device with copper wirings
US6602771B2 (en) Method for fabricating semiconductor device
US7396748B2 (en) Semiconductor device includes gate insulating film having a high dielectric constant
US6184073B1 (en) Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region
US6518113B1 (en) Doping of thin amorphous silicon work function control layers of MOS gate electrodes
KR19980070636A (en) Semiconductor device and manufacturing method thereof
KR20040105194A (en) Method of manufacturing a flash memory device
KR100192017B1 (en) Fabrication process of semiconductor device
US6699744B2 (en) Method of forming a MOS transistor of a semiconductor device
US5614745A (en) Contact structure between two conductive layers in semiconductor device and method of manufacturing the same
US6905980B2 (en) Semiconductor device and method of manufacturing same
JP2005158998A (en) Manufacturing method of semiconductor device
GB2318451A (en) Fabricating a semiconductor device
KR100314715B1 (en) Semiconductor element with thermally nitrided film on high resistance film and method of manufacturing the same
JPH10335640A (en) Semiconductor device and its manufacture
JP3228253B2 (en) Method for manufacturing semiconductor device
KR980011935A (en) Electrode Forming Method of Semiconductor Device
US6599820B1 (en) Method of producing a semiconductor device
US6893980B1 (en) Semiconductor device and manufacturing method therefor
JP2000082803A (en) Manufacture of semiconductor device
JP2814962B2 (en) Method for manufacturing semiconductor device
JPH06204456A (en) Semiconductor device
JPH04186733A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20041021