GB2305035A

GB2305035A - Open-drain SCSI driver with power-down protection

Info

Publication number: GB2305035A
Application number: GB9517220A
Authority: GB
Inventors: Johann Silvester Oberhauser
Original assignee: Motorola GmbH
Current assignee: Motorola Solutions Germany GmbH
Priority date: 1995-08-23
Filing date: 1995-08-23
Publication date: 1997-03-26
Also published as: GB9517220D0

Abstract

An open-drain bus driver, for example for coupling signals 25 from a device to an SCSI bus 15, is slew rate limited by Miller capacitor 28. The power supply potential of the device is fed to node 80 so that when the device is turned off the bus potential is fed through PMOS transistor 40 to turn on the clamping transistor 50. This prevents undesired turn-on of driver transistor 20 by capacitive coupling of bus signals to the gate of that device.

Description

INTERFACE CIRCUIT Field of the Invention This invention relates to interface circuits and particularly but not exclusively to bus interface circuits for connecting a device to a bus.

Background of the Invention A computer bus such as a Small Computer Serial Interface (SCSI) bus typically couples a number of devices to a computer. Each device coupled to the bus via an interface. The interface usually includes a transistor driven by the device and arranged to pull-down (or pull-up) the voltage on the bus.

Thus the devices operate on the bus in a wired-or configuration.

A problem with this arrangement is that if a device is switched off, it's physical connection to the bus is still in place. Without the influence of the device, the gate-drain capacitance associated with the interface transistor may provide enough charge at the gate terminal to turn-on the transistor, causing the interface to pull-down the voltage on the bus erroneously.

This invention seeks to provide an interface circuit which mitigates the above mentioned disadvantage.

Summary of the Invention According to the present invention there is provided an interface circuit, for connecting a bus to a device having an on and an off state, the circuit comprising: a driver transistor having first and second conducting terminals for coupling to the bus and to a reference potential respectively and a control terminal coupled for receiving signals from the device to drive the driver transistor; and, a clamp circuit coupled between the control terminal of the driver transistor and the reference potential, and arranged for selectively clamping the control terminal of the driver transistor to the reference potential, in response to the off state of the device; wherein during the off state, the clamp circuit clamps the driver transistor.

In this way when the device is switched off, the transistor is prevented from being turned on, ensuring that the interface has no influence on the bus.

Brief Description of the Drawing An exemplary embodiment of the invention will now be described with reference to the drawing of FIG. 1 which shows a preferred embodiment of an interface circuit in accordance with the invention.

Detailed Description of a Preferred Embodiment Referring to FIG. 1, there is shown an interface circuit 10, having a bus terminal 15 for connecting to a bus (not shown), for example a smallcomputer serial interface (SCSI) bus. The interface circuit 10 also has a device terminal 25, for receiving signals from the device (not shown).

A driver transistor 20 has a drain terminal 22 connected to the bus terminal 15, a source terminal 24 connected to a reference potential 70 (ground) and a gate terminal 26 coupled to receive signals from the device through the device terminal 25. In this way the driver transistor is arranged to selectively couple the bus terminal 15 to the reference potential 70 in response to the received signals.

The driver transistor has an inherent capacitance between the drain terminal 22 and the gate terminal 26. In addition capacitor 28, coupled between the drain terminal 22 and the gate terminal 26 augments the inherent capacitance in providing slew-rate control to reduce the switching speed of driver transistor 20.

A clamp circuit 30 of the interface circuit 10 comprises a transmission gate 40 and a pair of transistors 50 and 60. The transmission gate 40 has a first conducting terminal coupled to the bus terminal 15, a second conducting terminal having a coupling to be further explained below and a control terminal coupled to a supply voltage terminal 80. The supply voltage terminal 80 is coupled to the supply rail of the device (not shown) and has a voltage Vdd when the device is switched on, and a voltage equal to the reference potential when the device is switched off.

The first transistor 50 has a drain terminal coupled to the gate terminal 26 of the driver transistor 20, a source terminal coupled to the reference potential and a gate terminal coupled to the second conducting terminal of the transmission gate 40.

The second transistor 60 has a drain terminal coupled to the second conducting terminal of the transmission gate 40, a source terminal coupled to the reference potential and a gate terminal coupled to the supply voltage terminal 80.

In operation, the device (for example a hard disk drive) may be switched on or off by a user, depending upon the user's requirements. In the case of a typical prior art interface having a driver transistor, the gate terminal of the driver transistor receives signals from the device which selectively turn the driver transistor on and off, thereby driving the bus.

However, when the device is off, the gate terminal of the driver transistor is left floating and the gate-drain capacitance associated with the driver transistor may lead to the gate terminal having a voltage higher than the threshold voltage, thereby resulting in the driver transistor being switched on and driving the bus, even though the device is switched off.

In the present invention, this problem is overcome in the following way.

When the device is switched on, signals received at the device terminal 25 control the driver transistor 20 via the gate terminal 26 as before. With the device switched on, the supply voltage terminal 80 has a voltage of Vdd, causing the transmission gate 40 to be switched off. The second transistor 60 is switched on, in turn causing the first transistor 50 to be switched off, by coupling the gate input thereof to the reference potential 70. In this way the clamp circuit 30 is disabled when the device is switched on.

When the device is switched off, there are no signals received at the device terminal 25, and the driver transistor 20 should be switched off. With the device switched off, the supply voltage terminal 80 has a voltage equal to the reference potential 70, causing the transmission gate 40 to be switched on and the second transistor 60 to be switched off. Therefore voltage is drawn from the bus terminal 15, through the transmission gate 40 and the gate terminal of the second transistor, turning it on. In this way the clamp circuit 30 clamps the gate terminal 26 of the driver transistor 20 to the reference potential 70, ensuring that the driver transistor 20 is switched off when the device is switched off.

It will be appreciated by a person skilled in the art that alternative embodiments to that described above are possible. For example, the clamp circuit 30 could comprise an alternative arrangement to the transmission gate 40 and first and second transistors 50 and 60 described above.

Furthermore, the driver transistor 20 could be arranged to selectively couple the bus terminal 15 to a reference potential not equal to ground.

Claims

1. An interface circuit, for connecting a bus to a device having an on and an off state, the circuit comprising: a driver transistor having first and second conducting terminals for coupling to the bus and to a reference potential respectively and a control terminal coupled for receiving signals from the device to drive the driver transistor; and, a clamp circuit coupled between the control terminal of the driver transistor and the reference potential, and arranged for selectively clamping the control terminal of the driver transistor to the reference potential, in response to the off state of the device; wherein during the off state, the clamp circuit clamps the driver transistor.

2. The interface circuit of claim 1 wherein the clamp circuit is powered from the bus.

3. The interface circuit of claim 1 or claim 2 wherein the clamp circuit includes a transmission gate and two transistors.

4. The interface circuit of claim 3 wherein the transmission gate is coupled to be switched on when the device is in the off state.

5. The interface circuit of claim 3 or claim 4 wherein one of the two transistors is arranged to selectively couple the control terminal of the driver transistor to the reference potential.

6. The interface circuit of any preceding claim wherein the reference potential is ground.

7. An interface circuit substantially as hereinbefore described with reference to the drawing.