GB2298657A - Forming metal interconnects with phase transformed titanium nitride layers - Google Patents

Forming metal interconnects with phase transformed titanium nitride layers Download PDF

Info

Publication number
GB2298657A
GB2298657A GB9604614A GB9604614A GB2298657A GB 2298657 A GB2298657 A GB 2298657A GB 9604614 A GB9604614 A GB 9604614A GB 9604614 A GB9604614 A GB 9604614A GB 2298657 A GB2298657 A GB 2298657A
Authority
GB
United Kingdom
Prior art keywords
accordance
titanium nitride
layer
titanium
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9604614A
Other versions
GB9604614D0 (en
GB2298657B (en
Inventor
Gyung S Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9604614D0 publication Critical patent/GB9604614D0/en
Publication of GB2298657A publication Critical patent/GB2298657A/en
Application granted granted Critical
Publication of GB2298657B publication Critical patent/GB2298657B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

Description

-. 'D 1 a 2298657 14ETEODS OF FORbaNG METAL INTERCONNECTS IN SEMICONDUCTOR
DEVICES
FIELD OF TEE INVENTION
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a metal interconnect in a semiconductor device including a diffusion barrier metal layer.
DESCRIPTION OF TEE PRIOR ART
As the integration of semiconductor device is increased, many methods have been studied to make the interconnect design free and easy, and to make the designation of resistance and current capacitance variable.
In general, aluminum is widely used as the material for metal interconnect of semiconductor device. As the integration is increased, the width of the interconnect is fine, so the current density is increased. The increase of the current density, however, generates failure due to elect romigration, anti-reflection and movement of stress, which results in a drop in the reliability. To solve the above problem, a method that deposits copper(Cu) or titanium(Ti) on the interconnect of aluminum(Al) has been provided, but it leads to serious problems such as the failure of insulator and a short of interconnects due to L phenomena such as hillock and whisker.
Fig. 1 a sectional view of semiconductor device forming the metal interconnect after the formation of the diffusion barrier layer according to an embodiment of the conventional art. In the conventional method, an insulating layer 2 is first formed on a semiconductor substrate 1. Afterwards, contact holes are formed at the predetermined portions of the semiconductor substrate 1 by etching some portions of the insulating layer till the surface of the substrate 1 is exposed. Next, diffusion i5 barrier layers of titanium(Ti) 3 and titanium nitride(TiN) 4 are orderly formed by Physical Vapor Deposition.
Lastly, metal interconnect 8 using aluminum metal or aluminum alloy is formed on the Titanium Nitride layer 4.
Currently, however, as high integration of device proceeds, the size of the contact hole is more and more decreased. In proportion to the decrease of the contact hole size, the aspect ratio of the contact hole is increased. Accordingly, in a case where the diffusion barrier layers are formed by Physical Vapor Deposition as above, the step coverage is decreased resulting in the diffusion barrier layer being deposited unevenly.
Moreover, in a case where the thickness of the barrier layer is increased, a shadow effect is generated at the corner of the upper portion of the contact hole, making it impossible for the succeeding process to proceed. In addition, in a case where the Chemical Vapor Deposition method, in which TiC14 reacts on NH3. is used to enhance 2 1 - j the step coverage, there is a problem in the excess generation of particles. Therefore, the result is a drop in the yield and reliability of the devices. Furthermore, in this case, there is a problem in reducing the speed of the device because the inner resistance of it is increased by the phase transformation to the amorphous phase during the deDosition of TA.
SM^RY OF TEM INVMTION Accordingly, the object of the present invention is to provide a method of forming the metal interconnect of semiconductor device, which can enhance the yield and reliability of a semiconductor device by increasing the step coverage of the diffusion barrier layer and decreasing the inner resistance and the particle aeneration thereof.
To accomplish the object of the invention, first contact hole is formed at the predetermined portion of semiconductor substrate which active regions are formed in and then insulating layer is formed on. Afterwards, Titanium and Titanium Nitride layers each having a predetermined thickness are orderly deposited on the contact hole and the insulating layer by Chemical Vapor Deposition. Next, thermal annealing is performed in an atmosphere of nitrogen,-4n order to change the phase of the deposited Titanium Nitride layer and the content of NZ in each laver transformed. Lastly, the metal interconnect is formed to 3 connect the active regions to each other by depositing a interconnecting metal having 1OW resistivity on the diffusion barrier layers and afterwards, patterning of all layers is formed on the contact hole and insulating layer.
1m - Alternatively, it is also possible that the present invention further comprises of a step for depositing an arc-thin film which prevents the reflection of light on the interconnecting metal before the patterning of the formed layers occurs.
BRIEF DESCRIPTION OF TEE DRAWINGS
Fig. 1 is a sectional view for illustrating a method is of forming the metal interconnect according to the conventional embodiment.
Figs. 2A to 2D are sectional views, showing sequential processes of forming the metal interconnect, according to an embodiment of the present invention, respectively.
DETAILED DESCRIPTION OF TEE PRESENT INVENTION
Hereinbelow, a preferred embodiment of the present invention is illustrated referring to Figs. 2A to 2D.
Figs. 2A TO 2D are sectional views showing sequential processes for forming a metal interconnect according to an embodiment of the present invention.
4 First, referring to Fig. 2A, an insulating layer 2 is deposited on a semiconductor substrate 1 including active regions. A contact hole is then formed at the predetermined portion of the insulating layer 2 by photolithographic method which etches the exposed insulating layer till the surface of the semiconductor substrate 1 is exposed. Then, as shown in Fig. 2B, a Titanium layer 3 is deposited on the inner portion of the contact hole and the whole surface of the insulating layer 2. The Titanium layer 3 is very thinly f ormed to a degree capable of maintaining the shape of the contact hole 2 by Chemical Vapor Deposition which react TLiCl4 with NH3 or NF3. The Chemical Vapor Deposition method is to enhance the step coverage of the inside of the contact hole. Then, a Titanium Nitride layer 4 is formed on the Titanium layer 3. The Titanium Nitride layer 4 is formed by Chemical Vapor Deposit'-on to depress the generation of the particles. in other words, the method uses the raw material of only tetradimethyl-aminotitanium (Ti(N(CH3)2141 or tetradiethylaminotitanium (Ti(N(C2Hs)4H. and decomposes Titanium Nitride 'from one of said two compounds by thermal annealing wherein, the supplied gas is Nitrogen and/or Helium. The deposition temperature of the TiN rances from 300 to 500 C and the pressure of the furnace is controlled to the range from 5 to 10 mTorr.
What is -Formed "s an amorohous laver. Afterwards, the semiconductcr substrate which the above lavers were formed on, is thermally annealed in an atmosphere of nitrogen for the temperature 1 ^ l J range of 400 to 600 OC. Through the annealing process, the titanium nitride layer 4 is transformed to three titanium nitride layers 5, 6, 7 whose physical properties are different from one another. The lower or first layer is composed of titanium nitride 5 that exists as an amorphous layer, the middle or second layer is composed of titanium nitride 6 that exists as a crystalline layer, and the upper or third layer is composed of titanium nitride 7 that exists as a nitrogen-rich crystalline layer. Here, the Rapid Thermal Annealing (RTA) method can also be used on behalf of the conventional thermal annealing. it is performed at the temperature range of 700 to 900C and in the time range of 10 to 30 seconds. Titanium nitride 4 of single layer has very high resistance because it is in an amorphous state, but the triple layer of titanium nitride 5,6,7 has a low resistance compared with the single layer titanium nitride 4 because its physical properties are different from one another. The titanium layer 3 and titanium nitride layers 5, 6, 7 act as diffusion barrier metal for preventing the diffusion of metal atoms which would occur without the existence of the barrier.
Afterwards, as shown in Fig. 2C, a interconnecting metal such as aluminum, copper, or alloy of aluminum and copper etc., is formed on the diffusion barrier layer, wherein the interconnecting metal connects the active regions to each other by depositing any metal having a low resistivity on the diffusion barrier layers. Afterwards, Z -, 6 2 ^ an arc-metal layer 9 is formed on the metal layer 8 by Chemical Vapor Deposition. Here, the arc-metal layer is to prevent the light from reflecting on the interconnecting metal when light is exposed performed to form a pattern of interconnect. The arc-thin film is comDosed of the metal tetradimethylaminotitanium or tetradiethylaminotitanium, and the range of the deposition temperature is from 300 to 450"C. The step f or f orming the arc-thin f ilm 9 can be deleted according to-each case.
Lastly, as shown in Fig. 2D, the metal interconnect is f ormed by patterning said metal layers 3, 5, 6, 7,. 8, 9. The metal layer 8 can be substituted for a metal having high conductivity such as Tungsten.
As previously described in detail, the present invention can reduce the resistance of titanium nitride and the generation of particles, and enhance the step coverage by transforming titanium nitride of a single layer to titanium nitride of three layers having individual properties. The three layers are formed through a method that consists of forming titanium nitride by thermal decomposition of the raw material including nitroaen and titanium, and annealing the deposited titanium nitride in an atmosphere of nitrogen. Accordingly, it provides effects enhancing not only the reliability and yield but also the speed of the signal transfer.
other features, advantages and embodiments of the invention jisclosed herein will be readily apparent to those exercisina ordinary skill after reading the 7 foregoing disclosures. In this regard, while specific embodiments of the invention have been described in considerable detail, variations and modifications of these embodiments can be effected without departing from the spirit and scope of the invention as described and claimed.
9

Claims (11)

WRAT IS CLAIM= IS:
1. A method of forming a metal interconnect for semiconductor devices comprising the steps of: forming a contact hole at a predetermined portion of a semiconductor substrate on which an insulating layer is formed; depositing titanium and titanium nitride layers, each having a predetermined thickness, on said insulatina layer said contact hole in an order by Chemical Vapor Deposition; thermally annealing said substrate in an atmosphere of nitrogen wherein said titanium nitride layer is phasetransformed to titanium nitride layers which each layers has other nitrogen depositing a metal layer having low resistivity on Jde.layer; and k-he titanium nitrpatterning the layers formed on the contact hole and insulating layer till now.
2. The method in accordance with claim 1, wherein said titanium _Js formed by chemical vapor jerPosition which reacts TiC14 with NH3.
3. The -nethod in accordance with claim 1, wherein said titanium nitride is formed bv thermal decomposition of letradimethylaminoritanium.
9
4. The method in accordance with. claim 1, wherein said titanium nitride is formed by thermal decomposition of Tetradiethylaminotitanium.
.S
5. The method in accordance with claim 3, wherein said thermal decsition is performed at a condition of temperature of 300 to 500 OC, pressure of 5 to 10 mTorr.
6. The method in accordance with claim 4, wherein said thermal decomposition is performed at a condition,, of temperature of 300 to 500 'C, pressure of 5 to 10 mTorr.
7. The method in accordance with claim 1, wherein said thermal annealing for phase transformation of titanium nitride is performed in an atmosphere of nitrogen and temperature of 400 to 600 0 C for 30 to 60 minutes.
8. The method in accordance with claim 1, wherein said zo thermal annealing for phase transformation of titanium nitride is performed in an atmosphere of nitrogen, temperature of 700 to 9000C for 10 to 30 seconds by rapid thermal annealing.
9. The method in accordance with claim 1, wherein said interconnecting metal is aluminum or copper.
10. The method in accordance with claim 9, wherein said arc-thin film is made of titanium.
10. The method in accordance with claim 9, wherein said method further comprises a step of forming arc-thin film for preventing reflection by copper or aluminum before the patterning step of forming said metal interconnect.
z
11. The method in accordance with claim 10, wherein said arc-thin film is made of titanium.
12. The method in accordance with claim 10, wherein said titanium nitride is formed by thermal decomposition of Tetradiethylaminotitanium at 300 to 450 OC.
13. The method in accordance with claim 10, wherein said titanium nitride is formed by thermal decomposition of Tetradimethylaminotitanium at 300 to 450 C.
IL Amendments to the claims have been filed as follows A method of forming a metal interconnect for a semiconductor device, comprising the steps of forming a contact hole in an insulating layer formed on a semiconductor substrate; depositing titanium and then titanium nitride layers, each having a predetermined thickness, on said insulating layer and in said contact hole by chemical vapor deposition; thermally annealing said substrate in an atmosphere of nitrogen and/or helium, wherein said titanium nitride layer is phase-transformed to plural titanium nitride layers each of which layers has different nitrogen and/or heliurn content and a different phase state; depositing a metal layer having low resistivity on the titanium nitride layer, and patterning the layers formed on the contact hole and insulating layer.
2. The method in accordance with claim 1, wherein said titanium layer is formed by chemical vapor deposition which reacts TiChwith NH3.
3. The method in accordance with claim 1, wherein said titanium nitride is formed by thermal decomposition of tetradimethylaminotitanium.
4. The method in accordance with claim 1, wherein said titanium nitride is formed by thermal decomposition of tetradiethylaminotitanium.
5. The method in accordance with claim 3 or 4, wherein said thermal decomposition is performed at a condition of temperature of 300 to SOOT, pressure of 5 to 10 mtorr.
3 6. The method in accordance with claim 1, wherein said thermal annealing of titanium nitride is performed in the atmosphere of nitrogen and/or helium, at a temperature of 400 to 600C for 30 to 60 minutes.
7. The method in accordance with claim 1, wherein said thermal annealing of titanium nitride is performed in the atmosphere of nitrogen and/or helium, at a temperature of 700 to 900'C for 10 to 30 seconds by rapid thermal annealing.
8. The method in accordance with claim 1,3 or 4, wherein said metal layer is aluminum or copper.
9. The method in accordance with claim 8, wherein said method further comprises a step of forming a thin antireflective coating (arc) film on said metal layer for preventing reflection of light from said metal layer before said patterning step.
GB9604614A 1995-03-04 1996-03-04 Methods of forming metal interconnects in semiconductor devices Expired - Fee Related GB2298657B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950004447A KR0148325B1 (en) 1995-03-04 1995-03-04 Formation method of metal layer in semiconductor device

Publications (3)

Publication Number Publication Date
GB9604614D0 GB9604614D0 (en) 1996-05-01
GB2298657A true GB2298657A (en) 1996-09-11
GB2298657B GB2298657B (en) 1998-09-30

Family

ID=19409231

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9604614A Expired - Fee Related GB2298657B (en) 1995-03-04 1996-03-04 Methods of forming metal interconnects in semiconductor devices

Country Status (6)

Country Link
JP (2) JPH08250596A (en)
KR (1) KR0148325B1 (en)
CN (1) CN1057868C (en)
DE (1) DE19608208B4 (en)
GB (1) GB2298657B (en)
TW (1) TW288171B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6569751B1 (en) * 2000-07-17 2003-05-27 Lsi Logic Corporation Low via resistance system
US7518247B2 (en) 2002-11-29 2009-04-14 Nec Corporation Semiconductor device and its manufacturing method

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430684B1 (en) * 1996-12-31 2004-07-30 주식회사 하이닉스반도체 Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer
JP3040715U (en) * 1997-02-19 1997-08-26 株式会社熊谷 Packaging bag
KR100480576B1 (en) * 1997-12-15 2005-05-16 삼성전자주식회사 Forming method of metal wiring in semiconductor device
KR100494320B1 (en) * 1997-12-30 2005-08-31 주식회사 하이닉스반도체 Diffusion prevention film formation method of semiconductor device
KR100559028B1 (en) * 1998-12-29 2006-06-15 주식회사 하이닉스반도체 Copper wiring formation method of semiconductor device
KR100495856B1 (en) * 1998-12-30 2005-09-02 주식회사 하이닉스반도체 Copper metal wiring formation method of semiconductor device
JP3562628B2 (en) * 1999-06-24 2004-09-08 日本電気株式会社 Diffusion barrier film, multilayer wiring structure, and method of manufacturing the same
DE10154500B4 (en) * 2001-11-07 2004-09-23 Infineon Technologies Ag Process for the production of thin, structured, metal-containing layers with low electrical resistance
JP4222841B2 (en) * 2003-01-15 2009-02-12 三洋電機株式会社 Manufacturing method of semiconductor device
TW200526806A (en) * 2004-01-15 2005-08-16 Tokyo Electron Ltd Film-forming method
US7253501B2 (en) * 2004-08-03 2007-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. High performance metallization cap layer
US20060113675A1 (en) * 2004-12-01 2006-06-01 Chung-Liang Chang Barrier material and process for Cu interconnect
JP5204964B2 (en) * 2006-10-17 2013-06-05 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN101017793B (en) * 2007-02-16 2013-06-05 上海集成电路研发中心有限公司 A making method for diffusing blocking layer
CN101459174B (en) * 2007-12-13 2010-07-07 和舰科技(苏州)有限公司 Conductive structure for semiconductor chip and its producing method
CN102810504A (en) * 2011-05-31 2012-12-05 无锡华润上华半导体有限公司 Process for growing thick aluminium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209654A2 (en) * 1985-05-13 1987-01-28 Kabushiki Kaisha Toshiba Semiconductor device having wiring electrodes
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
EP0514103A1 (en) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Barrier metal process for sub-micron contacts
EP0525637A1 (en) * 1991-07-24 1993-02-03 Applied Materials, Inc. Method for the formation of tin barrier layer with preferential (111) crystallographic orientation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0174743A3 (en) * 1984-09-05 1988-06-08 Morton Thiokol, Inc. Process for transition metal nitrides thin film deposition
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
EP0448763A1 (en) * 1990-03-30 1991-10-02 Siemens Aktiengesellschaft Process and apparatus for manufacturing conductive layers or structures for highly integrated circuits
US5308655A (en) * 1991-08-16 1994-05-03 Materials Research Corporation Processing for forming low resistivity titanium nitride films
US5462895A (en) * 1991-09-04 1995-10-31 Oki Electric Industry Co., Ltd. Method of making semiconductor device comprising a titanium nitride film
JPH05121378A (en) * 1991-10-29 1993-05-18 Sony Corp Method of manufacturing semiconductor device
US5254499A (en) * 1992-07-14 1993-10-19 Micron Technology, Inc. Method of depositing high density titanium nitride films on semiconductor wafers
JP2570576B2 (en) * 1993-06-25 1997-01-08 日本電気株式会社 Method for manufacturing semiconductor device
US5494860A (en) * 1995-03-14 1996-02-27 International Business Machines Corporation Two step annealing process for decreasing contact resistance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209654A2 (en) * 1985-05-13 1987-01-28 Kabushiki Kaisha Toshiba Semiconductor device having wiring electrodes
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
EP0514103A1 (en) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Barrier metal process for sub-micron contacts
EP0525637A1 (en) * 1991-07-24 1993-02-03 Applied Materials, Inc. Method for the formation of tin barrier layer with preferential (111) crystallographic orientation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6569751B1 (en) * 2000-07-17 2003-05-27 Lsi Logic Corporation Low via resistance system
US7518247B2 (en) 2002-11-29 2009-04-14 Nec Corporation Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JPH08250596A (en) 1996-09-27
JP2000082742A (en) 2000-03-21
JP3122845B2 (en) 2001-01-09
CN1141506A (en) 1997-01-29
KR960035843A (en) 1996-10-28
DE19608208A1 (en) 1996-09-05
GB9604614D0 (en) 1996-05-01
CN1057868C (en) 2000-10-25
KR0148325B1 (en) 1998-12-01
DE19608208B4 (en) 2006-02-23
GB2298657B (en) 1998-09-30
TW288171B (en) 1996-10-11

Similar Documents

Publication Publication Date Title
GB2298657A (en) Forming metal interconnects with phase transformed titanium nitride layers
US5356836A (en) Aluminum plug process
EP0735586B1 (en) Semi-conductor structures
US4630357A (en) Method for forming improved contacts between interconnect layers of an integrated circuit
JP2845788B2 (en) Contact hole plug formation method
JPH07307385A (en) Formation of multilayer metal wiring of semiconductor element
US6331482B1 (en) Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization
JPH06181212A (en) Manufacture of semiconductor device
US20010036734A1 (en) Method of formation of conductive lines on integrated circuits
JP2004000006U6 (en) Semiconductor device
KR970003717B1 (en) Method of forming the metal wiring on the semiconductor device
KR100253385B1 (en) The manufacturing method of the interconnection layer for semiconductor device
JPH07135188A (en) Manufacture of semiconductor device
US5798300A (en) Method for forming conductors in integrated circuits
JPH10125785A (en) Method of forming wiring of semiconductor integrated circuit
JP3328358B2 (en) Method for manufacturing semiconductor device
JP3109269B2 (en) Method for manufacturing semiconductor device
US4992152A (en) Reducing hillocking in aluminum layers formed on substrates
KR100414745B1 (en) Method for forming metal interconnection of semiconductor device
KR19980060592A (en) Metal wiring formation method of semiconductor device
US6316355B1 (en) Method for forming metal wire using titanium film in semiconductor device having contact holes
KR0183772B1 (en) Forming method of titanium nitride thin film
US6350676B1 (en) Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers
KR100324020B1 (en) Metal wiring formation method of semiconductor device
KR100252764B1 (en) Method for fabricating multi-layer metallization in semiconductor device

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20070304