GB2296618A - Digital video decoding system requiring reduced memory space - Google Patents
Digital video decoding system requiring reduced memory space Download PDFInfo
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- GB2296618A GB2296618A GB9426431A GB9426431A GB2296618A GB 2296618 A GB2296618 A GB 2296618A GB 9426431 A GB9426431 A GB 9426431A GB 9426431 A GB9426431 A GB 9426431A GB 2296618 A GB2296618 A GB 2296618A
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- video decoding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/59—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
- H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
- H04N19/428—Recompression, e.g. by spatial or temporal decimation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
A digital video decoding system which lowers the requirement of memory space when a high resolution still picture signal is decoded, comprises a decompressing unit 603 which recovers reconstruction block data from the received compressed data when a full motion video signal (eg MPEG signal) is decoded, but recovers subsampling block data 608 from the compressed data when a high resolution still picture is decoded; a frame memory 604 which temporarily stores reconstruction block data or subsampling block data, both of these data are called image block data; and a display unit 605 which recovers decompressed frames from the image block data using an interpolation and filtering circuit. The subsampling circuit 608 is only enabled 606 when a high resolution still picture signal is being decoded. <IMAGE>
Description
SYSTEM AND METHOD FOR DIGITAL VIDEO DECODING
BACKGROUND OF THE INVENTION: Ddscrittion of the Prior Art
In digital video decoding system, a great amount of memory space is needed as temporary storage area for the reconstructed image and a small amount of memory space is used as compressed data buffer. Fig.1 shows a block diagram of a digital video decompressing system appeared in typical prior art. The compressed video data is put into an input unit 101, and then output to a memory unit 100, wherein a compressed data buffer 102 and a frame memory 104 are included.Said compressed data buffer 102 is a temporary storage area for the compressed video data coming from the input unit 101 to be decompressed, whereas the frame memory 104 is used for storage the reconstructed pictures which are used as the referenced pictures needed for decoding and as the final display pictures. A decompression unit 103 decompresses the data coming from the compressed data buffer 102 and creates the data for recovering image pictures; these data are then stored in the frame memory 104. Said data is further output and processed by the display unit 105. In the course of decoding, the input unit 101, decompression unit 103 and display unit 105 respectively controls the storing/retrieving of the memory unit 100, for inputting and calculating the compressed video data as well as the display of the reconstructed pictures.
The size requirement of the memory space of said memory unit 100 is related to the video compressing algorithm and the picture resolution. Generally, MPEG is used as video compressing algorithm for viedeo CD, thereof the full motion video is constructed by the picture resolution of the source input format (SIF), as for the still picture resolution, other than that of SIF format, another high resolution still picture is also applicable. The so-called high resolution means that the resolution of the pictures is twice as much as that of the SIF format both in horizontal and vertical directions, i.e., the number of pixel of a picture of high resolution equals to the total numbers of that of four SIF-format pictures.
Said MPEG is an international standard of a digital motion video compression. The data structre type of motion video compression and the procedure of its decompression are defined in MPEG. There are 352 x 240 or 352 x 288 pixels in the picture resolution of SIF. In
MPEG, the colors of pixels are indicated by Y, Cb,
Cr(4:1:1). Each pixel needs one byte to represent luminance Y and 1/4 byte each to represent chrominance Cb and Cr. Hence, the largest memory space required for each picture of SIF format is: 352 x 288 = 99 K bytes for the luminance Y element, and 24.75 K bytes each for the chrominance Cb and Cr elements respectively. The distribution of the memory for the memory spaces of Y element, Cb element and Cr element is shown in Fig. 2 as 201,202,and 203 etc. respectively.
Fig. 3 shows a data hierarchy in MPEG system. A video sequence 301 includes many groups of pictures 302 each including many picutres 303, a picture 303 further includes many slices 304. A slice 304 is divided into many macroblocks 305 and each macroblock 305 is further divided into many blocks 306 each block represents a Y or Cb or Cr element of B x 8 pixels. In
MPEG, the display order of pictures is shown in Fig.
4A while its compressed video stream order is shown In
Fig. 4B. In MPEG, the pictures of Fig. 4A are recovered through the MPEG decoding system from the video stream of Fig. 4B by storing the referenced pictures in the memory wherein I represents Intra
Picture that can be recovered without refering to any picture, P represents Predictive Picture which can be recovered only by refering to previous I picture or P picture, and B represents Bidirectionally Predictive
Picture that can be recovered by refering to the past and future I pictures or P pictures neighboring on each side as shown in Fig. 4C. In Fig. 4, I and P are the referenced pictures stored in the memory after recovering while B is the picture recovered by refering to the two referenced pictures.Therefore, when the decompressing system in Fig. 1 proceeds with the full motion video decoding , frame memory 104 must keep two recovered pictures to be the referenced pictures for decompression, in the meanwhile, it also requires an area for storing the recovering B pictue and thus requires a memory space to store at least 3 pictures, i.e., 445.5 K bytes. A 4M (Mega) bits (512 bytes) DRAM of industrial standard is usually used to serve as the memory unit 100 in Fig.1. Other than satisfying the need of frame memory 104, it still has 66.5 K bytes left for compressed data buffer 102. When the still pictures of high resolution is being decoded by the system as shown in Fig. 1, because the still pictures all use intracoding, steps as shown in Fig. 4 need not take place in frame memory 104.But, since the pixels of a high resolution picture are 4 times as much as that of SIF pictures, it needs 4 times the memory space as shown in
Fig. 5. FY 501 (396 K bytes) is the memory space for Y luminance element, FCb 502 (99 K bytes ) and FCr 503 (99
K bytes) are the memory spaces for Cb and Cr chrominance elements respectively. The total memory space of FY 501,
FCb 502 and FCr 503 is 594 K bytes which is over the capacity of a 4M bits DRAM. Thus, memory space has to be added to satisfy the requirement of memory unit 100 in the high resolution still picture decoding. This shortcoming has resulted in higher cost of the system hardware.
SUMMARY OF THE PRESENT INVENTION:
It is therefore an object of the present invention to provide a digital video decoding system and method to overcome the aforementioned difficulties encountered in the prior art.
Specifically, it is an object of the present invention to provide a digital video decoding system and method to reduce the cost of system hardware and limit the requirement of the memory unit to a 4M bits DRAM when the full motion video decoding or high resolution still picture decoding are in process.
To reach this goal, the present invention offers a digital video decoding system which can decode the compressed video data and output the decompressed frames. Said system includes at least (1) a reconstruction block buffer used to temporarily store the RB (Reconstruction Block) data recovered from the compressed video data; (2) a subsampling device having an EN (enable) control signal, when the digital video decoding system is processing the high resolution still picture decoding, said EN control signal is under an enabling state, and makes a horizontal subsampling to the RB data and then outputs the SB (Subsampling Block) data; and when the full motion video decoding is in process, the EN control signal is off the enabling state and passes the RB data through the subsampling device without subsampling; (3) a frame memory used for storing the RB data or SB data, said two kinds of data are all called IB(Image Block) data; (4) a display buffer device used for transforming the IB data output from the frame memory to SL (Scanning Line) data; and (5) an interpolation and filtering device that interpolates and filters the SL data, outputs the IFL(Interpolation and
Filtering Scanning Line)data, and transforms the IFL data to the decompressed frames.
BRIEF DESCRIPTION OF THE DRAWINGS:
Fig. 1 shows a function block diagram related to the digital video decoding system appeared in prior art;
Fig. 2 shows a memory distribution diagram of the frame memory while the system processes full motion video decoding;
Fig. 3 shows a data hierarchy in MPEG system.
Fig. 4A, B, and C show diagrams of video decoding and display order, and picture prediction in the MPEG system;
Fig. 5 shows a memory distribution of the frame memory while the system processes high resolution still picture decoding;
Fig. 6 shows a function block diagram of a digital video decoding system in the present invention;
Fig. 7 shows a memory distribution diagram of the frame memory while the digital video decoding system according to the present invention proceeds high resolution still picture decoding;
Fig. 8 shows a procedure of horizontally subsampling the RB data;
Fig. 9 shows a diagram illustrating the horizontal interpolation and filtering of the SL data; and
Fig. 10 shows a flow chart of the present invention.
DETAILED DESCRIPTION OF THE~PREEARRED INVENTION Fig. 6 shows a funtion block diagram of this invention. While the digital video decoding system is processing the full motion video decoding, its procedure is the same as illustrated in Fig. 1. The compressed video data is put into the input unit 601, then output to memory unit 600 which includes a compressed data buffer 602 used for temporarily storing the compressed video data from input unit 601 and a frame memory 604 used for storing the reconstructed pictures which are used as reference pictures or display pictures for the purpose of decoding. A decompression unit 603 decompresses the data from the compressed data buffer 602 to creat the reconstructed image data which is output to the frame memory 604 then is further transferred to and processed by the display unit 605.
The memory distribution of the frame memory 604 is the same illustrated in Fig. 2; the reconstruction of pictures by utilizing the referenced pictures is also the same as illustrated in Fig. 4. The unique character of the present invention is the structure and method of subsampling used in the decompression unit 603. This subsampling structure and method enables the system to process the high resolution still picture decoding within the one 4M DRAM limit. Referring to the preferred embodiment of this invention, the horizontal subsampling in decompression unit 603 is processed before the reconstruction block data is written into the frame memory area 604. Therefore, only half the pixels of the 594K bytes in Fig.5 are required to be stored in the frame memory 604. The distribution of memory space in the frame memory 604 is shown in Fig. 7.FY 701 (198K bytes) is the memory space for Y element in high resolution still picture decoding after subsampling; FCb 702 (49.5K bytes) and FCr 703 (49.5K bytes) are the memory spaces for Cb and Cr chrominance elements respectively under the same condition as FY 701. The total required memory space shown in Fig. 7 is 297K bytes, half of the 594K bytes required by prior art and indicated in Fig. 5.
The display unit 605 of this invention utilizes a structure and method of interpolation and filtering to perform horizontal interpolation and filtering and recovers the pixels of pictures with high resolution, i.e., 704 x 480 or 704 x 576 pixels, to maintain high picture quality in high resolution still picture decoding.
The preferred embodiment of this invention will be described in details. Referring to the blocks in Fig.
6, when the high resolution still picture decoding is in process, the compressed data is put into the input unit 601, then is stored in the compressed data buffer 602 and further transmitted from the compressed data buffer 602 to decompression unit 603 which utilizes a reconstruction block buffer 607 used for storing every reconstruction block temporarily. The block, shown in
Fig. 8, comprises 8 x 8 pixels. The subsampling circuit 608 performs horizontal subsampling, forms subsampling block 802 which is composed of 4 x 8 pixels and achieves the purpose of halving the number of pixels. The subsampling block data is then written into the frame memory 604. Therefore, the number of pixels in each reconstruction block is reduced to one half in the horizontal direction, thus, the required memory of the frame memory area 604 is reduced by half.
In Fig. 6, the subsampling circuit 608 has an
EN(Enable) control signal(EN 606), which is directly controlled by the decompression procedure of the decompression unit 603. When a general SIF format video decoding is in process, EN 606 will be disabled which further disables the subsampling circuit 608, thus all the data in the reconstruction block buffer 607 will go through the subsampling circuit 608 and be written into the frame memory 604. When a high resolution still picture decoding is in process, EN 606 is enabled and the subsampling circuit 608 carries out its subsampling function.In consideration of the complexity of the circuit, the filtering capability in the subsampling algorithm is not activated when the horizontal subsampling is proceeding, rather, the algorithm will directly save one point ("O" point) and drop the other point ("X" point) respectively in every two adjacent pixel sample points in the horizontal direction as illustrated in Fig. 8. The sample points of " X " are dropped, and the sample points " O " are reserved.
In Fig. 6, the display unit 605 utilizes a display buffer 609 to temporarily store data from the frame memory 604; an Interpolation & Filtering Circuit 610 interpolates and filters the SL data output from the display buffer 609, and recovers the resolution of the originally encoded pictures in the horizontal direction. Fig. 9 illustrates the recovering process of the horizontally subsampled data going through the
Interpolation & Filtering Circuit 610. The SL data 901, output from the display buffer 609, is interpolated and filtered by the Interpolation & Filtering Circuit 610 and results in the IFL data 902. The decompressed frame formed by IFL data 902 is then output through the display unit 605.
While the display is being output from the display unit 605, since the common requirement of the display resolution follows a digital TV or a VGA standard, and since the interpolation and filtering are needed for both the SIF format picture pictures and the high resolution still pictures after horizontal subsampling, thus the Interpolation & Filtering Circuit 610 does not need to enable or disable its interpolation and filtering functions according to the different resolution of pictures. In this invention, the interpolated pixels utilize a horizontal 2 tap filtering algorithm, i.e.,
O X O h = (A + B) //2 AhB where h indicates an interpolated pixel, its value is obtained by averaging the value of the two adjacent pixels A and B; " // " represents a rounding funtion.
This method has an advantage of simplicity. It can minimize the complexity of the display buffer 609 and the Interpolation and Filtering Circuit 610 without losing the quality of the high resolution still pictures.
Fig. 10 shows the flow chart of the method of present invention used in a digital video decoding system. Through said flow chart, the required memory space of recovering high resolution still pictures will be reduced to half of that required in the prior art thus the memory space used for full motion video decoding is also suitable for high resolution still picture decoding.
Step 1001 is to recover the RB data from the compressed video data.
Step 1002 is to decide whether it is a high resolution still picture decoding; if it is, go to Step 1003 , otherwise, go to Step 1004.
Step 1003 is to subsample the RB data so as to obtain the SB data.
Step 1004 is to store the SB data into the frame memory or to store the RB data into said memory.
Step 1005 is to transfer the SB data or RB data from the frame memory to the display buffer, and output the SL data from the display buffer.
Step 1006 is to interpolate and filter the SL data so as to obtain the IFL data.
Step 1007 is to form the decompressed frames from the IFL data.
Althougn the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various slternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
Claims (15)
1. A digital video decoding system used for decoding a compressed video data and outputing decompressed frames, comprising:
a decompression unit used to recover a RB data from the compressed video data in a full motion video decoding, and recover a SB data from the compressed video data in a high resolution still picture decoding;
a frame memory used to store said RB data and said SB data, said two kinds of data are both called image block (IB) data; and
a display unit used to recover a decompressed frame from image block data.
2. The system of claim 1 wherein said decompression unit comprising:
a reconstruction block buffer used to store said RB data recovered from said compressed video data; and
a subsampling means having an enable control signal used to subsample the RB data under an enabled state and output the SB data, said signal is used to allow the RB data to go through the subsampling means without subsampling said data when under a disabled state; and
wherein said enabled state is a state under the high resolution still picture decoding, and said disabled state is a state under the full motion video decoding.
3. The system of claim 1 wherein the display unit comprising:
a display buffer means used to transform the image block data output from said frame memory area to a
SL ( scanning line ) data and then output said SL data; and
an interpolation and filtering means used to interpolate and filter SL data so as to output an IFL ( Interpolation and Filtering Scanning
Line) data, and the IFL data further forms said decompressed frames.
4.The system of claim 1 wherein includes a compressed data buffer used for temporarily storing the compressed video data, said compressed data buffer and the frame memory are grouped as a memory unit.
5. The system of claim 2 wherein said sbusampling means is a horizontal subsampling means which can horizontally subsample the RB data so as to obtain a horizontal SB (subsampling block) data under a high resolution still picture decoding state.
6. The system of claim 1 wherein said RB data is composed of 8 x 8 pixels.
7. The system of claim 5 wherein said horizontal subsampling block data is composed of 4 x 8 pixels.
8. A MPEG digital video decoding system used to decode the compressed video data and output the decompressed frames, said system comprising:
a reconstruction block buffer means used to store the RB data revocered from the decompressed video data;
a subsampling means having an EN (enable) control signal that when the MPEG digital video decoding system is processing the high resolution still picture decoding, said signal is under an enabled state and horizontally subsamples the RB data so as to obtain the SB data, and that when the MPEG digital video decoding system is processing the full motion video decoding, said signal is under a disabled state and allows the RB data to go through the subsampling means without subsampling said data;
a frame memory area used to save the RB data or
SB data, said two kinds of data are all called image block data;;
a display buffer means used to transform the image block data output from the frame memory to the SL data;
an interpolation and filtering means used to interpolate and filter the SL data so as to output IFL data, said IFL data further forms said decompressed frame.
9. The system of claim 8 wherein includes a compressed data buffer used for temporarily storing the compressed video data, said compressed data buffer and the frame memory are grouped as a memory unit.
10. A digital video decoding method used in the high resolution still picture decoding, comprising the following steps:
(1) Recovering the RB data from compressed video data;
(2) Subsampling the RB data to obtain the SB data;
(3) Transforming the subsampling block data to SL data;
(4) Interpolating and filtering the SL data to obtain IFL data; and
(5) Forming decompressed frames from IFL data.
11. The method of claim 10 wherein said subsampling described in said step (2) is a horizontal subsampling.
12. Digital video decoding systems as claimed in claim 1 and as herein described.
13. Digital video decoding systems as herein described with reference to the accompanying drawings.
14. Digital decoding methods as claimed in claim 10 and as herein described.
15. Digital decoding methods as herein described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9426431A GB2296618B (en) | 1994-12-30 | 1994-12-30 | System and method for digital video decoding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9426431A GB2296618B (en) | 1994-12-30 | 1994-12-30 | System and method for digital video decoding |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9426431D0 GB9426431D0 (en) | 1995-03-01 |
| GB2296618A true GB2296618A (en) | 1996-07-03 |
| GB2296618B GB2296618B (en) | 2003-03-26 |
Family
ID=10766733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9426431A Expired - Lifetime GB2296618B (en) | 1994-12-30 | 1994-12-30 | System and method for digital video decoding |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2296618B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0827344A2 (en) * | 1996-08-30 | 1998-03-04 | Texas Instruments Incorporated | Video decoder |
| GB2320637A (en) * | 1996-12-19 | 1998-06-24 | Samsung Electronics Co Ltd | Recording and reproducing digital video signals |
| WO1998027737A1 (en) * | 1996-12-18 | 1998-06-25 | Thomson Consumer Electronics, Inc. | Formatting of recompressed data in an mpeg decoder |
| EP0964583A2 (en) * | 1998-06-01 | 1999-12-15 | Texas Instruments Incorporated | Reduced resolution video decompression |
| WO2001086963A1 (en) * | 2000-05-08 | 2001-11-15 | Micronas Munich Gmbh | Video-signal decoder and method for removing interferences in a video image |
| US6594315B1 (en) | 1996-12-18 | 2003-07-15 | Thomson Licensing S.A. | Formatting of recompressed data in an MPEG decoder |
| EP1026889A3 (en) * | 1999-01-27 | 2003-08-06 | General Instrument Corporation | Synchronous dram bandwidth optimization for display downsizing of an MPEG-2 image |
| US6879631B1 (en) | 1996-12-18 | 2005-04-12 | Thomson Licensing S.A. | Selective compression network in an MPEG compatible decoder |
| EP2055104A2 (en) * | 2006-07-27 | 2009-05-06 | Lsi Corporation | Method for video decoder memory reduction |
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| GB2068673A (en) * | 1980-01-30 | 1981-08-12 | Sony Corp | Decoding and recoding composite digital colour television signals |
| EP0352964A2 (en) * | 1988-07-28 | 1990-01-31 | British Broadcasting Corporation | Improvements in television signals |
| EP0394486A1 (en) * | 1988-10-24 | 1990-10-31 | Matsushita Electric Industrial Co., Ltd. | Television receiver |
| GB2232554A (en) * | 1989-04-20 | 1990-12-12 | Thomson Consumer Electronics | Instant replay television system |
-
1994
- 1994-12-30 GB GB9426431A patent/GB2296618B/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2068673A (en) * | 1980-01-30 | 1981-08-12 | Sony Corp | Decoding and recoding composite digital colour television signals |
| EP0352964A2 (en) * | 1988-07-28 | 1990-01-31 | British Broadcasting Corporation | Improvements in television signals |
| EP0394486A1 (en) * | 1988-10-24 | 1990-10-31 | Matsushita Electric Industrial Co., Ltd. | Television receiver |
| GB2232554A (en) * | 1989-04-20 | 1990-12-12 | Thomson Consumer Electronics | Instant replay television system |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0827344A3 (en) * | 1996-08-30 | 2000-01-19 | Texas Instruments Incorporated | Video decoder |
| EP0827344A2 (en) * | 1996-08-30 | 1998-03-04 | Texas Instruments Incorporated | Video decoder |
| US6879631B1 (en) | 1996-12-18 | 2005-04-12 | Thomson Licensing S.A. | Selective compression network in an MPEG compatible decoder |
| WO1998027737A1 (en) * | 1996-12-18 | 1998-06-25 | Thomson Consumer Electronics, Inc. | Formatting of recompressed data in an mpeg decoder |
| WO1998027743A1 (en) * | 1996-12-18 | 1998-06-25 | Thomson Consumer Electronics, Inc. | Selective compression network in an mpeg compatible decoder |
| US6594315B1 (en) | 1996-12-18 | 2003-07-15 | Thomson Licensing S.A. | Formatting of recompressed data in an MPEG decoder |
| GB2320637A (en) * | 1996-12-19 | 1998-06-24 | Samsung Electronics Co Ltd | Recording and reproducing digital video signals |
| GB2320637B (en) * | 1996-12-19 | 2001-02-14 | Samsung Electronics Co Ltd | Apparatus for recording and reproducing digital broadcast signals |
| EP0964583A2 (en) * | 1998-06-01 | 1999-12-15 | Texas Instruments Incorporated | Reduced resolution video decompression |
| EP0964583A3 (en) * | 1998-06-01 | 2000-02-23 | Texas Instruments Incorporated | Reduced resolution video decompression |
| EP1026889A3 (en) * | 1999-01-27 | 2003-08-06 | General Instrument Corporation | Synchronous dram bandwidth optimization for display downsizing of an MPEG-2 image |
| WO2001086963A1 (en) * | 2000-05-08 | 2001-11-15 | Micronas Munich Gmbh | Video-signal decoder and method for removing interferences in a video image |
| EP2055104A2 (en) * | 2006-07-27 | 2009-05-06 | Lsi Corporation | Method for video decoder memory reduction |
| JP2009545234A (en) * | 2006-07-27 | 2009-12-17 | エルエスアイ コーポレーション | Method for video decoder memory reduction |
| EP2055104A4 (en) * | 2006-07-27 | 2011-09-14 | Lsi Corp | Method for video decoder memory reduction |
| CN101513064B (en) * | 2006-07-27 | 2013-08-14 | Lsi公司 | Method for video decoder memory reduction |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9426431D0 (en) | 1995-03-01 |
| GB2296618B (en) | 2003-03-26 |
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| PE20 | Patent expired after termination of 20 years |
Expiry date: 20141229 |