GB2290892A

GB2290892A - Automatic parity detect and generate circuit

Info

Publication number: GB2290892A
Application number: GB9508487A
Authority: GB
Inventors: Stewart Goudie; Alexander Roger Deas
Original assignee: Memory Corp PLC
Current assignee: Memory Corp PLC
Priority date: 1995-04-26
Filing date: 1995-04-26
Publication date: 1996-01-10
Also published as: GB9508487D0

Abstract

A circuit for automatically detecting and generating the correct parity for a data system comprises a decoder 28 for analyzing the data bits and parity bit sent by a host, where the decoder has a register 26 for controlling a selection circuit 12, and where the selection circuit is connected to various parity system generators 14, 16, 20, 24, such that in response to the decoder the said selection circuit selects the appropriate parity generation system. The circuit may be incorporated in a single-in-line-memory-module. <IMAGE>

Description

Automatic Parity Detect and Generate Circuit The present invention relates to the field of memory modules for computers.

The present invention is applicable in particular, though not exclusively, to Single In-line Memory Modules (SIMMs) which are designed to be compatible with a range of different computers, for example IBMIM compatible personal computers, Apple McIntosh computers, Power McIntoshaM computers, etc.

Different types of computers have different conventions relating to reading and writing data. For example, most computers have the facility to use a parity bit in addition to the bits of data that are intended to be stored. When the bits of data are retrieved the extra parity bit is also read. This extra parity bit is used as a check to verify that the data sent by the memory is received by the computer host. Since the parity bit does not represent data which is vital to the integrity of the other bits of stored data, in many applications it can be discarded entirely. However, the computer must receive the parity bit that it is expecting, otherwise it will flag an error. To overcome this problem (that a computer must receive a parity bit according to the computer's convention), it is common to have a number of opencircuit connections on the SIMM.One pair of connections would be used for an Odd parity (the value of the parity bit is such that the total number of logic one bits is always odd), one pair for an Even parity (the value of the parity bit is such that the total number of logic one bits is always even), one pair for a fixed value of logic one (the parity bit is always set to logic one), and one pair for a fixed value of logic zero (the parity bit is always set to logic zero). A "jumper" is used to short-circuit any pair of these otherwise opencircuit connections and thus select the desired parity system. Thus a SIMM is manually configurable for a variety of computer systems by placing a jumper connection in the appropriate place.

It is an object of the present invention to provide a circuit that will automatically detect and generate the correct parity for a particular application.

One advantage of the present invention is the ability to incorporate the invention into a standard SIMM. This avoids the need to rely on manual adjustment of the "jumpers" to cope with the particular type of parity bit expected. Thus a standard SIMM could be used in many different applications without needing any manual adjustment to match the parity configuration of the system. A further advantage of the present invention is that the user does not need to know what parity scheme is being implemented in a computer system, since the user does not have to make any adjustments to the circuit.

Thus the present invention provides a circuit for detecting the parity system in operation in a computer system and generating a suitable parity for accompanying the data on each read cycle.

For a better understanding of the present invention, and to show how the same may be carried into effect reference will now be made by way of example, without loss of generality, to the accompanying drawing in which: Figure 1 shows a simple parity detect and generate circuit 10.

Figure 2 shows a simple truth table for determining what parity convention is being operated.

Figure 1 shows a four input multiplexer 12. Each input represents one possible parity system. The fixed logic one system is represented by a live wire 14 connected to Vcc. The fixed logic zero system is represented by an earth wire 16 connected to zero volts. An odd parity wire 18 is connected to a first parity generator 20 which generates odd parity. An even parity wire 22 is connected to a second parity generator 24 which generates even parity. The multiplexer 12 is controlled by a register 26. This register 26 selects the appropriate input ofthe multiplexer 12 corresponding to the input from a decoder 28. The decoder 28 is used to analyze the parity bit sent by a host computer and determine what parity convention is being implemented by the host computer.The decoder 28 has multiple input lines 30 to enable it to monitor the data sent by the host and the parity bit sent by the host.

The data sent by the host computer may have to be monitored for a number of write cycles to determine what parity convention is being used by the host computer. For example, if a byte is received which contains three logic one bits and five logic zero bits and the parity is set to logic one then this could mean either of two conventions. It could be a fixed logic one parity or it could be an even parity convention. If the next byte which was written contained four logic one bits and four logic zero bits and the parity bit was set to logic one then this would show that the parity convention was fixed at logic one. If however. the parity bit was set to logic zero then this would show that an even parity convention was in operation.

Once the decoder has analyzed the data and parity bit received from the host computer it then sends a bit sequence to the register 26 which is used to control the multiplexer 12 by selecting the appropriate input line. The multiplexer then routes the input line selected to a parity register (not shown in Figure 1) to be used as a parity bit when the host computer requests a read from the memory. When odd or even parity is being implemented then the parity register is used to determine whether a logical one or logical zero is required for the particular combination of bits read from the memory. This element of computation is not required when the parity convention being implemented is fixed logic one or fixed logic zero.

The circuit for detecting the parity system being implemented by a host computer may operate each time that data is written to the memory or it may only operate during a certain initialisation period. If the circuit only operated during a certain initialisation period then the multiplexer would be set to select the appropriate parity input continually, until another initialisation period changed the multiplexer setting.

It will be appreciated that various modifications may be made to the above described embodiment within the scope of the present invention.

Claims

1. A circuit for automatically detecting and generating the correct parity for a data system comprising: a decoder for analysing the parity bit sent by a host, where the decoder has control means for controlling a selection circuit, and where the selection circuit is connected to various parity system generators, such that in response to the control means operated by the decoder the said selection circuit selects the appropriate parity system.

2. A circuit for automatically detecting and generating the correct parity for a data system according to claim 1 where that system is a memory module.

3. A circuit for automatically detecting and generating the correct parity for a data system according to either claim 1 or claim 2 where the said decoder monitors the data sent by the host for a number of cycles before determining the parity system employed.

4. A circuit for automatically detecting and generating the correct parity for a data system according to any preceding claim where a register is used to control the selection circuit.

5. A circuit for automatically detecting and generating the correct parity for a data system according to any preceding claim where the said decoder sends a bit sequence to the register to control the selection circuit.

6. A circuit for automatically detecting and generating the correct parity for a data system according to any preceding claim where the selection circuit is a multiplexer.

7. A circuit for automatically detecting and generating the correct parity for a data system according to any preceding claim where the system only operates during an initialisation period.