GB2281827A

GB2281827A - PLL arrangements

Info

Publication number: GB2281827A
Application number: GB9416245A
Authority: GB
Inventors: Yoshitaka Hirose; Jun Sugawara
Original assignee: Alps Electric Co Ltd
Current assignee: Alps Alpine Co Ltd
Priority date: 1993-09-03
Filing date: 1994-08-11
Publication date: 1995-03-15
Anticipated expiration: 2014-08-11
Also published as: GB2281827B; DE4431172C2; DK100994A; DK174133B1; JPH0774671A; GB9416245D0; DE4431172A1

Description

K1769GB:JK 2281827 OSCILLATION CIRCUIT AND PLL IC The present invention

relates to an oscillation circuit and a PLL IC of a transmitter-receiver and, more particularly, to an oscillation circuit and a PLL IC which are suitable for use in a transmitter-receiver of a cordless telephone system.

In a cordless telephone system, for example a DECT type digital cordless telephone system used in the Europe region, generally a frame for conversation channels for 10 msec is divided into 24 time slots (about 417 Msec) and two of these time slots are used as conversation slots. one of the divided time slots is used as a base station slot in order to transmit signals from a base station to a hand set, and another one is used as a hand set slot in order to transmit signals from a hand set to a base station. Thus conversation is conducted. The base station slot and the hand set slot are separated by 12 time slots. For example, when a first slot is assumed as a base station slot a thirteenth slot is used as a hand set slot.

Which slot of which channel is used to conduct a conversation is determined for each frame by a base station, and the hand set monitors all slots of all channels at times other than the conversation slots assigned to the machine on its own. The contents of the conversation are converted into digital signals, and then time-compressed and transmitted. The receiving side expands the time-compressed signals into their original signals, and thus a substantially simultaneous two-way communication is possible.

In the above-described cordless telephone system, it is necessary to provide an oscillator for transmitting signals and another one for receiving signals. since for hand sets in particular there has been a demand for a lighter weight, lower power consumption, K1769GB:JK 2 and lower cost, circuitry is used in which one oscillator formed of one VCO and one PLL IC is made to serve both as a receiving local oscillator and also as a transmitting carrier-wave oscillator.

In a telephone set having such circuitry, when switching the VCO from a local oscillator to a carrier wave oscillator, the frequency thereof must be changed.

The above-mentioned DECT type system allows one slot just before the hand set slot lock-up time during this switching. Therefore, the circuitry is realized by using a high-speed lock-up type PLL (phase locked loop).

The telephone set operates the VCO as a carrier wave oscillator during a transmitting state, and applies both digital signals to be transmitted and a frequency control signal from the.PLL to the VCO so that the VCO outputs a FSK modulated wave. However, since the PLL is of a high-speed lock-up type, FSK modulation is cancelled by the frequency control signal from the PLL.

Therefore, the PLL is placed in a standby state when the VCO is operated as a carrier-wave oscillator so that the PLL does not output a frequency control signal, and the oscillation frequency of the VCO is controlled only by a voltage maintained in a loop filter.

There follows a description of a wireless transmitter-receiver into which an oscillator of the present invention and of the prior art is applied, and of an oscillator according to the prior art with reference to the accompanying drawings.

Figure 4 is a block diagram illustrating the construction of a wireless transmitter-receiver into which an oscillator of the present invention and of the prior art is applied. Figure 5 is a block diagram illustrating the construction of an oscillator of the prior art.

Figure 6 is an illustration showing the switching of a PLL in accordance with a power save signal. In Figures 4 and K1769GB:JK 3 5, reference numeral 1 denotes a PLL IC; reference numeral 2 denotes a loop filter; reference numeral 3 denotes a voltage control oscillator; reference numeral 4 denotes a quartz oscillator; reference numeral 5 denotes a controlling microcomputer 5; reference numeral 6 denotes a prescaler; reference numeral 7 denotes a PLL control circuit; and reference numeral 8 denotes a charge pump circuit 8.

The transmitter-receiver shown in Figure 4 comprises an oscillation circuit using a PLL frequency synthesizer circuit having a quartz oscillator 4, a voltage control oscillator (VCO) 3, a PLL IC 1, and a loop filter (LPF) as an oscillation circuit which serves as a carrier-wave oscillator at a time of transmission and also as a local oscillator during reception. The PLL IC 1 comprises the prescaler 6, the PLL control circuit 7, and the charge pump circuit 8. The PLL control circuit 7 is operated when a reference frequency signal is supplied thereto from the quartz oscillator 4 and various control signals are supplied thereto from the control microcomputer (CPU) 5. The PLL control circuit 7 controls the oscillation frequency of the voltage control oscillator (VCO) 3 by supplying a synchronization pulse DO, which is an output from the charge pump circuit, to the VCO 3 via the LPF 2.

Since those circuit portions shown in the figure other than those described above are not directly related to the present invention, and since the construction and operation thereof is well known, an explanation thereof is omitted.

The construction of the above-described oscillation circuit formed of a PLL frequency synthesizer circuit is shown in Figure 5. In the circuit shown in the figure, VCC is a power-supply terminal for each apparatus, and VP is a power-supply terminal for a charge pump K1769GB:JK 4 circuit, PLL IC I receives each control signal PLLCLK, PLLSTB, and PLLDATA from the CPU 5 shown in Figure 4, and the charge pump circuit 8 outputs the synchronization pulse Do, which is a frequency control signal, to the VCO 3 from the charge pump circuit 8, so that the oscillation frequency of the VCO 3 is controlled via the LPF 2.

The synchronization pulse DO is output at a frequency equal to that of a reference frequency signal which is input to a phase comparator contained in the PLL IC 1. In the wireless transmitter-receiver shown in Figure 4, this frequency is 1.728 MHz, which is equal to the channel separation. The output waveform of this synchronization pulse DO, as shown in Figure 6, is formed into a waveform having a pump-up pulse and a pump-down pulse.

In the wireless transmitter-receiver for mobile communication, shown in Figure 4, to suppress power consumption of a battery, the PLL synthesizer function is operated for a necessary time. At other times, the PLL synthesizer function is halted and placed in a standby state. This control is effected by a power save signal PS shown in Figures 4 and 5.

When the PLL synthesizer circuit shown in Figure 5 is placed in a standby state by the power save signal, the PLL IC 1 halts the output of the synchronization pulse DO, and the output of the charge pump circuit 8 is controlled to a high impedance. Therefore, the VCO 3 can maintain the oscillation frequency thereof at a specific frequency before the PLL synthesizer circuit is placed in a standby state by a control voltage maintained in the LPF 2 during the standby period.

However, the PLL synthesizer circuit of the prior art shown in Figure 5 has a problem in that the oscillation frequency of the VCO 3 becomes unstable when an input of the power save signal PS and an output of the K1769GB:JK 5 synchronization pulse DO take place at the same time.

Figure 6 illustrates such a situation. It is now assumed, as shown in Figure 6, that the synchronization pulse DO is output in coincidence with the input of the power save signal PS which causes the PLL synthesizer circuit to be placed in a standby state, and the timing to the input (fall) of the power save signal PS coincides with the timing of the trailing edge of the pump-up pulse of the synchronization pulse DO.

In this case, since the output of the charge pump circuit of the PLL IC 1 is interrupted while the pump-up pulse of the synchronization pulse DO is being output, the pump-down pulse is not applied to the LPF 2.

As a result, the electrical potential of a capacitor used for a smoothing circuit within the LPF 2 becomes an electrical potential in a state in which a charge is injected by a pump-up pulse before the power save signal PS is applied, and maintained as a value different from the electrical potential before that. Since this voltage is applied to VCO 3 as a control voltage, the oscillation frequency of WO 3 varies. The magnitude of this variation differs depending upon the time within the output time width T of the synchronization pulse DO at which the power save signal PS occurs.

The above-described oscillation circuit using the PLL synthesizer circuit of the prior art has a problem in that when the input of the power save signal PS and the output of the synchronization pulse DO takes place at the same time, the value of the frequency control signal for the VCO, maintained in the LPF, becomes unstable, and as a result, the oscillation frequency of the VCO becomes unstable.

It is an object of the present invention to provide an oscillation circuit and a PLL IC of a transmitter-receiver which is capable of constituting a K1769GB:JK 6 transmitter-receiver of one PLL method which oscillates while maintaining the frequency accuracy required for communication equipment of a TDMA method even when the PLL is in a standby state.

According to the present invention, the above described object is achieved by inputting a power-save signal to a PLL while a synchronization pulse is not output, so that the PLL is switched from an operating state to a standby state while a synchronization pulse is not output in an oscillation circuit of a PLL synthesizer method of the above-described prior art.

According to the present invention there is provided an oscillation circuit of a transmitter-receiver, comprising: a VCO which is used as a carrier-wave oscillator for transmission and also as a local oscillator for reception; a PLL, including a charge pump circuit, which intermittently outputs a synchronization pulse, formed of a pump-up pulse and a pump-down pulse, when the phase of a comparison signal obtained by dividing the frequency of the oscillation signal of said VCO, coincides with the phase of a reference signal; and a loop filter into which said synchronization pulse is input, which filter smooths this pulse and outputs it as a frequency control signal to said VCO, said PLL being switched from an operating state to a standby state in accordance with a power-save signal, wherein said PLL is switched from an operating state to a standby state in a period during which said synchronization pulse is not output.

Also, according to the invention, the above described object is achieved by providing a flip-flop which inputs a power-save signal and a lock detection pulse which is output when the PLL is locked and which outputs the input power-save signal after the trailing edge of the lock detection pulse and switching the PLL from an operating state to a standby state in accordance K1769GB:JK 7 with a power-save signal output from the flip-flop.

According to the present invention in a second aspect there is provided an oscillation circuit of a transmitter-receiver, comprising: a VCO which is used as a carrier-wave oscillator for transmission and also as a local oscillator for reception; a PLL, including a charge pump circuit, which intermittently outputs a synchronization pulse, formed of a pump-up pulse and a pump-down pulse, when the phase of a comparison signal, obtained by dividing the frequency of the oscillation signal of said VCO, coincides with the phase of a reference signal; and a loop filter into which said synchronization signal is input, wherein said PLL is formed of a PLL IC comprising an input terminal into which a power-save signal is input, a lock detection circuit for detecting the locked state of the PLL and outputting a lock detection pulse, and a flip- flop for outputting the power-save signal input from said input terminal after the trailing edge of said lock detection pulse so that the PLL is controlled to be placed in a standby state.

According to the present invention in a third aspect there is provided a PLL IC, comprising: an input terminal for inputting a power-save signal; a lock detection circuit for detecting the lock state of the PLL and outputting a lock detection pulse; a flip-flop for outputting the power-save signal input from said input terminal after the trailing edge of said lock detection pulse; and a PLL which is controlled to be placed in a standby state in accordance with an output of the flip- flop.

The flip-flop functions as a power-save signal timing adjustment circuit, which flip-flop receives a lock detection pulse which is output in synchronization with a synchronization pulse output from the PLL, and a power- save signal. When only a power-save signal is input, the K1769GB:JK 8 flip-flop outputs the power-save signal at the same time when the signal is input. When a lock detection pulse and a power-save signal are input at the same time, the flip flop outputs the power-save signal after the lock detection pulse ceases. Since the power-save signal which is output from the flip-flop is applied to the PLL and the PLL is placed in a standby state, the frequency control voltage applied to the VCO is not varied when the PLL is switched to a standby state. Thus, the VCO is able to continue stable frequency oscillation with a high degree of accuracy even if the PLL is switched to a standby state.

An embodiment of an oscillation circuit and a PLL IC of a transmitter-receiver of the present invention will be explained below in detail by way of example only with reference to the accompanying drawings, in which:

Figure 1 is a block diagram illustrating the construction of an oscillation circuit in accordance with an embodiment of the present invention; Figure 2 shows the operation of a flip-flop for outputting a power-save signal to be applied to a PLL IC; Figure 3 is a block diagram illustrating the construction of the PLL IC in accordance with the embodiment of the present invention; Figure 4 is a block diagram illustrating the construction of a wireless transmitter-receiver into which an oscillator of the present invention and of the prior art is applied; Figure 5 is a block diagram illustrating the construction of an oscillator of the prior art; and

Figure 6 is an illustration showing the switching of a PLL in accordance with a power save signal.

In Figure 1, reference numeral 9 denotes a flip flop, and the other reference numerals in Figure 1 which are the same as those in Figure 5 designate the same K1769GB:JK 9 components.

The oscillation circuit using a PLL synthesizer circuit in accordance with the embodiment of the present invention, shown in Figure 1, differs from the oscillation circuit of the prior art explained with reference to

Figure 5 in that the former oscillation circuit comprises the flip-flop 9 which functions as a power-save signal timing adjustment circuit.

The flip-flop 9 inputs a power save signal PS output from the CPU which controls the entire transmitterreceiver and a lock detection pulse LOCKDET which is output from the PLL IC 1. When only the power save signal PS is input, the flip-flop 9 outputs the power save signal PS at the same time when the signal is input, and outputs the power save signal PS after the lock detection pulse LOCKDET ceases when the power save signal PS and the lock detection pulse LOCKDET are input at the same time. This output signal is applied as a power-save signal PS' to the PLL IC 1, and as a result the oscillation circuit shown in the figure is controlled to be placed in a standby state.

Next, the operation of flip-flop 9 will be described in detail with reference to Figure 2.

The flipflop 9 has D, CLK and PR as input terminals, and Q as an output terminal, and operates as indicated in the truth value table shown in Figure 2. As has already been described, the PLL IC 1 outputs the synchronization pulse DO produced by a pump-up pulse and a pump-down pulse at a predetermined cycle and applies the pulse to the LPF 2, and also outputs the lock detection pulse LOCKDET in a time period in which the pump-up pulse and the pump- down pulse of the synchronization pulse DO are included.

The lock detection pulse LOCKDET is input to the input terminal CLK of the flip-flop 9, while the power save signal PS from the CPU of the transmitter-receiver is K1769GB:JK - 10 - input to the input terminal D of the flip-flop 9 and an inversion signal of the power save signal PS is input to the input terminal PR of the flip- flop 9.

The flip-flop 9 operates in such a way that it detects the rise of the lock detection pulse LOCKDET which is input to the input terminal CLK, and outputs a lowlevel signal of the power save signal PS of the input terminal D to the output terminal Q. Therefore, as shown in Figure 2, when a power save signal PS which varies to a low level is input from the CPU of the transmitterreceiver to the input terminal D of the flip-flop 9 while the low-level lock detection pulse LOCKDET is applied to the input terminal CLK of the flip-flop 9, the power save signal PS is not transmitted to the output terminal Q and retarded.

Then, when the lock detection pulse LOCKDET rises to a high level from a low level, the low-level power save signal PS, which is applied to the input terminal D, is transmitted to the output terminal D of the flip-flop 9. This output signal is input as the powersave signal PSI to the PLL IC 1.

As a result, the PLL IC 1 halts output of a synchronization signal from the charge pump circuit so that the output of the charge pump circuit is controlled to a high impedance. The switching of the PLL IC 1 to a standby state in accordance with the power-save signal is not performed while the PLL IC 1 is outputting the synchronization pulse DO because of the above-described function of the flip-flop 9, and the VCO 3 always operates stably due to this switching.

In an oscillation circuit in accordance with an embodiment of the present invention, the VCO oscillates at a stable frequency accuracy even at a standby state when it is used in a transmitter-receiver of one PLL method, and thus the frequency accuracy required for communication K1769GB:JK equipment using a TDMA method can be ensured.

Figure 3 is a block diagram illustrating the construction of the PLL IC in accordance with an embodiment of the present invention.

The PLL IC shown by the dotted line of Figure 3, is formed in such a way that the PLL IC 1 and the flip flop 9 of the oscillation circuit are formed into one IC.

The block indicated as a power-save signal timing adjustment circuit is formed of a flip-flop explained with reference to Figure 2. The other circuit portions are the same as the PLL IC having a power save function of the prior art.

Such a PLL IC can be easily manufactured merely by adding one flip-flop to a PLL IC having a power save function of the prior art.

According to the present invention a stable frequency oscillation can be performed even when the PLL is in a standby state, and a transmitter-receiver of one PLL method, which oscillates while maintaining the frequency accuracy required for communication equipment using a TDMA method, can be formed. Also, according to the present invention, it is possible to provide a PLL IC, which does not make the operation of the VCO unstable even when the PLL IC is switched to a standby state, by merely adding a very simple circuit to the PLL IC.

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Claims

_7 CLAIMS

1. An oscillation circuit of a transmitter receiver, comprising:

a VCO which is used as a carrier-wave oscillator -5 for transmission and also as a local oscillator for reception; a PLL, including a charge pump circuit, which intermittently outputs a synchronization pulse, formed of a pump-up pulse and a pump-down pulse, when the phase of a comparison signal, obtained by dividing the frequency of the oscillation signal of said VCO, coincides with the phase of a reference signal; and a loop filter into which said synchronization pulse is input, which filter smooths this pulse and outputs it as a frequency control signal to said VCO, said PLL being switched from an operating state to a standby state in accordance with a power-save signal, wherein said PLL is switched from an operating state to a standby state in a period during which said synchronization pulse is not output.

2. An oscillation circuit according to Claim 1, wherein the timing of said switching is set immediately after the trailing edge of said synchronization pulse.

3. An oscillation circuit according to Claim I or Claim 2, wherein said PLL outputs a lock detection pulse which is interlocked to said synchronization pulse, and the timing of said switching is set immediately after the trailing edge of said lock detection pulse.

4. An oscillation circuit according to Claim 3, further comprising a flip-flop into which said power-save signal and said lock detection pulse are input, which flip-flop outputs said power-save signal after the trailing edge of said lock detection pulse, and wherein said PLL is switched from an operating state to a standby state in accordance with a power-save signal output from K1769GB:JK - 13 - said flip-flop.

5. An oscillation circuit of a transmitter receiver, comprising:

a VC0 which is used as a carrier-wave oscillator for transmission and also as a local oscillator for reception; a PLL, including a charge pump circuit, which intermittently outputs a synchronization pulse, formed of a pump-up pulse and a pump-down pulse, when the phase of a comparison signal, obtained by dividing the frequency of the oscillation signal of said VCO, coincides with the phase of a reference signal; and a loop filter into which said synchronization signal is input, wherein said PLL is formed of a PLL IC comprising an input terminal into which a power-save signal is input, a lock detection circuit for detecting the locked state of the PLL and outputting a lock detection pulse, and a flip-flop for outputting the power save signal input from said input terminal after the trailing edge of said lock detection pulse so that the PLL is controlled to be placed in a standby state.

6. A PLL IC, comprising:

an input terminal for inputting a power-save signal; a lock detection circuit for detecting the lock state of the PLL and outputting a lock detection pulse; a flip-flop for outputting the power-save signal input from said input terminal after the trailing edge of said lock detection pulse; and a PLL which is controlled to be placed in a standby state in accordance with an output of the flip flop.

7. An oscillation circuit as claimed in Claim 1 or Claim 5 and substantially as hereinbefore described, with reference to, and as illustrated by, the accompanying 7 K1769GB:JK - 14 - drawings.

8. A PLL IC as claimed in Claim 6 and substantially as hereinbefore described with reference to, and as 1 illustrated by, the accompanying drawings.

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