GB2278246A

GB2278246A - Current limiting circuit; bleed current control circuit for a telephone

Info

Publication number: GB2278246A
Application number: GB9409979A
Authority: GB
Inventors: Murray David Wild; Ronald Christopher Shaw Fox
Original assignee: Alcatel Australia Ltd
Current assignee: Nokia Services Ltd
Priority date: 1993-05-19
Filing date: 1994-05-18
Publication date: 1994-11-23
Anticipated expiration: 2014-05-18
Also published as: NZ260221A; BE1009093A5; GB2278246B; SG44687A1; GB9409979D0

Abstract

A bleed current control circuit for a telephone provides a shuntpath R2, T3 around the phoned line switch S1 to an on-hook load L1, such as a memory and real time clock. A transistor T2 senses the voltage across R2 and controls a transistor T1 causing the load current through transistor T3 to decrease when the current through R2 is excessive. <IMAGE>

Description

CURRENT CONTROL CIRCUIT This invention relates to a bleed current circuit to provide power to an electronic circuit in its quiescent mode. This bleed current may be necessary to provide power for circuit elements such as a memory or processor while the circuit is not in use. A common situation where the need for such a bleed circuit arises is in the case of an ON-HOOK telephone subset, and the invention will be described in that context.

Many modern telephones include memories and processors and are connected to the phone line via a line switch which is open circuit when the phone is ON-HOOK. The phone is powered from the exchange via the phone line so when the phone is ON-HOOK the phone is unpowered.

One way to continue to provide power for the phone when ON-HOOK is to provide a large value bleed resistor (-1Mn) shunting the line switch. However, this solution may not always be acceptable. In Australia, there is a requirement that bleed currents be kept below 50A, so the bleed resistor must limit the current to that value with maximum line voltage which may be of the order of 50V.

However where two phones are connected in parallel to a line and one of the phones is taken OFF-HOOK the line voltage may fall to e.g., 10V. This means that the bleed current for the ON-HOOK phone is reduced in proportion to the change in line voltage. This may cause the bleed current to fall below that required by the phone's circuit. Alternatively if the bleed resistor is chosen to provide sufficient current at minimum line voltage, the current may exceed the permitted level at maximum line voltage.

The present invention seeks to provide a bleed current circuit that satisfied the before mentioned requirements.

According to one aspect of the invention there is provided a bleed current regulating circuit to control the bleed current fed from a source of electric power to a load, the regulating circuit including sensing means to sense the bleed current, the sensing means causing impedance control means to increase a series impedance between the source and the load when the sensing means detects that the bleed current has exceeded a first threshold level.

According to another aspect of the invention there is provided a bleed current control circuit to control the bleed current to a load from a source of electric power, the circuit including a first transistor with its emittercollector path in series with a first resistor and the load, a second transistor with its emitter-collector path in series with a second resistor and the load, the base of the first transistor being connected to the junction of the collector of the second transistor and the second resistor, and a third transistor with its collector emitter path in series between a third resistor and the load, the base of the third transistor being connected to the junction of the collector of the first transistor, the third resistor being connected between the base-emitter terminals of the second transistor, wherein, when the current through the third resistor causes the voltage drop across the third resistor to exceed the turn-on base-emitter voltage of the second transistor, the emitter-collector voltage of the second transistor falls, reducing the emitter collector current of the first transistor, which tends to reduce the collectoremitter current of the third transistor, whereby the collector-emitter current of the third transistor is limited.

In order that the invention and its various other preferred features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the drawing the single Figure of which shows a bleed circuit embodying the invention.

In the drawing an on-hook load L1, e.g., a telephone memory and real time clock circuit, is connected to a source of electric power VS, e.g., a telephone line, via a switch S1, e.g., the line switch, and a diode D1, and an off-hook load L2 e.g., a telephone speech circuit being also coupled to VS. In the case of an electronic line switch, S1 may be controlled from a handset detection circuit which switches S1 on and off via line W1 depending on whether the handset is OFF-HOOK or ON-HOOK respectively. Line W1 may also be used to switch S1 where the subset includes a hands free control switch.

When the phone is ON-HOOK, S1 is open circuited, so the phones memory and real time clock circuit is powered via the bleed circuit. The bleed circuit contains first, second, and third transistors T1, T2 and T3, resistors R1, R2 and R3 and capcitor C1. Diode D1 prevents current from the bleed circuit flowing via load L2.

Under normal operating conditions T1, T2 and T3 are biased in their linear regions. In one embodiment R1 and R3 are each of the order of 5MN and R2 is of the order of 14it.

The main bleed current path is via R2 and the collectoremitter path of TR3 to load L1. Thus the supply voltage VS is dropped across R2, VCE of TR3, and across the load (VL).

The operating point of T3 is chosen so that for a nominal line voltage Vs of 50v, the bleed current will be 45yA.

This means that (45yA x 14000X) volts are dropped across R2 so that the remaining voltage (50 - VR2) is dropped across TR3 and load L1.

VR2-0.5v and the load voltage VL is an order of magnitude smaller than VS. Thus the major part of VS is dropped across TR3 (-47v), T3 is controlled by the current passed by T1 and T1 in turn is controlled by T2. T2 is controlled by the voltage drop across R2 as this corresponds to VBE for T2.

Thus as the bleed current through R2 increases, VBE for T2 increases. When VEE T2 exceeds the turn-on voltage, T2 begins to conduct. This causes a reduction in VCE for T2 which is equal to VBE for T1. Thus the emitter-collector current of T1 is reduced, reducing the base current for T3.

Consequently the collector-emitter current of T3 is stabilized and prevented from exceeding the predetermined limit.

The bleed current is determined by the formula:

When VS falls to a level where VR2 < VBE(TURN ON) (approximately 0.5v) for T2, T2 is switched off and does not contribute to the bleed current. The bleed current ib is determined by the gains of T1 and T3, so that:

Where ss1 is the gain of T1, and ss3 is the gain of T3.

Capacitor C1 filters noise from the line.

Claims

CLAIMS: 1. A bleed current regulating circuit to control the bleed current fed from a source of electric power to a load, the regulating circuit including sensing means to sense the bleed current, the sensing means causing impedance control means to increase a series impedance between the source and the load when the sensing means detects that the bleed current has exceeded a first threshold level. 2. A bleed current control circuit to control the bleed current to a load from a source of electric power, the circuit including a first transistor with its emittercollector path in series with a first resistor and the load, a second transistor with its emitter-collector path in series with a second resistor and the load, the base of the first transistor being connected to the junction of the collector of the second transistor and the second resistor, and a third transistor with its collector emitter path in series between a third resistor and the load, the base of the third transistor being connected to the junction of the collector of the first transistor, the third resistor being connected between the base-emitter terminals of the second transistor, wherein, when the current through the third resistor causes the voltage drop across the third resistor to exceed the turn-on base-emitter voltage of the second transistor, the emitter-collector voltage of the second transistor falls, reducing the emitter collector current of the first transistor, which tends to reduce the collectoremitter current of the third transistor, whereby the collector-emitter current of the third transistor is limited. 3. A bleed current control circuit substantially as herein described with reference to the accompanying drawing. 4. A telephone subset including a bleed current control circuit as claimed in any one of claims 1 to 3. Amendments to the claims have been filed as follows

1. A current supply arrangement to supply a load current to a load via a load switch when the load is in an activated condition with the load switch being switched ON, and to supply a bleed current to the load via a bleed current circuit when the load is in a quiescent condition with the load switch being switched OFF, wherein the bleed current circuit is in parallel with the load switch, the bleed current circuit including a first transistor with its emitter-collector path in series with a first resistor and the load, a second transistor with its emitter-collector path in series with a second resistor and the load, the base of the first transistor being connected to the junction of the collector of the second transistor and the second resistor, and a third transistor with its collector emitter path in series between a third resistor and the load, the base of the third transistor being connected to the collector of the first transistor, the third resistor being connected between the base-emitter terminals of the second transistor, wherein, when the current through the third resistor causes the voltage drop across the third resistor to exceed the turn-on base-emitter voltage of the second transistor, the emitter-collector voltage of the second transistor falls, reducing the emitter collector current of the first transistor, which tends to reduce the collectoremitter current of the third transistor, whereby the collector-emitter current of the third transistor is limited.

2. An arrangement as claimed in claim 1 in which the first transistor is a first PNP transistor, the second transistor is a second PNP transistor, and the third transistor is an NPN transistor.

3. An arrangement as claimed in claim 1 or claim 2, including a noise suppression capacitor connected between the base and emitter of the first transistor.

4. An arrangement as claimed in any one of claims 1 to 3, wherein the first and second resistors are of the order of 5MQ and the third resistor is of the order of 14KR.

5. A telephone circuit including a current supply arrangement as claimed in any one of claims 1 to 4.

6. A telephone circuit including a current supply arrangement substantially as herein described with reference to the accompanying drawing.