GB2278013A - Forming nanoscale conductive patterns on substrates - Google Patents

Abstract

A conductive pattern of atoms 5<1> is initially formed on a substrate using a scanning tunneling microscope. The conductive atoms are connected to external conductive lines 4<1>, 4<2>, 4<3> to which suitable potentials are applied. The applied potentials allract atoms 7<1> during an MOCVD or MBE process to sites such as X<1> thereby forming a multi-layer structure. <IMAGE>

Description

Method of forming Nano-scale Electronic Device DESCRIPTION This invention relates to a method of forming nanoscale electronic device.

Future electronic devices will be on the atomic scale.

A number of such devices are described in our co-pending GB 9213054.1 filed on 19th June 1992 in which a probe such as a scanning tunneling microscope (STM) is used to manipulate inidividual atoms so as to construct the desired devices and circuits. However, the methods described in our aforesaid application suffer from the disadvantage that the slow speed at which individual atoms can be manipulated with a STM limits the practicality of the method for mass producing atom scale devices. Also, it is difficult to build up a complex 3-dimensional structure on an atomic scale since a large number of individual manipulations are required to achieve the desired result. In our application aforesaid, it has been proposed to overcome this difficulty by providing an array of STM tips on a common substrate, which produce a plurality of devices concurrently, i.e. in parallel.

However, even with such a method, a large number of individual steps are required and it still remains difficult to achieve a desired 3-dimensional structure.

The main limitation for 3-dimensional building is the relative coarseness of the STM tip; the radius of curvature of its tip is large compared with the scale of fabrication desired, making 3-dimensional structuring difficult.

In accordance with the present invention, a method is provided which may overcome these difficulties.

In accordance with the present invention there is provided a method of forming a nano-scale electronic device, comprising manipulating atoms on a substrate to form a conductive atomic scale pattern, applying at least one electrical potential to said pattern, and depositing material on the pattern whereby atoms or molecules selectively aggregate to predetermined parts of the pattern in dependence upon the configuration thereof and the potential applied thereto.

The manipulation of substrate atoms can be performed by a probe, for example a STM or an atomic force microscope (AFM).

The material may be deposited by any suitable means, for example molecular beam epitaxy (MBE) or metalorganic chemical vapour deposition (MOCVD).

The potential applied to the pattern can be varied so that during deposition of a first material, a first potential pattern causes a first selective aggregation of material, and thereafter, during deposition of a second material, a second potential pattern is produced, so as to produce a second selective aggregation of material. In this way, a 3-dimensional structure can be built up using an initial pattern of atoms manipulated on the substrate into a template with a STM, without the need for further complex manipulation of atoms with the STM for subsequent layers formed on the substrate, as in the prior art.

In accordance with the invention, it is possible to provide a single substrate with a plurality of starting templates, produced using an STa, and thereafter to achieve the growth processes in parallel, to produce a plurality of devices concurrently.

The devices may all be the same, but by applying different potentials to the patterns, different devices can be built up by the method on the same substrate.

In order that the invention may be more fully understood, an example thereof will now be described with reference to the accompanying drawings in which Figure 1 illustrates a pattern of interconnections formed on a substrate for use in forming a nano-scale electronic device in accordance with a method of the invention; Figure 2 is an enlarged view of a portion of the arrangement shown in Figure 1; Figure 3A is an enlarged view of a portion of the configuration shown in Figure 2; Figure 3B corresponds to Figure 3A, with a selective atomic deposition thereon; and Figure 4 illustrates a number of process steps in accordance with a method of the invention.

Referring firstly to Figure 1, this illustrates a plan view of a semiconductor substrate, typically formed of gallium arsenide having a central region 1 in which an atomic scale device is to be formed. In order to provide external connections, relatively large bond pads 2 and interconnections 3 are defined by optical lithography in a manner well known per se, and then finer lines 4 are formed by electron beam lithography between the connecting regions 3 and the central region 1. A metalisation is applied to the lithographically defined areas in a manner well known in the art.

In the region 1, the configuration of atoms on the substrate surface is selectively manipulated using a STM. It is known that the STM is a useful tool for single atom manipulation and a general review is given in "Atomic and Molecular Manipulation with the Scanning Tunneling Microscope" J.A. Stroscio and D.M. Eigler Science Volume 254, 29 November 1991 p 1319 - 1326.

Also, reference is directed to our patent application aforesaid. A typical arrangement of atoms in a portion of the region 1 is shown schematically in Figure 3A, it can be seen that a pattern of conductive atoms 5 (shown shaded) is arranged amongst non-conductive atoms 6. The conductive atoms are connected to the external conductive lines 4 defined by electron beam lithography.

It is known that when atoms and molecules are deposited onto a substrate of this nature, they first physisorb and then chemisorb preferentially at surface sites in which the potential distribution suits the particular atom or molecule best. This general principle is described for example in our GB-A-2258236, in which a substrate is manipulated with an STM to provide an atomic site, useable as a template, to assemble complex molecular chains.

In the present arrangement, as shown in Figure 3A, potentials are applied via the external connections 2, 3, 4 to the conductive atoms in region 1 so as to influence the manner in which deposited atoms attach themselves to the substrate. Thus, referring to Figure 3A, the conductive atoms 5 receive an external potential through connection 41. Since the atoms are arranged in a generally U-shaped configuration, an appropriate field distribution is produced in the region X1 shown in Figure 3A.

Similarly, conductive atoms 52 receive an external potential through connection 42, and when a suitable potential is applied, a shaped field region is produced at location X2 . Also, a shaped field region can be produced at site X3 by the application of a suitable potential to external connection 43.

Referring now to Figure 3B, a suitable external 41 potential is applied to connections 41 and 42 and vapour deposition is carried out, for example MOCVD or MBE. As a result of the applied potentials, atoms of a particular type are be preferentially attracted to the sites on the substrate. As shown in Figure 3B, atoms 2 71 and 7 are preferentially attracted to the sites X and X2.

After the first deposition shown in Figure 3B has been achieved, a different set of potentials are applied to the connections 4 and a further, different vapour source may be used so that atoms of a different type are preferentially attracted to different sites on the substrate e.g. site X3. In this way, it is possible to build a multi-layer structure with atoms of different types being preferentially deposited in different sites, by suitable application of different configurations of control potentials to the external connections 4.

The fabrication process is much quicker than prior proposals which solely utilised the STM. The relatively slow processing of the substrate with an STM need only be carried out for the substrate itself and the overlayers are produced by e.g. vapour deposition, which is much quicker than the laborious process of manipulating individual atoms or molecules with a STM.

Furthermore by means of the invention, many identical bases may be formed on the substrate using an STM, for example an STM including a plurality of tips formed on a common substrate to write structures in parallel.

Thereafter, individual bases thus formed, can be used to make different atomic scale structures by appropriate masking and vapour deposition, using different potential configurations applied to the connections 4 for an individual base. Thus, a plurality of different circuits can be built up on identical bases by selecting appropriate materials for vapour deposition and suitable control potentials applied to the connections 4. Thus, the base can serve a role corresponding to that of an uncommitted logic array in conventional circuit manufacture.

Thus, in accordance with the invention, each device can be built up mono-layer by mono-layer, or in a more granular fashion to achieve a 3-dimensional device or circuit with no lithography after the first layer i.e.

the base.

Deposition of atoms or molecules at a particular site X can be monitored by checking the electrical characteristics of the corresponding external connections 4 i.e. to note a change of resistance that will be associated with deposition of an atom at the site. Unwanted material can be removed from the site by applying an appropriate voltage pulse to the connection(s). Thus, error correction is possible during manufacture.

A further example of the method according to the invention is shown schematically in Figure 4. In Figure 4A, an array of atoms in a region 1 of the base includes two generally parallel lines of conductive atoms 5 shown in shaded outline, disposed between non-conductive atoms 6.

In Figure 4B, control potentials are applied to the conductive atoms 5 such that a deposited atom 7 is preferentially attracted to a site between the conductive atoms 6, the resulting deposition being shown in Figure 4C. Typically the atom is deposited from a gaseous complex by MOCVD.

Thereafter, as shown in Figure 4D, an atom 8 of a different type is deposited. At this time, different potentials are applied to the conductive atoms 5 and as a result, the atom 8 is preferentially attracted to the site shown in Figure 4E. Thereafter the potentials are removed. The atoms 7, 8 are first physisorbed and chemisorbed into the structure.

Whilst in the foregoing the structure has been described in terms of individual atoms, it will be appreciated that molecular structures may be preferentially located on the substrate in a similar manner and complicated, long chain molecules can be constructed in this way. Reference is also directed to our aforesaid specification GB-A-2258236.

Claims (12)

1. A method of forming a nano-scale electronic device comprising manipulating atoms on a substrate to form a conductive atomic scale pattern, applying at least one electrical potential to the pattern, and depositing material on the pattern whereby atoms or molecules selectively aggregate to predetermined parts of the pattern in dependence upon the configuration thereof and the potential applied thereto.

2. A method according to claim 1 including applying a first electrical potential to the pattern and depositing a first material thereon, and thereafter applying a second potential to the pattern and depositing a second material thereon.

3. A method according to claim 1 or 2, including depositing the or each said material by MBE or MOCVD.

4. A method according to any preceding claim wherein the atomic manipulation on the substrate is carried out by an atomic probe.

5. A method according to claim 4, wherein said probe comprises a STM.

6. A method according to any preceding claim including forming a plurality of said atomic scale patterns on a substrate and depositing material on each said pattern concurrently.

7. A method according to any preceding claim including forming electrical connections to said pattern by lithography.

8. A method according to claim 7 including defining bond pads by optical lithography, and forming connections from said bond pads to said pattern by electron beam lithography.

9. A method according to any preceding claim wherein said substrate is formed of gallium arsenide.

10. A method according to claim 6 wherein different sets of electrical potentials are applied to said plurality of patterns respectively, whereby to form different structures thereon.

11. A method of forming a nano-scale electronic device substantially as hereinbefore described with reference to the accompanying drawings.

12. A nano-scale electronic device formed by a method according to any preceding claim.