GB2276981A

GB2276981A - Integrated circuits

Info

Publication number: GB2276981A
Application number: GB9405770A
Authority: GB
Inventors: Philippe Lance
Original assignee: Motorola Semiconducteurs SA
Current assignee: Freescale Semiconducteurs France SAS
Priority date: 1993-04-08
Filing date: 1994-03-23
Publication date: 1994-10-12
Anticipated expiration: 2014-03-23
Also published as: FR2703830A1; DE4411859A1; FR2703830B1; GB9405770D0; GB2276981B; CN1035090C; CN1095863A; JPH07130761A

Description

2276981 SWITCHING TRANSISTOR ARRANGEMENT

Backaround of the Invention

This invention relates to switching transistor arrangements.

Switching transistors are widely used in electronics to switch high power. In a known switching transistor arrangement a diode is connected in anti-parallel with a power transistor's base-emitter junction. The role of this diode is to provide a reverse current path from the emitter and the collector. Such provision is necessary when, for example, the power transistor is to switch a current flowing through an inductance: since the current through an inductance cannot stop immediately the transistor switches, the diode provides a path for this current. One example of a switching transistor arrangement of this kind is in the halfbridge self-oscillating circuit commonly used in electronic ballast circuits for fluorescent lights.

The cost of switching transistor arrangements for such applications is very critical, and it would therefore be desirable to integrate the diode into the same integrated circuit with the switching transistor, in order to reduce cost. Unfortunately, prior art attempts to provide this diode integrally with the switching transistor have resulted in unpredictable and unstable variation in the switching behaviour of the transistor.

Summarv of the Invention In accordance with the invention there is provided a switching transistor circuit arrangement comprising a semiconductor substrate having:

2 first and second semiconductor regions which are mutually interdigitated and which form respectively a control electrode and a signal electrode of the transistor; a third semiconductor region forming a second signal electrode of the transistor; and a fourth semiconductor region extending with the first and second semiconductor regions and forming with the third semiconductor region a diode junction which extends over a substantial area of the substrate.

It has been found that, by providing the third semiconductor region extending with the first and second semiconductor regions to form the diode junction extending over a substantial area of the substrate, good, predictable 15 and stable switching behaviour is obtained.

Brief DescrfiDtion of the Drawinas One switching transistor arrangement in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIGS. 1.1, 1.2 and 1.3 show respectively a plan view, a cross-sectional view and a schematic circuit diagram of a known integrated circuit switching transistor arrangement; FIGS. 2.1, 2.2 and 2.3 show respectively a plan view, a crosssectional view and a schematic circuit diagram of an integrated circuit switching transistor arrangement in accordance with the invention.

I 3 Description of the Preferred Embodiment

Referring now to FIGS. 1.1, 1.2 and 1.3, a known switching transistor circuit arrangement 100 has a substrate 102 of N+ silicon, and a N- layer 104 thereon. overlying the layer 104 is a P+ region 106. Within the region 106 is formed a N+ region 108 having fingers 108A, 108B, 108C. Interdigitated metalizations 110 and 112 are formed respectively on the regions 106 and 108.

Thus, it will be understood that the regions 106 and 108 respectively constitute base and emitter regions which are mutually interdigitated, and the layer 104 constitutes a collector region. Thus the integrated circuit shown in FIGS. 1.1 and 1.2 constitutes a NPN bipolar transistor 114 as shown in FIG. 1.3 with an interdigitated base/emitter which gives good high-power switching behaviour.

However, as mentioned above, attempts to integrate a diode into this known power transistor (such as forming a diode under the emitter bond pad requiring additional processing steps) have resulted in unpredictable and unstable variation in the switching behaviour of the transistor, requiring post-production testing and selection of devices of satisfactory behaviour from a production batch.

Referring now to FIGS. 2.1, 2.2 and 2.3, in an integrated circuit semiconductor device (not shown) a switching transistor circuit arrangement 200 is provided.

The switching transistor circuit arrangement 200 has a substrate 202 of 1V+ silicon, and a N- layer 204 thereon.

Within the layer 204 is a P+ region 206 having fingers 206A, 206B. Also within the layer 204, and extending interdigitated between the fingers 206A and 206B, there is formed a further P+ region 207. Within the region 206 is formed a N+ region 208 having fingers 208A, 208D.

Interdigitated metalizations 210 and 212 are formed E - 4 respectively on the regions 206 and extending across the regions 208 and 207.

Thus, it will be understood that the regions 206 and 208 respectively constitute base and emitter regions which are mutually interdigitated, and the layer 204 constitutes a collector region. Thus the integrated circuit shown in FIGS. 2.1 and 2.2 constitutes a NPIq bipolar transistor 214 as shown in FIG. 2.3 with an interdigitated base/emitter which gives good high-power switching behaviour.

It will further be understood that the region 207 constitutes, with the Nlayer 204, a diode 216 connected in anti-parallel with the base-emitter junction of the transistor. It will further be appreciated that since the junction of the diode 214 formed between the P+ region 207 and the Nlayer 204 extends over a substantial area of the substrate (in fact, over approximately the same total area as the base-emitter junction of the switching transistor), the switching transistor exhibits no deleterious effect from the presence of the diode, enabling predictable and stable switching behaviour to be obtained.

Thus, it will be appreciated that the switching transistor arrangement of FIGS. 2.1, 2.2 and 2.3 allows anti- parallel diode function to be satisfactorily integrated with a power switching transistor.

It will also be appreciated that the P+ region 206, the P+ region 207 and the N- layer 204 constitute a PNP bipolar transistor 218. It will be appreciated that by appropriately arranging the N+ gap between the P+ region 206 and the P+ region 207 (thus determining the width of the base of the PNP transistor 218) the PNP transistor 218 can be made to function fully satisfactorily (even at high switching rates) as a "Baker clamp", avoiding hard saturation of the NPN transistor 214.

It will, further be appreciated that the switching transistor arrangement of FIGS. 2.1, 2.2 and 2.3 allows stored charge on the base junction of the transistor 214 to be removed from the base of the transistor rather than simply from its emitter as in prior art devices such as in FIG. 1. Thus, the switching transistor arrangement of FIGS. 2.1, 2.2 and 2.3 may be used for any range of carrier lifetime (even very high lifetimes). Similarly, the die size may be reduced by as much as 30% compared with prior art arrangements, allowing greater yields and subsequent cost reductions.

It will appreciated that, although not so shown in FIGS. 2.1 and 2.2, if desired the collector connection of the arrangement may he taken directly from the N+ substrate 202. It will also be appreciated that, although not so shown in FIGS. 2.1 and 2.2, a guard ring of 1V+ material may be formed in the N- layer 204 around the other areas 206 and 207.

It will be appreciated that the switching transistor arrangement of FIGS. 2.1, 2.2 and 2.3 may be fabricated by a standard bipolar process, and requires no additional processing steps compared with prior art arrangement such as in FIG. 1.

It will be appreciated that various other modifications or alternatives to the above described embodiment will be apparent to a person skilled in the art without departing from the inventive concept.

Claims

1. A switching transistor circuit arrangement comprising a semiconductor substrate having:

first and second semiconductor regions which are mutually interdigitated and which form respectively a control electrode and a signal electrode of the transistor; a third semiconductor region forming a second signal electrode of the transistor; and a fourth semiconductor region extending with the first and second semiconductor regions and forming with the third semiconductor region a diode junction which extends over a substantial area of the substrate.

2. A circuit arrangement according to claim 1 wherein the fourth semiconductor region is interdigitated with the first and second semiconductor regions.

3. A circuit arrangement according to claim 1 or 2 wherein the fourth semiconductor region is arranged to form, with the third semiconductor region and the first semiconductor region, a clamp transistor.

4. A circuit arrangement according to claim 1, 2 or 3 wherein the switching transistor is a NPN transistor.

5. A circuit arrangement according to claim 4 when dependent from claim 3 wherein the clamp transistor is a PNP transistor

6. A switching transistor circuit arrangement substantially as hereinbefore described with reference to Fig. 2 of the drawings.

7. An integrated circuit device containing a switching transistor circuit arrangement according to any preceding claim.