GB2272315B - Asynchronous modular bus architecture with burst capability - Google Patents
Asynchronous modular bus architecture with burst capabilityInfo
- Publication number
- GB2272315B GB2272315B GB9325945A GB9325945A GB2272315B GB 2272315 B GB2272315 B GB 2272315B GB 9325945 A GB9325945 A GB 9325945A GB 9325945 A GB9325945 A GB 9325945A GB 2272315 B GB2272315 B GB 2272315B
- Authority
- GB
- United Kingdom
- Prior art keywords
- bus architecture
- modular bus
- burst capability
- asynchronous
- asynchronous modular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Communication Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72472691A | 1991-07-02 | 1991-07-02 | |
PCT/US1992/005482 WO1993001552A1 (en) | 1991-07-02 | 1992-06-30 | Asynchronous modular bus architecture with burst capability |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9325945D0 GB9325945D0 (en) | 1994-03-02 |
GB2272315A GB2272315A (en) | 1994-05-11 |
GB2272315B true GB2272315B (en) | 1995-10-04 |
Family
ID=24911646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9325945A Expired - Fee Related GB2272315B (en) | 1991-07-02 | 1992-06-30 | Asynchronous modular bus architecture with burst capability |
Country Status (3)
Country | Link |
---|---|
DE (2) | DE4292241T1 (de) |
GB (1) | GB2272315B (de) |
WO (1) | WO1993001552A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5526512A (en) * | 1993-09-20 | 1996-06-11 | International Business Machines Corporation | Dynamic management of snoop granularity for a coherent asynchronous DMA cache |
JP3579461B2 (ja) * | 1993-10-15 | 2004-10-20 | 株式会社ルネサステクノロジ | データ処理システム及びデータ処理装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4366539A (en) * | 1980-10-31 | 1982-12-28 | Honeywell Information Systems Inc. | Memory controller with burst mode capability |
US4370712A (en) * | 1980-10-31 | 1983-01-25 | Honeywell Information Systems Inc. | Memory controller with address independent burst mode capability |
US4376972A (en) * | 1980-01-08 | 1983-03-15 | Honeywell Information Systems Inc. | Sequential word aligned address apparatus |
US4451880A (en) * | 1980-10-31 | 1984-05-29 | Honeywell Information Systems Inc. | Memory controller with interleaved queuing apparatus |
US4558429A (en) * | 1981-12-17 | 1985-12-10 | Honeywell Information Systems Inc. | Pause apparatus for a memory controller with interleaved queuing apparatus |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5134699A (en) * | 1988-06-24 | 1992-07-28 | Advanced Micro Devices, Inc. | Programmable burst data transfer apparatus and technique |
US5159679A (en) * | 1988-09-09 | 1992-10-27 | Compaq Computer Corporation | Computer system with high speed data transfer capabilities |
-
1992
- 1992-06-30 GB GB9325945A patent/GB2272315B/en not_active Expired - Fee Related
- 1992-06-30 WO PCT/US1992/005482 patent/WO1993001552A1/en active Application Filing
- 1992-06-30 DE DE4292241T patent/DE4292241T1/de active Pending
- 1992-06-30 DE DE4292241A patent/DE4292241C2/de not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4376972A (en) * | 1980-01-08 | 1983-03-15 | Honeywell Information Systems Inc. | Sequential word aligned address apparatus |
US4366539A (en) * | 1980-10-31 | 1982-12-28 | Honeywell Information Systems Inc. | Memory controller with burst mode capability |
US4370712A (en) * | 1980-10-31 | 1983-01-25 | Honeywell Information Systems Inc. | Memory controller with address independent burst mode capability |
US4451880A (en) * | 1980-10-31 | 1984-05-29 | Honeywell Information Systems Inc. | Memory controller with interleaved queuing apparatus |
US4558429A (en) * | 1981-12-17 | 1985-12-10 | Honeywell Information Systems Inc. | Pause apparatus for a memory controller with interleaved queuing apparatus |
Also Published As
Publication number | Publication date |
---|---|
GB9325945D0 (en) | 1994-03-02 |
DE4292241T1 (de) | 1994-05-05 |
WO1993001552A1 (en) | 1993-01-21 |
DE4292241C2 (de) | 1998-04-16 |
GB2272315A (en) | 1994-05-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100630 |