GB2268013A - Frequency modulator - Google Patents
Frequency modulator Download PDFInfo
- Publication number
- GB2268013A GB2268013A GB9212583A GB9212583A GB2268013A GB 2268013 A GB2268013 A GB 2268013A GB 9212583 A GB9212583 A GB 9212583A GB 9212583 A GB9212583 A GB 9212583A GB 2268013 A GB2268013 A GB 2268013A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- input
- output
- control
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C3/00—Angle modulation
- H03C3/02—Details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplitude Modulation (AREA)
- Amplifiers (AREA)
Abstract
This invention relates to a frequency modulator (Fig. 2), such as for non-return-to-zero (NRZ) FM Modulation. A sample and hold element (12) is provided having an analog input for receiving an analog input signal, a control input (18) for receiving first and second control signals and an output. It is arranged to pass the analog signal to its output when the first control signal is applied to the control input and to provide a nominal middle voltage (u0) on its output when the second control signal is applied to its control input. Binary modulation elements (20, 21, 22) are provided, arranged to commence binary modulation of the output about said nominal middle voltage when said second control signal is applied to said control input. The arrangement avoids disturbance of voltage stabilising circuitry associated with the analog modulation portion by the binary modulation signal. <IMAGE>
Description
BINARY MODULATOR
Field of the Invention
This invention relates to binary modulators, such as for nonreturn-tozero (NRZ) FM Modulation.
Backaround of the Invention
For data transmission a NRZFM-Modulation is often used to transport binary information via RF-Channels. NRZ-FM means hat the two binary values are directly transformed by switchng between two discrete RF- carrier frequencies (f+ for "high and f - f or 11 low"). The f requency f 0 (f 0 = (f + = f _) /2) is a fictive middle frequency that will actually never be transmitted. But high stability of fo is needed to guarantee a d- ,st-,nct decision threshold between both modulation values.
Modulation is frequently carried out by a voltage controlled oscillator (VCO). To achieve NRZ f+ and ffrequency offsets, it is necessary to DCcouple the binary modulation signal source with the WO.
A problem exists when there is a need to provide both voice (or tone) modulation and binary modulation. Both the voice signal and the DC binary modulation source need to be applied about a highly stable centre voltage, but the binary modulation signal source has a tendency to disturb the accurate setting of any stabilising circuitry used for stabilising the centre voltage to which the voice signal is applied.
Summary of the Invention
According to the present invention, there is provided a binary modulator comprising: a sample and hold element having an analog input for receiving an analog signal, a control input for receiving first and second control signals and an output, the element is arranged to pass the analog signal to its output when the first control signal is applied to the control input and to provide a nominal middle voltage on its output when the second control signal is applied to its control input. The modulator further comprises binary modulation means arranged to commence binary modulation of the output about the nominal middle voltage when the second control signal is applied to the control input.
The invention has the advantage of holding the nominal middle voltage before commencing binary modulation and thereby de-coupling the source of binary modulation signal from any stabilizing circuitry, for example temperature compensating circuitry, associated with the analog input.
The binary modulation means may comprise means for applying first and second voltages of equal and opposite polarity to the output. 1 The sample and hold element may comprise two amplifier stages, for example providing unity amplification in total, with the means for binary modulation being applied to the input of the second stage. The amplifier stages may be decoupled upon change of the control input signal from the first control signal to the second control signal.
A preferred embodiment of the invention will now be described by way of example only, with reference to the drawings.
Brief Description of the Drawings
Fig. 1 shows a preferred embodiment of the invention in an analog mode Fig. 2 shows the circuit of Fig. 1 in a digital mode (only the elements common to both modes being shown) and Fig. 3 shows various signals in the circuits of Figs. 1 and 2.
Referring to Fig. 1, there is shown an analog input 10, temperature compensating circuitry 11, a sample and hold amplifier 12, a capacitor 13 and a voltage control oscillator 14. The sample and hold amplifier 12 has first and second stages 15 and 16 and a switch 17 between these stages with a control input 18 controlling the switch.
In the analog mode, as shown, the switch 18 is closed and a further switch 19 connects the capacitor 13 to ground.
Sample and hold amplifiers are characterized by two operational modes. In sample mode, the output voltage follows the input voltage very accurately. The word "amplifier" is a little inaccurate, because the overall amplification of the device is one. The word is used, because first and second stages 15 and 16 are operational amplifiers with high input impedances.
The circuit of Fig. 1 is in the sample mode and, when an analog voice or tone signal is applied to the input 10, as indicated by the reference uan, this signal causes the input of the sample and hold amplifier 12 to vary about a nominal bias voltage uo, which is accurately set by the temperature compensating circuitry 11. Accordingly, the output of the sample and hold amplifier 12 fluctuates about the accurate centre voltage and causes the VC0 14 to output a signal frequency modulated about fo.
In the hold mode of the sample and hold amplifier, the output voltage is held at the level of the last sample input voltage. The amplifier now operates as an analog voltage storage device for a certain time which depends on the typical droop rate of the device used.
Whereas sample and hold amplifiers are normally used as buffers for analog-to-digital converters, in order to hold the sample voltage constant during the conversion time of the converter, in this application, the sample and hold amplifier works as a voltage sampler for uo, as follows.
Referring to Fig. 2, the binary modulation mode is shown, in which a second control signal is applied to the control input 18 of the sample and hold amplifier 12, causing the switch 17 to open. Provided that this takes place when there is no signal applied to the analog input 10, the capacitor 13 will store a voltage corresponding to uo. This gives the necessary high frequency stability. Using a further two-way switch 20 and equal and opposite voltage sources 21 and 22, the input of the second stage 16 of the amplifier 12 is now switched between voltages u+ and u_. The 4 frequencies resulting from the WO 14 lie symmetrically above and below fo. The switching of switch 20 is controlled by the binary signal source ubin. The sample and hold amplifier 12 is now operating as a summing device to the stored temperature compensated steering voltage uo.
In Fig. 3, the two modes of operation are shown in a time diagram with the resulting WO frequencies.
Signal A is the analog signal applied to input 10. At time tbin, binary operation commences. At this time, the voice signal A has died to a level negligibly removed from uo. The switch 17 is opened (signal C) and ubin is applied to switch 20 (signal B). The combined output of the two modes in shown as signal D.
It will be understood that the switch 20 and the opposite voltages 21 and 22 can be implemented using a CMOS transmission gate, a voltage divider and an operational amplifier.
Accordingly, a simple binary modulator has been described which controls a WO without losing high frequency stability. This is achieved by completely de-coupling the temperature compensator network from the binary signal source during modulation so that neither can influence the other. The additional modulator cannot alter the overall frequency stability. The circuitry has the great advantage of being usable as an addon circuit to a conventional radio. In this way, it provides a two- mode modulator for analogue FM or binary NRZ-FM.
Claims (5)
1. A binary modulator comprising: a sample and hold element having an analog input for receiving an analog input signal, a control input for receiving first and second control signals and an output said element being arranged to pass the analog signal to its output when the first control signal is applied to the control input and to provide a nominal middle voltage on its output when the second control signal is applied to its control input and further comprising binary modulation means arranged to commence binary modulation of the output about said nominal middle voltage when said second control signal is applied to said control input.
2. A modulator according to claim 1, further comprising temperature compensating means for maintaining a temperature compensated bias voltage on the analog input.
3. A modulator according to claim 1 or 2 wherein the binary modulation means comprise means for applying first and second voltages of equal and opposite polarity to said output.
4. A modulator according to claim 3, wherein the sample and hold element comprises two amplifier stages and the means for binary modulation applies the first and second voltages to the input of the second stage.
5. A modulator according to claim 4, wherein the sample and hold element comprises decoupling means for decoupling the stages upon change of the control input signal from the first control signal to the second control signal.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9212583A GB2268013B (en) | 1992-06-13 | 1992-06-13 | Binary modulator |
DE19934317111 DE4317111A1 (en) | 1992-06-13 | 1993-05-21 | Binary modulator |
HK97102166A HK1000614A1 (en) | 1992-06-13 | 1997-11-17 | Binary modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9212583A GB2268013B (en) | 1992-06-13 | 1992-06-13 | Binary modulator |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9212583D0 GB9212583D0 (en) | 1992-07-29 |
GB2268013A true GB2268013A (en) | 1993-12-22 |
GB2268013B GB2268013B (en) | 1995-10-25 |
Family
ID=10717043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9212583A Expired - Fee Related GB2268013B (en) | 1992-06-13 | 1992-06-13 | Binary modulator |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE4317111A1 (en) |
GB (1) | GB2268013B (en) |
HK (1) | HK1000614A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0647015A3 (en) * | 1993-09-28 | 1995-12-27 | Plessey Semiconductors Ltd | Modulators. |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE50102224D1 (en) * | 2001-12-07 | 2004-06-09 | Aastra Technologies Ltd | Modulator using a phase locked loop and method therefor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3651428A (en) * | 1970-05-25 | 1972-03-21 | Beltone Electronics Corp | Gradual on-off keying circuit for an oscillator |
GB2179480A (en) * | 1985-08-13 | 1987-03-04 | Notifier Co | Security systems |
-
1992
- 1992-06-13 GB GB9212583A patent/GB2268013B/en not_active Expired - Fee Related
-
1993
- 1993-05-21 DE DE19934317111 patent/DE4317111A1/en not_active Withdrawn
-
1997
- 1997-11-17 HK HK97102166A patent/HK1000614A1/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3651428A (en) * | 1970-05-25 | 1972-03-21 | Beltone Electronics Corp | Gradual on-off keying circuit for an oscillator |
GB2179480A (en) * | 1985-08-13 | 1987-03-04 | Notifier Co | Security systems |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0647015A3 (en) * | 1993-09-28 | 1995-12-27 | Plessey Semiconductors Ltd | Modulators. |
Also Published As
Publication number | Publication date |
---|---|
GB9212583D0 (en) | 1992-07-29 |
DE4317111A1 (en) | 1993-12-16 |
HK1000614A1 (en) | 1998-04-09 |
GB2268013B (en) | 1995-10-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19990613 |