GB2267617A - A digital sample and hold phase detector - Google Patents

Abstract

The digital sample and hold phase detector compares the phase relationship between input pulses and a high frequency reference clock. A digital counter arrangement (15) counts the high frequency reference clock to produce a digital ramp signal and a digital sampling arrangement (13, 16) coupled to the input pulses and an output of the counter arrangement (15) enables the input pulses to sample the digital ramp signal and produce a digital phase difference signal. <IMAGE>

Description

A DIGITAL SAMPLE AND HOLD PHASE DETECTOR The present invention relates to sample and hold phase detectors and more particularly to digital sample and hold phase detectors.

Known sample and hold phase detectors used in phase locked loops and phase measuring applications are analog in nature. Figure 1 shows an example of a prior art analog sample and hold phase detector employed in a phase-locked loop. The analog sample and hold phase detector 1 includes an analog ramp generator 2 responsive to the reference frequency to produce an analog ramp having a period equal to that of the reference frequency. The voltage controlled oscillator 3 produces an RF (radio frequency) output which is divided by N in a frequency divider 4. Under phase locked conditions, the output period of the divider 4 is equal to that of analog ramp produced at the output of generator 2. The output of divider 4 is formed into a narrow pulse which samples the voltage level of the analog ramp by means of, for instance, a semi-conductor switch which is shown schematically as a mechanical switch 5. The sample voltage is held by a holding capacitor 6 between samples. Under locked conditions, the voltage held in capacitor 6 is proportional to the phase difference between the RF output of oscillator 3 divided by N and the reference frequency. This voltage of capacitor 6 is amplified and integrated in amplifier-integrator 7 and fed back negatively to control the frequency of oscillator 3 to maintain phase lock.

N of divider 4, depending on the applicaiton, can be any number including one and fractions. When N is fractional, the phase locked frequency source assembly is often known as a "fractional division" or "fractional-N" frequency synthesizer. The output voltage of the sample and hold phase detector 1 will change somewhat in amplitude, causing a phase measurement error with temperature, with bias voltage variation and with aging. When used in a phase-locked loop, this error will be reflected in a phase change in the RF output of the oscillator 3. In some applications, the phase detector output voltage is used as an indication of phase offset between signal sources.

Any detector non-linearities will cause a phase measurement error. The non-linearities are worse at high frequencies where it is difficult to generate a linear ramp. When the analog sample and hold phase detector 1 is used in a fractional division frequency synthesizer, non-linearities of a couple of per cent are capable of producing rather strong FM (frequency modulation) sidebands around the oscillator 3 operating frequency (carrier).

The present invention seeks to provide a digital sample and hold phase detector that may be employed in phase locked loops and for phase measurement of the phase offset between two input signals.

According to the invention there is provided a digital sample and hold phase detector having a pulse signal input for receiving input pulses and a clock input for receiving a high frequency reference clock signal the detector comprising digital connector means coupled with the clock input for counting the clock pulses to produce a digital ramp signal output, and digital sampling means coupled with the pulse signal input and the digital ramp signal output of the digital counter means to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

In order that the invention and its various other preferred features may be understood more easily, some embodiments thereof will now be described, by way of example only, with reference to the drawings, in which: Figure 1 is a block diagram of a prior art analog sample and hold phase detector employed in a phased locked loop as previously described, Figure 2 is a block diagram of a digital sample and hold phase detector, constructed in accordance with the invention, employed in a phase locked loop, Figure 3 is a block diagram of one embodiment of a digital sample and hold phase detector constructed in accordance with the present invention, Figure 4 is a block diagram of a second embodiment of a digital sample and hold phase detector constructed in accordance with the present invnetion, and Figure 5 is a block diagram of a third embodiment of a digital sample and hold phase detector constructed in accordance with the present invention.

A description of the digital sample and hold phase detector of the present application will be described in the environment of the phase locked loop. However, it is to be noted that the digital sample and hold phase detector of the present application may be also employed for other purposes, for example to provide an indication of the phase offset or phase difference between two input signals.

Referring to Figure 2, a digital sample and hold phase detector 8 is shown in a phase locked loop including a voltage controlled oscillator 9, frequency divider 10 and amplifier-integrater 11 applying the phase error control voltage to the tuning input of the voltage controlled oscillator 9 with the error voltage resulting from the operation of detector 8. All the processing in detector 8 except for the digital to analog converter 12 is done digitally and, therefore, the non-linearity and temperature shortcomings mentioned hereinabove with respect to the analog sample and hold phase detector is substantially avoided.

As previously mentioned with reference to Figure 1 the output of frequency divider 10 provides a sampling pulse which in tflis case is operated upon by the Count Enable, Clear and Latch Control circuit 13 to produce a not Count Enable Signal (CE), a CLEAR signal and a LATCH signal. A high frequency reference or clock is passed through OR gate 14 when the -E signal is low or logic "0" so as to provide the high frequency reference clock at the count input of counter 15. The incrementing or decrementing binary or digital output word of counter 15 forms a digital reference "ramp" which is "sampled" by the sampling pulse at the output of divider 10 or a pulse derived therefrom. The sampling takes place in latches 16 under the control of the LATCH signal. The "sampled" words stored in latch 16 are converted to an analog voltage by the digital to analog converter 12.

Referring to Figure 3, there is illustrated therein one embodiment of the digital sample and hold phase detector 8 of Figure 2. The sampling pulse from divider 10 of Figure 2 is synchronized with the high frequency reference clock in circuit 20 and the high frequency reference clock is counted in an M-bit synchronous counter 21. The synchronized sampling pulse at the output of circuit 20 is tben used to latch the accumulated contents of counter 21 in latches 22 until the next sampling pulse arrives, at which time the latches 22 are updated. The data stored in latches 22 would then be coupled to converter 12 of Figure 2 and is a digital word which is proportional to the time delay (or phase difference) between reset of counter 21 and the time the sampling pulse appears.

The high frequency reference clock drives the synchronous counter 21 which increments or decrements its binary output data word after each clock pulse. Counter 21 reaches terminal count and resets at the rate of fR 12M where f HC HC is a frequency of the high frequency reference clock and M is the number of output bits from counter 21.

The output word or counter 21 is often referred to as the reference frequency fR or reference "ramp". Under normal steady state conditions the frequency of the sampling pulse train F5 equals the reference frequency fR The phase detector of Figure 3 has a full 21 radian dynamic range with an output resolution of 2n2M radians of phase.

Referring to Figure 4, there is illustrated therein a block diagram of an alternative arrangement for phase detector 8 employing ripple counters instead of synchronous counters. Ripple counters can work at gigahertz rates. In this configuration, after a sampling pulse arrives and triggers a flip flop 23, the Q output therefrom is coupled to OR gate 24 to inhibit the high frequency reference clock from clocking phase detector counter 25.

The Q output of "D" type flip flop 23 is normally low or logic "0" and when the sampling pulse clocks flip flop 23 the Q output becomes high or logic "one". Thus, when one input to OR gate 24 is high upon the occurrence of the sampling pulse the high frequency reference clock is blocked by gate 24 and cannot clock the counter 25. Time is allowed for the ripple counter data outputs to stabilize after which the data is latched in latches 26. A second M-bit ripple counter 27 produces a reference frequency clock fR which clears the phase detector counter 25 and flip flop 23 and restarts the counter cycle via the flip flop 23 and gate 24. The clear pulse for clearing flip flops 23 and counter 25 is produced in clear pulse generator 28. Delay circuit 29 delays the sampling pulse by a time tD until ripple counter 25 outputs have time to stabilise.

As the frequency increases, the time (tD it takes for the ripple counter 25 to stabilise becomes a significant portion of the reference frequency period and the dynamic range of the phase detector becomes limited. The dynamic range can be defined as R=[(TR - tD)/TR] 2n radians, where TR = l/fR If the range limitation is unacceptable the arrangement of Figure 5 may be employed wherein two ripple counters 30 and 31 are employed as the phase detector counters with the outputs of these two counters 30 and 31 being multiplexed in multiplexer 32. As in Figure 4 the sampling pulse is coupled to "D" type flip flop 33 but in this case the Q output of the flip flop is coupled to OR gates 34 and 35 for controlling the input of the high frequency reference clock to ripple counters 30 and 31.

Ripple counter 36 provides the reference clock from the high frequency reference clock and is divided by two in flip flop 37 with the Q output of flip flop 37 being coupled to OR gate 34 and the Q output of flip flop 37 being coupled to OR gate 35.

The inputs from flip flop 37 to gates 34 and 35 control counter 30 to count at one time while counter 31 is settling and vice versa. The output of counter 36 controls the clearing of flip flop 33 and clears pulse generators 38 and 39 which responsive to the Q and Q outputs of flip flop 37 to control the clearing of counters of 30 and 31, respectively. The Q output of flip flop 37 controls multiplexer 32 and the Q output of flip flop 33 controls latches 40 the outputs of which are coupled to converter 12 of Figure 2.

Claims (11)

CLAIMS:

1. A digital sample and hold phase detector having- a pulse signal input for receiving input pulses and a clock input for receiving a high frequency reference clock signal the detector comprising digital connector means coupled with the clock input for counting the clock pulses to produce a digital ramp signal output, and digital sampling means coupled with the pulse signal input and the digital ramp signal output of the digital counter means to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

2. A phase detector as claimed in claim 1, including a digital-to-analog converter coupled to the sampling means to convert the digital phase differences signal into an analog phase difference signal.

3 A phase detector as claimed in claim 1 or 2, wherein the digital counter means comprises a digital counter, and a gate having an output coupled to an input of the counter, a first input coupled with the clock input and a second input coupled to the sampling means to control the coupling of the high frequency reference clock to the counter in response to the input pulses.

4. A phase detector as claimed in any one of claims 1 to 3, wherein the sampling means comprises latches coupled to said counter controlled by the input pulses.

5. A phase detector as claimed in any one of the preceding claims, wherein the counter means comprises an M-bit synchronous counter coupled to the high frequency reference clock to produce the ramp signal, where M is an integer, and the sampling means comprises a synchronizing circuit coupled with the input pulses and the high frequency reference clock to synchronize the input pulses to the high frequency reference clock, and latches coupled to the synchronizing circuit and the counter to sample the ramp signal with the synchronized input pulses.

6. A phase detector as claimed in any one of claims 1 to 4, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal, where M is an integer, a gate having an output coupled to a count input of the first counter, a first input coupled to the high frequency reference clock and a second input having a count enable signal coupled thereto to control passage of the high frequency reference clock to the first counter, and the sampling means includes a D-type flip flop coupled to the input pulses to produce the count enable signal, a second M-bit ripple counter coupled to the high frequency reference clock, a clear pulse generator coupled to the second counter, the first counter and the flip flop to produce a clear pulse for clearing the first counter and the flip flop, a delay means coupled to the flip flop responding to said count enable signal to produce a sampling pulse delayed a predetermined amount and a sampling pulse delayed a predetermined amount related to settling time of the first counter, and latches coupled to the first counter and the delay means to enable sampling of the digital ramp signal to the sampling pulse to produce the digital phase difference signal.

7. A phase detector as claimed in any one of claims 1 to 4, wherein the counter means includes a first M-bit ripple counter to produce the digital ramp signal during first time periods, where M is an integer, a second M-bit ripple counter to produce the digital ramp signal during second time periods each disposed between different adjacent ones of the first time periods, a first gate having an output coupled to the first counter, a first input coupled to the high frequency reference clock, a second input having a first count enable signal coupled thereto and a third input having a second count enable signal coupled thereto, the first and second count enable signals controlling passage of the high frequency reference clock to the first counter, and a second gate having an output coupled to the second counter, a first input coupled to the high frequency reference clock, a second input having the first count enable signal coupled thereto and a third input having a third count enable signal coupled thereto, the first and third count enable signals controlling passage of the high frequency reference clock to the second counter; and the sampling means includes a D-type flip flop coupled to the input pulses to produce the first count enable signal, a third M-bit ripple counter coupled to the high frequency reference clock and the flip flop to produce a reference signal to clear the flip flop, a divide-by-two circuit coupled to the first and second gates and the third counter to divide the reference signal in half and to provide at a non-inverting output one of the second and third count enable signals and at an inverting output the other of the second and third count enable signals, a first clear pulse generator coupled between the non-inverting output of the divide-by-two circuit and the first counter to clear the first counter, a second clear pulse generator coupled between the inverting output of the divide-by-two circuit and the second counter to clear the second counter, multiplexing means coupled to the first and second counters and the divide-by-two circuit to provide the digital ramp signal in each of the first and second time periods at an output thereof, and latches coupled to the output of the multiplexing means and the flip flop to enable sampling of the digital ramp signal by the first count enable signal to produce the digital phase difference signal.

8. A phase detector as claimed in any one of claims 1 to 4, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal, where M is an integer, a gate having an output couPled to a count input of the first counter, a first input coupled to the high frequency reference clock and a second input having a count enable signal coupled thereto to control passage of the high frequency reference clock to the first counter, and the sampling means comprises a D-type flip flop coupled to the input pulses to produce the count enable signal, a second M-bit ripple counter coupled to the high frequency reference clock, a delay means coupled to the flip flop responding to the count enable signal to produce a sampling pulse delayed a predetermined amount related to settling time of the first counter, and latches coupled to the first counter and the delay means to enable sampling of the digital ramp signal by the sampling pulse to produce the digital phase difference signal.

9. A phase detector as claimed in any one of claims 1 to 4, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal during first time periods, where M is an integer, a second M-bit ripple counter to produce the digital ramp signal during second time periods each disposed between differenT adjacent ones of the first time periods, a first gate having an output coupled to the first counter, a first input coupled to the high frequency reference clock, a second input having a first count enable signal coupled thereto and a third input having a second count enable signal coupled thereto, the first and second count enable signals controlling passage of the high frequency reference clock to the first counter, and a second gate having an output coupled to the second counter, a first input coupled to said high frequency reference clock, a second input having the first count enable signal coupled thereto and a third input having a third count enable signal coupled thereto, the first and third count enable signals controlling passage of the high frequency reference clock to the second counter, and the sampling means comprising a D-type flip flop coupled to the input pulses to produce the first count enable signal, a third M-bit ripple counter coupled to the high frequency reference clock and the flip flop to produce a reference signal to clear the flip flop, a divide-by-two circuit coupled to the first and second gates and the third counter to deviDe the reference signal in half and to provide at a non-inverting output one of the second and third count enable signals and at an inverting output the other of the second and third count enable signals, multiplexing means coupled to the first and second counters and the divide-by-two circuit to provide the digital ramp signal in each of the first and second time periods at an output thereof, and latches coupled to the output of the multiplexing means and the flip flop to enable sampling of the digital ramp signal by the first count enable signal to produce the digital phase difference signal.

10. A digital sample and hold phase detector substantially as described herein with reference to Figure 2, 3, 4 or 5 of the drawings.

11. A phase locked loop circuit substantially as described herein with reference to Figure 2 of the drawings.

11. A phase locked loop circuit including a digital sample and hold circuit as claimed in any one of the preceding claims.

12. A phase locked loop circuit substantially as described herein with reference to Figure 2 of the drawings.

Amendments to the clains have been fled as flows

1. A digital sample and hold phase detector having a pulse signal input for receiving input pulses and a clock input for receiving a high frequency reference clock. signal- the detector comprising digital counter means coupled with the clock input for counting the clock pulses to produce a digital ramp signal output, and digital sampling means coupled with the pulse signal input and the digital ramp signal output of the digital counter means to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal wherein the sampling means comprises latches coupled to the counter controlled by the input pulses.

2. A phase detector as claimed in claim 1, including a digital-to-analog converter coupled to the sampling means to convert the digital phase differences signal into an analog phase difference signal.

3. A phase detector as claimed in claim 1 or 2, wherein the digital counter means comprises a digital counter, and a gate having an output coupled to an input of the counter, a first input coupled with the clock input and a second input coupled to the sampling means to control the coupling of the high frequency reference clock to the counter in response to the input pulses.

4. A phase detector as claimed in any one of the preceding claims, wherein the counter means comprises an M-bit synchronous counter coupled to the high frequency reference clock to produce the ramp signal, where N is an integer, and the sampling means comprises a synchronizing circuit coupled with the input pulses and the high frequency reference clock to synchronize the input pulses to the high frequency reference clock, and latches coupled to the synchronizing circuit and the counter to sample the ramp signal with the synchronized input pulses.

5. A phase detector as claimed in any one of claims 1 to 3, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal, where M is an integer, a gate having an output coupled to a count input of the first counter, a first input coupled to the high frequency reference clock and a second input having a count enable signal coupled thereto to control passage of the high frequency reference clock to the first counter, and the sampling means includes a D-type flip flop coupled to the input pulses to produce the count enable signal, a second M-bit ripple counter coupled to the high frequency reference clock, a clear pulse generator coupled to the second counter, the first counter and the flip flop to produce a clear pulse for clearing the first counter and the flip flop, a delay means coupled to the flip flop responding to said count enable signal to produce a sampling pulse delayed a predetermined amount and a sampling pulse delayed a predetermined amount related to settling time of the first counter, and latches coupled to the first counter and the delay means to enable sampling of the digital ramp signal to the sampling pulse to produce the digital phase difference signal.

6. A phase detector as claimed in any one of claims 1 to 3, wherein the counter means includes a first M-bit ripple counter to produce the digital ramp signal during first time periods, where M is an integer, a second M-bit ripple counter to produce the digital ramp signal during second time periods each disposed between different adjacent ones of the first time periods, a first gate having an output coupled to the first counter, a first input coupled to the high frequency reference clock, a second input having a first count enable signal coupled thereto and a third input having a second count enable signal coupled thereto, the first and second count enable signals controlling passage of the high frequency reference clock to the first counter, and a second gate having an output coupled to the second counter, a first input coupled to the high frequency reference clock, a second input having the first count enable signal coupled thereto and a third input having a third count enable signal coupled thereto, the first and third count enable signals controlling passage of the high frequency reference clock to the second counter; and the sampling means includes a D-type flip flop coupled to the input pulses to produce the first count enable signal, a third M-bit ripple counter coupled to the high frequency reference clock and the flip flop to produce a reference signal to clear the flip flop, a divide-by-two circuit coupled to the first and second gates and the third counter to divide the reference signal in half and to provide at a non-inverting output one of the second and third count enable signals and at an inverting output the other of the second and third count enable signals, a first clear pulse generator coupled between the non-inverting output of the divide-by-two circuit and the first counter to clear the first counter, a second clear pulse generator coupled between the inverting output of the divide-by-two circuit and the second counter to clear the second counter, multiplexing means coupled to the first and second counters and the divide-by-two circuit to provide the digital ramp signal in each of the first and second time periods at an output thereof, and latches coupled to the output of the multiplexing means and the flip flop to enable sampling of the digital ramp signal by the first count enable signal to produce the digital phase difference signal.

7. A phase detector as claimed in any one of claims 1 to 3, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal, where M is an integer, a gate having an output coupled to a count input of the first counter, a first input coupled to the high frequency reference clock and a second input having a count enable signal coupled thereto to control passage of the high frequency reference clock to the first counter, and the sampling means comprises a D-type flip flop coupled to the input pulses to produce the count enable signal, a second M-bit ripple counter coupled to the high frequency reference clock, a delay means coupled to the flip flop responding to the count enable signal to produce a sampling pulse delayed a predetermined amount related to settling time of the first counter, and latches coupled to the first counter and the delay means to enable sampling of the digital ramp signal by the sampling pulse to produce the digital phase difference signal.

8. A phase detector as claimed in any one of claims 1 to 3, wherein the counter means comprises a first M-bit ripple counter to produce the digital ramp signal during first time periods, where M is an integer, a second M-bit ripple counter to produce the digital ramp signal during second time periods each disposed between differenT adjacent ones of the first time periods, a first gate having an output coupled to the first counter, a first input coupled to the high frequency reference clock, a second input having a first count enable signal coupled thereto and a third input having a second count enable signal coupled thereto, the first and second count enable signals controlling passage of the high frequency reference clock to the first counter, and a second gate having an output coupled to the second counter, a first input coupled to said high frequency reference clock, a second input having the first count enable signal coupled thereto and a third input having a third count enable signal coupled thereto, the first and third count enable signals controlling passage of the high frequency reference clock to the second counter, and the sampling means comprising a D-type flip flop coupled to the input pulses to produce the first count enable signal, a third M-bit ripple counter coupled to the high frequency reference clock and the flip flop to produce a reference signal to clear the flip flop, a divide-by-two circuit coupled to the first and second gates and the third counter to deviDe the reference signal in half and to provide at a non-inverting output one of the second and third count enable signals and at an inverting output the other of the second and third count enable signals, multiplexing means coupled to the first and second counters and the divide-by-two circuit to provide the digital ramp signal in each of the first and second time periods at an output thereof, and latches coupled to the output of the multiplexing means and the flip flop to enable sampling of the digital ramp signal by the first count enable signal to produce the digital phase difference signal.

9. A digital sample and hold phase detector substantially as described herein-with reference to Figure 2,3, 4 or 5 of the drawings.

10. A phase locked loop circuit including a digital sample and hold circuit as claimed in any one of the preceding claims.