GB2265034A

GB2265034A - Bit line control circuit

Info

Publication number: GB2265034A
Application number: GB9226863A
Authority: GB
Inventors: Gyo-Jin Han; Choong-Keun Kwak
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1992-03-13
Filing date: 1992-12-23
Publication date: 1993-09-15
Also published as: KR930020442A; JPH05282866A; GB9226863D0; DE4239121A1

Description

2265034 BIT LINE CONTROL CIRCIAT The present invention relates to

semiconductor memory devices, and more particularly to a bit line control circuit for performing a sensing operation of memory cell data.

In a highly integrated semiconductor memory device, high-speed operation of an integrated circuit is demanded. However, high-speed operation is hindered by the delay of a word line operation for assigning an address of memory cell data and enabling the output thereof, and a bit line operation for reading the memory cell data. In order to obtain high- speed development of the bit line during a read operation of the memory cell data, control circuits are required comprising a bit line precharge circuit for precharging a pair of bit lines to a given level and an equalizing circuit for equalizing the pair of bit lines during precharging of the bit lines. Thus, by the use of such a bit line control circuit, data stored in a given memory cell may be read and written at a high speed.

Referring to Figure 1 of the accompanying diagrammatic drawings, a conventional bit line control circuit is illustrated. Precharge transistors. P 1 and P2 having channels connected between supply voltage Vcc and bit lines BL and BL respectively are controlled by a first equalizing signal OEQ2. An equalizing transistor P5 controlled by the first equalizing signal EQ2 equalizes the voltage level of the bit lines BL and B L. NMOS transistors N1 and N2, each having a control terminal connected to supply voltage Vcc, and PMOS transistors P3 and P4 being controlled by a second equalizing signal 0 EQ 1 accelerate a sensing operation of the bit line by controlling a "low" level of the bit line during a read operation of data in a memory cell 1. The construction of Figure 1 shows one column in a memory array of a static RAM, and although not shown in the figure, there are a plurality of memory cells in both column and row directions of Figure 1.

When the bit line control circuit shown in Figure 1 performs a read operation, the second equalizing signal OEQ1 will have a "low" level of ground voltage Vss as shown in Figure 2. Bit lines BL and BL are precharged and equalized by PMOS transistors P1, P2, and P5 which are controlled by the first equalizing signal OEQ2. Moreover, bit lines BL and BL are prevented from dropping to a specified level by transistors P3, P4, NI and N2. PMOS transistors P3 and P4 are designed to be small in size so as to obtain fast development of the bit lines BL and BL during the read operation.

If a word line WL is enabled during the read operation, bit lines BL and BL will have fast development since NMOS transistors NI and N2 are in off states until the voltage level of bit lines BL and B L is lowered to Vcc Vth (where Vth is a threshold voltage of an NMOS transistor) from supply voltage Wc. In addition, if NMOS transistors NI and N2 are turned on at a voltage level of Wc-Vth-ct (where a is an arbitrary constant), there is no voltage drop of the bit line and the equalizing time can be reduced in the following read operation. However, after the read operation is over, if the level of data being written is "high" when a write operation is enabled, a "low" level between levels of the bit lines BL and BL forms a direct current path through the NMOS transistor NI (or N2) and the bit line BL (or BL) into a write driver (not shown).

1 Further, because the NMOS and PMOS transistors on the bit lines BL and BL are simultaneously built during a manufacturing process for complementary MOS, the integrated circuit occupies a relatively large area which is undesirable for a highly integrated semiconductor memory device.

Preferred embodiments of the present invention aim to provide a bit line control circuit for performing a high-speed operation by improving the development of a bit line during a read operation.

It is another aim to provide a bit line control circuit for suppressing the generation of direct current during a write operation.

It is a further aim to provide a bit line control circuit having a reduced area of an integrated circuit occupied by transistors.

According to one aspect of the present invention, there is provided a bit line control circuit comprising a precharge circuit for precharging a voltage level of a bit line connected to a memory cell of a semiconductor memory device by a first control signal, an equalizing circuit for equalizing a voltage level of said bit line, and a sensing acceleration circuit for accelerating the development of a sensing voltage level of said bit line by a second control signal during a read operation, wherein said precharge circuit, said equalizing circuit and said sensing accelerating circuit comprise the same type of MOS transistor, and a charge sharing operation of said sensing acceleration circuit is disabled by the control of said second control signal during said read operation.

Preferably, said first and second control signals are bit line precharge and equalizing signals respectively and have a complementary logic level.

Preferably, said MOS transistor is a PMOS transistor.

The invention extends to a semiconductor memory device provided with a bit fine control circuit according to any of the preceding aspects of the invention.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 3 and 4 of the accompanying diagrammatic drawings, in which:

Figure 3 is a circuit diagram of one example of a bit line control circuit according to the present invention; and Figure 4 is a timing chart illustrating an example of the read operation of the circuit shown in Figure 3.

In the figures, like reference numerals denote like or corresponding parts.

Although the bit line control circuit in the following embodiment consists of PMOS transistors, NMOS transistors may be analogously used for the same purpose. The same embodiment can be applied by reversing a supply voltage level for each control signal shown in Figure 4.

t In Figure 3, there are provided precharge transistors M1, M2, an equalising transistor M5, and sensing acceleration transistors M3, M4, all of the same MOS type.

In Figure 3, the NMOS transistors N1 and N2 shown in Figure 1 are eliminated. Moreover, the logic operation of first and second control signals OEQ2 and 95EQ l is opposite to each other as shown in Figure 4. That is, during a read operation of memory cell data, the first control signal OEQ2 is asserted, while the second control signal OEQ 1 is negated. Therefore, sensing acceleration transistors M3 and M4 are turned off.

An example of a read operation of the circuit shown in Figure 3 will now be described with reference to Figure 4. Since the circuit of Figure 3 is constructed using the same type of transistors, that is, PMOS transistors, the area occupied by the transistors is accordingly reduced, and as a result, a highly integrated circuit can be more easily designed. In order to obtain the fast development of a bit line, the sensing acceleration transistors M3 and M4 are turned off during a specified pulse period, an interval tl just before a word line WL is enabled, and a charge sharing operation between bit lines BL and BL and data of a memory cell 10 is executed at a high speed.

After the read operation, a "low" level among voltage levels of bit lines BL and BL is maintained above a constant voltage Vcc-a by enabling the operation of the sensing acceleration transistors M3 and M4. Furthermore, it is possible to have a large size transistor in order to obtain the fast development of bit lines BL and BL because the sensing acceleration transistors M3 and M4 are turned off until the data of memory cell 10 is read sufficiently. Hence, the sensing acceleration transistors M3 and M4 serve a purpose similar to that of the NMOS transistors N1 and N2 shown in Figure 1. Further, disadvantages in the conventional bit line control circuit can be eliminated when the word line WL is enabled, the sensing acceleration transistors M3 and M4 are turned off, and each enabled time of the first and second control signal OEQ2 and OEQ1 is adjusted.

According to the bit line control circuit described above, a high-speed operation is obtained when a write operation is enabled after a read operation. Also, during a charge sharing operation between bit lines and memory cell data, the generation of direct current is suppressed. Further, the area occupied by transistors is reduced, producing the desirable result of a highly integrated semiconductor memory device.

While preferred embodiments of the present invention have been shown and described above, it will now be apparent to those sIdIled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except

7- combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any 15 novel combination, of the steps of any method or process so disclosed.

1

Claims

1. A bit line control circuit comprising a precharge circuit for precharging a voltage level of a bit line connected to a memory cell of a semiconductor memory device by a first control signal, an equalizing circuit for equalizing a voltage level of said bit line, and a sensing acceleration circuit for accelerating the development of a sensing voltage level of said bit line by a second control signal during a read operation, wherein said precharge circuit, said equalizing circuit and said sensing accelerating circuit comprise the same type of MOS transistor, and a charge sharing operation of said sensing acceleration circuit is disabled by the control of said second control signal during said read operation.

2. A bit line control circuit as claimed in claim 1. wherein said first and second control signals are bit line precharge and equalizing signals respectively and have a complementary logic level.

3. A bit line control circuit as claimed in claim 1 or 2, wherein said MOS transistor is a PMOS transistor.

4. A bit line control circuit substantially as hereinbefore described with reference to Figure 3 or Figures 3 and 4 of the accompanying drawings.

5. A semiconductor memory device provided with a bit line control circuit 25 according to any of the preceding claims.

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