GB2262405A - Transmitting video signals with reduced horizontal and vertical blanking periods - Google Patents

Abstract

Horizontal and/or vertical blanking intervals can be reduced or completely eliminated from a video signal by arranging for a FIFO buffer 24 to have a faster input clock rate (input PLL 28) than its output clock rate (output PLL 32). This provides a digital video signal for transmission or the like which has a reduced data rate since the lines (and/or frames) of the video data are expanded to fill the periods previously allocated to the blanking intervals. On reception, the blanking intervals can be restored for processing or display of the video signal by an inverse technique, data being written into a buffer at a slower rate than that being read out, the beginning of read out from the buffer being delayed until the required blanking interval has elapsed. A similar technique can be applied to modification and optimisation of inconvenient blanking intervals. <IMAGE>

Description

HORIZONTAL AND VERTICAL BLANKING IN VIDEO SIGNALS This invention relates to horizontal and vertical blanking in video signals such as those produced by video cameras for transmission, recording and/or other processing prior to display.

It is conventional for video signals to be composed of two parts, firstly the active video portion and secondly horizontal and vertical blanking. The active video portion conveys the picture content information, whereas the blanking part contains picture synchronising information for cameras, processors and/or displays. Horizontal synchronising information is provided between lines of video data, and vertical synchronising information is provided between frames of video data.

In any particular video standard, the lengths of the horizontal and vertical blanking intervals have to be chosen taking the following factors into account: (i) the synchronising signals indicating horizontal (H) and vertical (V) blanking must be easily detectable by all equipment; (ii) the H blanking interval must be longer than the minimum required in all types of equipment to be used; and (iii) the V blanking interval must be longer than the minimum required in all types of equipment to be used.

In the process of setting a practical analogue video interface standard for High Definition (HD) equipment, vertical and horizontal blanking periods have been chosen to allow for the scanning and other requirements of current cathode ray tube (CRT) and camera technology.

Vertical blanking is typically 45 lines, this representing the minimum time for transfer of charge from photosites into the masked region of a charge-coupled device (CCD) camera. Horizontal blanking is about 3 pçs which represents the current minimum practical flyback time of a CRT display.

In order to simplify the design of equipment, a digital video interface standard (SMPTE 240M) has been proposed which retains the original blanking intervals specified in the equivalent analogue standard. The result of this is that, for a given number of samples from the active picture area, the transmission rate of those samples between equipment is higher than it need be by a factor equal to the ratio of the frame period to the active picture time. In a digital system, only the net active data together with a small set of code words for synchronisation need be transmitted. However, in the SMPTE 240H standard, considerable redundancy exists in the inefficiency of the digital representation which relates essentially to an analogue signal format.

Another factor is that the blanking periods in the standard have been specified to take account of existing technology. New devices developed in the future may turn out to have different requirements; either shorter blanking intervals which would fit the presently specified standard but involve further signal format redundancy, or longer blanking intervals which would at present be incompatible with the standard.

According to one aspect of the invention there is provided a method of conveying video data, the method comprising transmitting the video data with reduced horizontal and/or vertical blanking intervals and, upon receiving the transmitted video data, inserting predetermined values of horizontal and/or vertical blanking intervals.

According to another aspect of the invention there is provided apparatus for modifying horizontal and/or vertical blanking intervals in video data, the apparatus comprising storage means for the video data operable at different input and output data rates, the difference in the data rates over each line and/or frame period of the video data providing the modification of the horizontal and/or vertical blanking intervals.

Embodiments of the invention provide the ability to remove, insert and/or modify the length of horizontal and/or vertical blanking intervals in video signals, thereby providing a reduction in data rate or an increase in data quantity during transmission, as well as the possibility of tailoring the blanking intervals to meet specific individual requirements so as to improve the degree of possible compatibility of equipment to different standards.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which.

Figure 1 shows a video camera and associated video buffer store according to one embodiment of the invention; Figure 2 shows an implementation of the buffer store of Figure 1; Figure 3 is a diagram of input and output data formats of the buffer store of Figure 2; Figure 4 is a diagram of the manner in which horizontal blanking is introduced according to an aspect of the invention; Figure 5 is a circuit diagram of another embodiment of the invention, for introduction of horizontal blanking as shown in Figure 4; Figure 6 is a circuit diagram of a further embodiment of the invention, for introduction of vertical blanking; Figure 7 is a circuit diagram of an implementation suitable for introducing both horizontal and vertical blanking; and Figure 8 is a circuit diagram of a still further embodiment of the invention, which modifies existing analogue horizontal and vertical blanking in a video signal to different values.

Referring to Figure 1, there is shown a video camera 10 which may, for example, be a charge-coupled device (CCD) camera, receiving light 12 through a lens system 14. Analogue sync signals are supplied to the video camera 10 at an input 16 and analogue video signals are consequently produced by the video camera 10 at an output 18. The analogue video output signals conform to normal interface standards, including the required vertical and horizontal blanking intervals. The analogue video output signals are supplied to a digital video buffer store 20 which digitises the video signals before buffering the signals for data rate and timing conversion. The digital video buffer store 20 also receives the analogue sync signals. If the video camera 10 is capable of providing a digital output, the buffer store 20 does not require a digitising means, but can receive the digital signals directly.The output of the buffer store 20 is a reduced data rate digital output video signal, as will be described below.

Figure 2 shows one implementation of the digital video buffer store 20 in greater detail. The analogue video signals from the video camera 10 (Figure 1) are supplied to an analogue-to-digital (A-D) converter 22. Digital data from the A-D converter 22 is supplied to a data input of a first-in-first-out (FIFO) buffer 24.

The analogue sync signals are supplied to a sync separator 26 which operates to separate out the horizontal (H) sync signals and the vertical (V) sync signals. The H sync signals are supplied to an input phase-locked-loop (PLL) 28 from which a clock signal is derived for the A-D converter 22 and the FIFO 24. The H and V sync signals are gated together in a gate 30 thereby providing a mixed blanking signal which is supplied to an inverted write enable WE of the FIFO buffer 24.

The H sync signals are also supplied to an output PLL 32 which provides an output clock signal for the FIFO buffer 24. The video data signal is read out of the FIFO buffer 24 and supplied to an output 34 of the buffer store 20 in response to the output clock signal from the output PLL 32.

The buffer store 20 shown in Figure 2 operates as follows. The analogue video signal from the video camera 10 is digitised by the A-D converter 22 at a sample rate sent by the H sync signal and is then written into the FIFO buffer 24. (If a digital output can be provided by the video camera 10, the A-D converter 22 is not necessary.) Only the active samples of the analogue video signal are stored in the FIFO buffer 24, since the inverted write enable input WE prevents writing in during the H and V blanking periods. The relationship between the clock signal rates set by the input PLL 28 and the output PLL 32 are set so that the contents of the FIFO buffer 24 are read out at a continuous rate which allows the active video samples plus a very small number of digital synchronising codes to fill the frame period exactly.

It will be seen that the storage size of the FIFO buffer 24 is set by the ratio of active picture-to-frame period. For example, in the case of the SMPTE 240M digital video standard: Number of active pixels/s = 1920 x 1035 x 30 = 59,616,000 Resulting transmit clock = 16.77 ns SMPTE 240M clock period = 13.468 ns Horizontal blanking = 180 samples = 2.42 Jus Vertical blanking = 45 lines + 180 samples = 99000 + 180 samples = 99180 = 1335.756 ps Number of transmit cycles in Vertical blanking = 79,652 samples In the above calculation of transmit clock rate, digital sync codes have not been included. It should be noted that luminance and chrominance are processed in parallel in the SMPTE 240M standard and so no further time allowance needs to be made.

Modification of this standard to 1080 active lines (in order to obtain "square" pixels) would in practice reduce the FIFO storage requirement from 79,652 samples to 42,546 samples.

In order to arrive at a practical (analogue) interface standard for High Definition (HD) video equipment, vertical and horizontal blanking periods will be chosen to allow for the scanning requirements of current cathode ray tube (CRT) technology. In this case, vertical blanking is typically 45 lines whilst horizontal blanking is about 3 )1S. These values could be changed as necessary to allow for developed technology.

Figure 3 shows the manner in which the input digital data to the FIFO buffer 24 is effectively expanded on a line-by-line basis so as to produce the reduced data rate digital output. In effect, the video data samples can be time expanded per line so as to fit into most of each blanking period. This is achieved by using a slower output clock (from the output PLL 32) at the FIFO buffer 24 than the input clock (from the input PLL 28). Thus it is possible to achieve the significant advantage of reducing the data transmission rate (and/or increasing the number of active pixels per second) by making use of the blanking intervals which would otherwise represent redundant transmission capacity. As shown in Figure 3, it is possible to provide a continuous data stream, including the necessary synchronisation and other codes.

Once the time-expanded digital video signals (lacking appropriate blanking intervals) have been received for subsequent display or other processing, it is necessary to convert the signals into a suitable form. This will now be discussed.

Figure 4 illustrates graphically the manner in which an active video period, which may be a time-expanded video signal as discussed above, is then correspondingly time-compressed in order to introduce a sufficiently long horizontal blanking interval. The effect on the active video is that the instantaneous sampling rate, together with the bandwidth of the signal, are increased by a factor of 1/(degree of compression). In the form as received (in other words, without blanking intervals) each line of samples commences with a "start new line" code SNL. The samples for that line are then stored, as will be explained below, and no samples are read out until the duration of the required horizontal blanking period has elapsed.At that time, the first sample of the line is read out of store but at an increased sampling rate, so that the final samples of each line will coincide (in effect, although there may be some residual small delay). Vertical blanking is achieved in a similar manner, but with the vertical blanking intervals introduced between frames. Thus, the digital signal has been put into a form suitable for display or other processing. The inserted horizontal blanking interval will be chosen to be suitable for the particular requirement, for example, the analogue requirements of an HD CRT display typically impose a minimum 3 ps line flyback time.

An interface circuit can be included, typically in the CRT display circuit, which will allow these requirements to be met, even when the video input signal is a totally efficient digital representation of the active video, for example, as shown in the top diagram of Figure 4.

Figure 5 shows an interface circuit suitable for producing the time-compressed video as shown in Figure 4, in other words a video data format with H blanking insertion. Digital data, such as that produced by the buffer store 20 of Figure 2, is supplied to a FIFO buffer 40, together with an input clock signal. The digital data and the input clock signal are also supplied to an H sync detection circuit 42 which supplies detected timings at which the H sync interval is to commence (as well as the input clock signal, if required) to an output clock processor 44. The output clock processor 44 generates a read enable RE signal for the FIFO buffer 40. The outputs from the H sync detection circuit 42 are also supplied to a H sync waveform insertion circuit 46, the output from which is combined in a combiner circuit 48 with the output from the FIFO buffer 40.The combined digital output is then converted into analogue form and supplied to the CRT display circuit (not shown). This analogue output will consist of the time-compressed active video lines with blanking and sync added by the H sync waveform insertion circuit 46, according to the scheme shown in the lower diagram of Figure 4.

The interface circuit of Figure 5 operates in a substantially inverse manner to that of the buffer store of Figure 2, in that the digital data is written into the FIFO buffer 40 at the input clock rate, a delay equivalent to the horizontal blanking interval is introduced by the output clock processor 44 after H sync detection, and the data is read out of the FIFO buffer 40 at a faster clock rate set by the output clock processor 44, after the delay equivalent to the horizontal blanking interval. A waveform suitable for the H sync is generated by the insertion circuit 46 and is combined with the data from the FIFO buffer 40 during the delay period equivalent to the horizontal blanking interval.

It is to be noted that the capacity of the FIFO buffer 40 only has to equal the number of input video data samples corresponding to the length of time of horizontal blanking in the output. This is because the output clock rate of the FIFO buffer 40 is faster than the input clock rate, and so once read-out starts to occur after the delay introduced for the H blanking interval, the FIFO buffer 40 will gradually be emptied during each line period. For example, if there are 1920 active samples in a line plus a six word sync code, with a line repetition rate of 32.2 us, then the FIFO buffer 40 would need to be capable of storing only 180 samples in order to provide a three ps H blanking interval.

An alternative implementation of the Figure 5 circuit involves a digital-to-analogue conversion of the FIFO buffer 40 output, with an analogue H sync waveform being generated by the insertion circuit, the resulting two analogue signals being combined to produce the output analogue video signal.

A similar technique can be used for inserting vertical blanking, and this is shown in Figure 6. The circuit shown in Figure 6 has a similar general configuration to that shown in Figure 5. The digital data and input clock signal are applied to an N-line FIFO buffer 50 and to a V sync detection circuit 52 which supplies detected timings at which the V sync interval is to commence (as well as the input clock signal, if required) to an output clock processor 54. The output clock processor 54 generates a read enable RE signal for the N-line FIFO buffer 50. A V sync waveform insertion circuit 56 also receives the outputs from the V sync detection circuit 52 in response to which a V sync waveform is generated and combined in a combiner circuit 58 with the output from the FIFO buffer 50.The combined digital signal is then converted into analogue form and supplied to the CRT display circuit (not shown) or the like. This analogue output will consist of time-compressed active video frames with V blanking and sync added by the insertion circuit 56. As with the Figure 5 arrangement, the V blanking insertion circuit of Figure 6 can alternatively involve direct digital-to-analogue conversion of the FIFO buffer 50 output, with an analogue V sync waveform being generated by the insertion circuit, and the resulting two analogue signals being combined to produce the output analogue signal.

In the V blanking insertion circuit of Figure 6, if for example an HD CRT video display requires 600 Ats for field retrace, and a line period on the input to the system is 32.2 gs, then only 600/32.2 ';19 lines (namely N = 19) would require buffering in the FIFO buffer 50.

This again is because the output clock rate of the FIFO buffer 50 is faster than the input clock rate, and so once read-out starts to occur after the delay introduced for the V blanking interval, the FIFO buffer 50 will gradually be emptied during each frame period.

Figure 7 shows a circuit for inserting both H and V blanking of required durations. The circuit is basically a combination of the functions of the separate H and V blanking insertion circuits of Figures 5 and 6. In Figure 7, the digital data and input clock signal are applied to an N-line FIFO buffer 60 and to an H and V sync detection circuit 62 (capable of both H and V sync detection) which supplies detected timings at which both H and V sync intervals are to commence (as well as the input clock signal, if required) to an output clock processor 64. The output clock processor 64 generates a read enable RE signal for the N-line FIFO buffer 60.An H and V sync waveform insertion circuit 66 also receives the outputs from the H and V sync detection circuit 62 in response to which either an H or V sync waveform is generated as required, and is then combined in a combiner circuit 68 with the output from the FIFO buffer 60. The combined digital signal is then converted into analogue form. Alternatively, analogue conversion can be performed directly on the FIFO buffer 60 output, and the waveform insertion circuit arranged to produce an analogue output.

The circuit of Figure 7 operates in a similar manner to both Figure 5 and Figure 6 circuits. It will be appreciated that the output clock processor 64 must be able to provide delays equivalent to both the required horizontal and vertical blanking intervals. The circuit of Figure 7 can effectively restore (the same values of) the horizontal and vertical blanking intervals which were removed by the circuit of Figure 2.

The implementations thus far described have been in the context of video data transmission systems in which a conventional video format including blanking periods is expanded prior to transmission to "fillin" the blanking periods, these being subsequently reconstituted upon reception by data compression and blanking insertion. This is a highly advantageous mode of implementation of the invention, but it should be noted that many others are possible. For example, a video camera other than a conventional video camera need not be designed to include blanking periods in the output video signal, in which case removal of such blanking periods prior to transmission would not be necessary.As a general feature, implementations of the invention on the reception side can be viewed as being suitable for introduction of required H and/or V blanking intervals into any digital video representation.

However, the invention can also be used in two further areas, as will now be described.

One of these further areas concerns the modification of inconvenient analogue H and V blanking. Requirements can be considerably relaxed in standards in which the H and/or V blanking intervals are considered inconveniently short. One example of this involves the modification of the SMPTE-240M standard to provide "square" pixels in which: Total no. of lines = 1125 No. of active lines = 1080 No. of fields/sec = 60 H blanking = 3.77 V blanking - 22 2 lines/field 2 A minimum of 45 lines/field is presently considered the limit for current CCD HD camera technology; therefore a further 222 lines of V 2 blanking can be added.

A similar situation applies to H blanking in a proposed progressive scan version of the SMPTE-240M standard in which: Total no. of lines = 1125 No. of active lines = 1080 No. of frames/sec = 60 H blanking = 1.885 4s In this scheme, the H blanking can be expanded from 1.885 ys to around 3 pays.

Figure 8 shows a circuit suitable for such modification of inconvenient analogue H and V blanking intervals to optimum values. An analogue video signal in a first format is supplied to an A-D converter 70 and to a sync separation and clock generator circuit 72. An extracted input clock signal from the circuit 72 is used for digitisation in the A-D converter 70. An output clock signal as well as H and V timing signals are supplied to an H and V output sync generator 74. The digitised signal from the A-D converter 70 is supplied to a FIFO buffer 76 clocked by the output clock signal from the circuit 72, the FIFO buffer 76 providing H and V blanking adjustment.The outputs of the FIFO buffer 76 and the H and V output sync generator 74 are combined in a combiner circuit 78 and finally converted back into analogue form but with modified H and V blanking and sync intervals. H and V drive signals can also be provided from the H and V output sync generator 74 for use in subsequent processing circuitry.

The circuit of Figure 8 operates in a broadly similar manner to those described previously except that, instead of either removing existing blanking intervals from a video signal or inserting blanking intervals in a video signal lacking such intervals, the circuit modifies the length of existing blanking intervals to preferred values, for example by introducing a delay equivalent to a required blanking interval extension to read-out of video data from the FIFO buffer 76.

The other of the further areas of implementation involves changing the sampling frequency in digital representations of analogue video systems, or modifying inconvenient parameters in such digital representations. The choice of sampling frequency. for a digital representation of an analogue standard will often be open to discussion. The exact value will usually be chosen to result in an integer number of samples per line, but the exact number of samples per line is determined by the active line length plus the blanking time.

Amongst the proposals put forward for an international HD standard, two have found favour: 81 MHz and 74.25 MHz.

With 1920 active samples/line, these result in the following parameters for an 1125/60/2:1 system: 81 MHz 74.25 MHz Line period: 29.63 ALS 29.63 Fs Active line time: 23.7 s 25.86 s Blanking period: 5.926 s 3.77 As Ratio H blanking to active line: 20% 12.7% The 74.25 MHz system has the following characteristics compared to the 81 MHz system:- the 74.25 MHz system has a lower sampling frequency and is therefore easier to handle in transmission and processing; the 74.25 MHz system has a lower bandwidth of the analogue representation; and the 74.25 KHz system makes more efficient use of the H blanking.

However, the 81 MHz system is favoured by those considering progressive scan in which an optimum system having a sampling frequency of 162 MHz would yield an H blanking interval of 2.963 tl s. (H blanking would not be practical in a system using double the 74.25 MHz sampling frequency.) This inconvenient restriction of a simple 2:1 ratio between sampling frequencies for progressive and interlaced systems can be removed by a variation of the circuit shown in Figure 7 which acts to "stretch" the blanking period. Thus considerable flexibility of design is provided by the ability to insert, remove or modify blanking intervals in video signals.

Claims (12)

1. A method of conveying video data, the method comprising transmitting the video data with reduced horizontal and/or vertical blanking intervals and, upon receiving the transmitted video data, inserting predetermined values of horizontal and/or vertical blanking intervals.

2. A method according to claim 1, wherein the video data is expanded for transmission, and compressed upon reception in order to enable insertion of the horizontal and/or vertical blanking intervals.

3. A method according to claim 1 or claim 2, wherein the video data to be transmitted includes predetermined values of horizontal and/or vertical blanking intervals and, prior to transmission, the horizontal and/or vertical blanking intervals are reduced from the predetermined values.

4. A method according to claim 3, wherein the predetermined values of the horizontal and/or vertical blanking intervals in the video data prior to transmission and inserted upon reception are the same.

5. A method according to any one of the preceding claims, wherein the horizontal and/or vertical blanking intervals are reduced to the extent that the video data is in the form of a continuous data stream.

6. Apparatus for modifying horizontal and/or vertical blanking intervals in video data, the apparatus comprising storage means for the video data operable at different input and output data rates, the difference in the data rates over each line and/or frame period of the video data providing the modification of the horizontal and/or vertical blanking intervals.

7. Apparatus according to claim 6, wherein the horizontal and/or vertical blanking intervals in the video data include horizontal and/or vertical synchronisation signals, the apparatus comprising means for extracting the synchronisation signals from the video data prior to storing the video data in the storage means, and means for restoring the synchronisation signals to the modified video data read out of the storage means at the output data rate.

8. Apparatus according to claim 6 or claim 7, wherein horizontal and/or vertical blanking intervals are to be inserted in the video data, the apparatus comprising delay means for setting a delay time corresponding to a required blanking interval, read out from the storage means being inhibited until the delay time has elapsed.

9. Apparatus according to claim 7, wherein the apparatus is operable to receive video data in a format having predetermined values of horizontal and/or vertical blanking intervals, and read out of video data from the storage means is arranged to provide a continuous stream of data including the horizontal and/or vertical synchronisation signals

10. Apparatus according to any one of claims 6 to 9, wherein the storage means comprises a first-in-first-out buffer.

11. A method of conveying video data, the method being substantially as herein described with reference to Figures 1, 1 and 2, 3, 4, 5, 6, 7 or 8 of the accompanying drawings.

12. Apparatus for modifying horizontal and/or vertical blanking intervals in video data, the apparatus being substantially as herein described with reference to Figures 1, 1 and 2, 5, 6, 7 or 8 of the accompanying drawings.