GB2259794A

GB2259794A - Virtual mode computer system having interrupt related instructions

Info

Publication number: GB2259794A
Application number: GB9217612A
Authority: GB
Inventors: Donald B Alpert; Albert Teng
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1991-09-23
Filing date: 1992-08-19
Publication date: 1993-03-24
Also published as: GB9217612D0; DE4231552A1; CN1071269A; JPH05216690A; ITMI922140A1; ITMI922140A0; IT1255601B; KR930006555A

Abstract

A computer system including a given microprocessor is specifically designed to operate in a virtual operating mode (or protected mode) that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI) instructions, from the previously written program by means of emulation software forming part of the host program. The CLI and STI instructions are handled in a way which expedites their execution without appreciably sacrificing compatibility between the given microprocessor and earlier microprocessors. Use is made of a virtual interrupt flag (VIF) bit and a virtual interrupt pending (VIP) bit in a register 30''. If the VIP bit is in its 'non-pending' state, the state of the VIF bit can be changed without using the emulation software. If the VIP bit is in its 'pending' state, then the STI instruction can be executed and an awaiting interrupt serviced by using the emulation software without first changing the VIF bit from its CLI state to its STI state. <IMAGE>

Description

A COMPUTER SYSTEM HAVING INTERRUPT RELATED INSTRUCTIONS OPERATING IN A

VIRTUAL MODE

FIELD QF THE INVENTION

The present invention relates generally to a computer system including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single programmed microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The present invention relates more particularly to an improvement in the way in which the given microprocessor and its host operating software program handle certain sensitive interrupt related instructions, specifically CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI), from the previously written program by means of emulation software forming part of the host program in order to emulate the way in which those instructions would have been executed by the earlier microprocessor.

BACKGROUND OF THE INVENTION

In the discussion immediately above, reference was made to a given microprocessor, to a previously written software program, to an earlier designed single program microprocessor, and to a particularly designed host operating software program. In the actual practice of the present invention, the given microprocessor specifically refers to an improvement to Intel Corporation's 80386 and 80486T.M microprocessor, hereinafter merely referred to as the 386 microprocessor since the invention is equally applicable to both. The earlier designed single programmed microprocessor refers to Intel Corporation's earlier designed single program 8086 microprocessor, The previously written software program refers to any of a number of different programs including specifically DOS programs that were previously written for the 8086 microprocessor. Finally, the host operating software program refers to any suitable host or central control -2operating system such as WINDOWS7m software by Microsoft or UNIX-1m system software by AT&T, both written specifically for the given microprocessor so that the latter can operate in the virtual operating mode described above. While the present invention will be described hereinafter in relation to the Intel 386 (and 486Tm) and 8086 microprocessors, the previously written DOS programs, and a WINDOWS or UNIX operating system, it is to be understood that the present invention is not limited to those particular microprocessors, to those previously written software programs, or to those particular central operating systems. With that understanding in mind, a brief history of the 8086 and the 386 microprocessors will immediately follow. A more detailed discussion of those microprocessors as they relate specifically to the present invention will be provided in the DETAILED DESCRIPTION. It can be stated, without reservation, that Intel Corporation's earlier

8086 microprocessor was so highly successful that there were many software programs written for it. However, given that this microprocessor was to be the first of a series of subsequently improved microprocessors, it did have its limitations. One in particular, although it was not necessarily considered a limitation at the time, was the inability of the microprocessor to act on more than one software program at a time. This, of course, meant that the program itself did not have to execute in a protected, paged, multitasking environment. However, as the technology evolved, Intel Corporation eventually developed its 386 microprocessor which, as stated previously, is capable of running a number of programs using a more sophisticated central operating system such as WINDOWS or UNIX. At the same time, the 386 microprocessor was designed to operate in a virtual 8086 operating mode that allowed multiple software programs previously written for the earlier 8086 microprocessor to be used and specifically to execute in a. protected, paged, multi-tasking environment under the more sophisticated central operating system, even though those earlier software programs were not intended to execute in that manner. There were just too many earlier -3programs to allow them to become obsolete. Therefore, whenever changes are made to successors of the 8086 microprocessor compatibility with earlier 8086 software is always a consideration.

While compatibility between Intel's present microprocessors and the earlier wfitten software is, indeed, important, there are instances in which this objective compromises certain other operational aspects of the overall computer system. Such has been the case in the execution of certain sensitive interrupt related instructions, specifically CLI and STI. As will be discussed in more detail hereinafter, the present 386 microprocessor is designed to execute all CLI and STI instructions in virtual mode so as to emulate the way in which these instructions would have been executed on the 8086 microprocessor. While the number of executions of these particular instructions is a relatively small percentage of the total instructions executed in the virtual mode, they account for a relatively large amount of execution time. One particular solution to this problem has been proposed, as will also be discussed in more detail hereinafter. However, while this proposal does, indeed, substantially reduce the time required to execute CLIs and STis in the virlual mode, it does so by compromising compatibility between the microprocessor and its software.

SUMMARY OF THE INVENTION

In view of the foregoing, it is a primary object of the present invention to maintain the reduced execution time for CLis and STis as proposed previously, while at the same time providing an improved compatibility 5 related feature.

As will be seen hereinafter, a computer system is disclosed herein including a given microprocessor, for example the 386 microprocessor, which is specifically designed to operate in a virtual operating mode that allows a software program, for example a DOS program previously written for an earlier designed single program microprocessor, for example the 8086 microprocessor, to execute in a protected, paged, multi-tasking environmeni under a particularly designed host operating software program, for example WINDOWS or UNIX. The system also includes means for executing certain sensitive interrupt related instructions, specifically CLI and STI, initiated by the previously written program using emulation software forming part of the host program in order to emulate the way in which the instructions would have been executed by the earlier microprocessor.

In order to reduce the time it takes for the emulation software to execute the CLI and STI instructions during the virtual operating mode of the computer system, the given microprocessor is provided with an EFLAGS register including (1) a VIRTUAL INTERRUPT FLAG (VIF) bit which operates between a STI state for enabling the execution of interrupt instructions initiated by the previously whiten program and a CLI state for disabling the execution of the interrupt instructions, and (2) a VIRTUAL INTERRUPT PENDING (VIP) bit that operates between a PENDING state during which interrupt requests are awaiting execution and a NONPENDING state in which no such interrupt requests are awaiting execution. To that same end, that is to reduce execution time in the virtual mode, means are provided for changing the state of the VIF bit of the EFLAGS register without use of the emulation software, so long as the VIP bit is in its NONPENDING state. In that way, the CLI and STI execution time in the virtual mode is reduced 1 1 -5substantially. However, at the same time, means are provided in response to the PENDING state of the VIP bit, the CLI state of the VIF, and a STI instruction subsequently initiated by the previously written software program for automatically executing the subsequently initia-ed STI instruction and an awaiting interrupt request by means of the emulation software without first changing thd state of the VIF bit from a CLI state to a STI state. This, as will be discussed in more detail hereinafter, enhances compatibility between the microprocessor and its associated software.

-6BRIEF DESCRIP11ON OF THE DR AWINGS The present invention will be described in more detail hereinafter in conjunction with the drawings, wherein:

FIGURE 1 diagrammatically illustrates certain aspects of a prior art computer system including the earlier 8086 microprocessor; FIGURE 2 is a similar view of a computer system including the earlier 386 microprocessor, specifically illustrating its virtual mode in relation to STI and CLI interrupt instructions; FIGURE 3 is yet a similar view of a computer system including the 386 microprocessor which incorporates the previously proposed modification to allow it to execute interrupt instructions in the virtual mode more rapidly than was possible by the system illustrated in Figure 2; FIG6RE 4 is a diagrammatic illustration of a computer system designed in accordance with the present invention to include not only the advantages of the system illustrated in Figure 3, but also certain advantages relating to compatibility between the microprocessor and software executing within the computer system; and FIGURE 5 is a flow diagram depicting the way in which the computer system illustrated in Figure 4 execute CLI and STI instructions in accordance with the present invention.

1 DETAILED DESCRIPTION

Turning now to the drawings, attention is first directed to Figure 1 which, as indicated previously, is a diagrammatic illustration of certain aspects of a prior art computer system including the earlier 8086 microprocessor. The overall computer system is generally indicated by the reference numeral 10. While this particular system includes a number of components not illustrated, it is specifically shown including an 8086 microprocessor 12 having an EFLAGS register 14 containing an interrupt flag IF, a single DOS software program 16 and a number of 1/0 peripherals 18, 20 and 22. For purposes of discussion, it will be assumed that the peripheral 18 is a monitor, the peripheral 20 is a disk drive and, the peripheral 22 is a keyboard, although the present invention is not limited to these particular 110 devices, as should become apparent.

Having described computer system 10 thus far, attention is now directed to the way in which the system and particularly the 8086 microprocessor 12 handles interrupt commands from its 1/0 peripherals. Generally speaking, the 8086 microprocessor is designed to be interrupted while executing certain instructions and is designed not to be interrupted while executing other instructions. For example, during those periods that the microprocessor is being asked by the DOS software to access disk drive 20, the microprocessor would not want to be interrupted as a result of, for example, a key stroke from keyboard 22. Thus, during the disk drive access period, the interrupt flag bit IF of the FLAGS register 14 would be placed in a CU slate for disabling or preventing the presence of an external interrupt demand from interrupting the microprocessor while it is accessing the disk drive. For purposes of convenience it will be assumed that, the CLI state of the interrupt flag bit IF is represented by a zero in Figure 1. So long as the IF bit remains zero, no interrupts will be accepted by the microprocessor. Once access to the disk drive is completed and assuming that the microprocessor is not immediately thereafter asked to execute other uninterruptable instructions, the state of the interrupt flag IF will be switched from the CLI -R state to the STI state which in Figure 1 is represented by a 1. So long as the interrupt flag is in its STI state, the 8086 microprocessor will accept interrupts. These interrupts would include, for example, the keystroke previously initiated while the IF bit was in its CLI state and is now in its STI state, as well as those interrupts initiated after switching the IF flag to its STI state from its CLI state. In either case, it is important to note that DOS software program 16 communicates directly with the interrupt flag bit of the EFLAG register forming part of the 8086 microprocessor during this process of switching between CLI and STI states. There is no reason for it not to since the DOS program 16 is the only one being run by computer system 10.

Turning now to Figure 2, attention is directed to a more advanced computer system which is generally indicated by the reference numeral 24.

Among other differences between this system and the system 10, system 24 includes the 386 microprocessor indicated at 26 and is capable of operating simultaneously on more than one software program including programs previously written for the 8086 microprocessor, although only one such program for example, the DOS program 16, is shown. As a result of this ability to operate on multiple software programs simultaneously, computer system 24 must be designed so that none of these programs can directly access and thereby change the state of the interrupt flag of the 386 microprocessor's EFLAGS register which is generally indicated at 30 including its interrupt flag IF. As a result of this and the desire to use 8086 software, the 386 microprocessor was designed to operate in a particular virlual operating mode, as stated previously, that is, in an operating mode that allows 8086 programs, for example, DOS program 16, to execute in a protected, paged, muffi-tasking environment under a host operating system.

As also stated previously, one such host or central operating system is the previously recited WINDOWS or UNIX program which is diagrammatically depicted at 32 in Figure 2. This program must be written to include 8086 emulation software, hereinafter sometimes referred to merely as an emulator, for executing certain sensitive interrupt related instructions, -gspecifically CLI and STI, from the previously wfitten program by means of the emulation software in order to emulate the way in which the instructions would have been executed by the earlier 8086 microprocessor.

Still referdng to Figure 2, for purposes of convenience, computer system 24 is shown including the same 1/0 peripherals 18, 20, and 22. In addition, the EFLAGS register 30 forming part of the 386 microprocessor 26 is shown including a virtual mode bit VM. When this bit is provided in its virtual mode state, for example, the 1 state, the system is set to operate in its virtual mode described briefly above. Switching the VM bit to a zero causes the system to operate in its standard or nonvirtual mode.

With computer system 24 described thus far, attention is now directed to the way in which this system handles interrupts in its virtual operating mode. In this regard, it will be assumed that computer system 24 is operating simultaneously on a number of software programs previously written for the 8086 microprocessor including specifically DOS program 16.

For purposes of discussion, it will also be initially assumed that DOS program 16 has just instructed the microprocessor to access the disk drive 20. Under these circumstances, the program initiates a CLI instruction to assure that the interrupt flag IF of the EFLAGS register 30 is in its clear interrupt, zero state while the disk drive is being accessed. However, as indicated previously, because microprocessor 26 may be handling a number of software programs and therefore is operating in a protected mode, DOS program 16 is not allowed to directly the access the EFLAGS register 30. Moreover, since program 16 was actually writlen for the 8086 microprocessor, this particular CLI instruction, as well as many other instruction initiated by this program, must be trapped to and executed through the emulation software forming part of the host operating system 32 for emulating the way in which those instructions would have been executed by the 8086 microprocessor. Immediately after disk ddve 20 and assuming there are no other reasons to inhibit interrupts, the STI instruction is initiated so as to enable interrupts to be handled by microprocessor 26. Like the CLI -10instructions, this and all other STI instructions which cause the IF interrupt flag of EFLAGS register 30 to switch from a zero to a one state must be trapped to and executed through the same emulation software.

From the discussion above, it should be apparent that the interrupt flag of register 30 is required to switch back and forth between its CLI and STI states even if an interrupt is not present or pending. Indeed, upon examination of a typical operating computer system 24, the interrupt flag IF of register 30 switches between its CL] and STI states far more frequently than actual interrupt requests are made of microprocessor 26. Moreover, since each of the CLI and STI instructions required to switch the IF flag must be trapped in and executed through the emulation software, the time spent in carrying out these instructions is quite high. In fact, in some cases it has been found that while these CLI and STI instructions amount to approximately one half of one percent of the total instructions emulated by the host operating system 32 during a given period, the time required to execute the CLI and STI instructions account for as much as 30 percent of the total execution time including time spent within the emulator.

As indicated above, Figure 3 diagrammatically illustrates a computer system including a 386 microprocessor which itself is shown including a previously roposed modification to allow it to execute interrupt instructions in the virtual mode more rapidly than computer system 24 shown in Figure 2. The overall computer system in Figure 3 is depicted by the reference in numeral 34 and the modified microprocessor which is referred to as a 386, microprocessor is indicated by the reference numeral 26'. This latter microprocessor is shown including a modified EFLAGS register 30' and a modified host operating system 321o be discussed hereinafter. Overall, system 34 is shown also including the same DOS software program 16 and the 110 peripherals 18, 20 and 22. With the exceptions to be described, computer system 34 may operate in the same manner as system 24.

As illustrated in Figure 3, EFLAGS register 39' not only includes an interrupt flag bit IF (not shown) and a virtual operating mode bit VM which is illustrated, but also two additional bits that do not form part of the flags register 30 of computer system 24. One of these two additional bits is a VIRTUAL INTERRUPT FLAG bit VIF and the other is VIRTUAL INTERRUPT PENDING bit VIP. The VIF bit is maintained in a CL[ state depicted by, for example, a zero, or in a STI depicted by a one, and corresponds in function to the interrupt flag bit IF. That is, when interrupts to the microprocessor are to be cleared (inhibited), the VIF bit is maintained in its CLI state and when interrupts are allowed, it is maintained in its STI state. At the same time, the VIP bit switches between its PENDING state during which interrupt requests are awaiting execution, as indicated for example by a one, and the NONPENDING state in which no such instructions are awaiting execution, as indicated, for example, by a zero.

With the modified EFLAGS register 30' in mind, the 386' microprocessor 26' and its associated host operating system 32, are designed so that overall computer system 34 operates in the following manner. First assume that the system is operating in its virlual mode (VM set at one) and that there are no interrupt instructions being executed or awaiting execution so that the VIP bit is set at zero during a given period of time. Assume further that during the same given period of lime, the DOS program 16 initiates successive STI and CLI instructions, as illustrated in Figure 3. Under these circumstances, each time the DOS program 16 initiates either a ST1 or CLI instruction it communicates with the EFLAGS register 30 to change its VIF bit from the STI state one to the CLI state zero, back to the STI state 1, and so on without trapping these STI and CLI instructions in and executing them through the host operating system's emulation ioftware. In other words, the host operating system's emulator ignores changes in the state of the VIF bit in the EFLAGS register, so long as the VIP bit is in its NONPENDING zero state. This is to be contrasted with system 24 in which each STI and CLI instruction is trapped within the emulator, that is executed through the emulation software of the host operating system. Thus, it should be apparent that system 34 substantially -12reduces the execution time within the emulator forming part of the host operating system 32'.

The discussion immediately above assumed that there was no interrupt instruction awaiting execution, that is, that the VIP bit was continuously in its NONPENDING state as STI and CLI instructions were successively initiated. Assume now that the VIF bit is in its STI (1) state and that an interrupt instruction is actually initiated by software program 16. Under these circumstances, the modified computer system operates in the following manner. The software program first communicates with the EFLAGS register 30 through the host operating system to change the VIP bit from a NONPENDING (0) state to a PENDING (1) state. As a result, the VIF bit is in its one state and the VIP bit is in its 1 state, as indicated in Figure 3. Once this Was occurred, the system is designed to handle the interrupt through the emulator 32' in the same manner as system 24. Once the interrupt has been handled and assuming that the VIF bit remains in its ST1 stale, the VIP bit is returned to its NONPENDING state.

Still referring to the way in which computer system 34 operates, assume now that the VIF bit in the EFLAGS register 30' is in its CLI (0) state and that the VIP bit is in its PENDING (1) state. With the VIF bit and the VIP bit in these states, assume now that the software program issues a STI instruction in order to enable the microprocessor to accept interrupts. In this case, according to the previously proposed computer system 34, the host operating system recognizes this instruction and immediately switches the VIF bit from its CLI (0) to its STI (1) state. As a result, both the VIF bit and the VIP bit are now set at one and the awaiting interrupt request is executed by trapping to the emulator. It is important to note specifically that execution of the awaiting interrupt request does not occur until the VIF bit has been changed from its CLI state to its STI state. This is to be distinguished from computer system 24. In the latter system, if the interrupt flag bit IF is initially in its M (0) state and an interrupt is pending, the subsequent STI instruction initiated from the software program 28 is immediately trapped in the 1 -13 emulator and the awaiting interrupt request is executed by the emulator along with the STI instruction without first changing the interrupt flag in register 30. Only after execution of these instructions by the emulation software does the latter reset the interrupt flag to its STI (1), assuming no other CU instructions have been initiated. This comparison between system 24 and system 34 is made to point out that the latter system's technique of first changing its VIF bit from zero to one before trapping and executing an awaiting interrupt instruction in the emulator is contrary to and therefore incompatible with the way in which the emulation software in system 24 handles the same situation which is to trap and emulate first. As will be seen hereinafter, the present invention eliminates this incompatible situation while, at the same time, maintaining the advantages of system 34 over system 24.

Turning now to Figure 4, attention is directed to a furiher computer system 36 and specifically one which is designed in accordance with the present invention. Like system 34, system 36 includes what may be characterized as a modified 386 microprocessor 26', depicted in Figure 4 as a 386 microprocessor. This microprocessor is specifically designed to operate in a virtual operating mode that allows multiple previously written 8086 software programs including, for example, DOS program 16 to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program 32 having its own 8086 emulation software in the same manner as system 34. System 36 is also shown including corresponding peripherals 18, 20 and 22 and a corresponding EFLAGS register W forming part of the microprocessor W.

In many ways, computer system 36 handles interrupt requests in the same manner as system 34. Specifically, so long as the VIP bit of register W is in its NONPENDING (0) state which means that no interrupt instructions are pending, the VIF bit is allowed to switch between its STI (1) and its CLI (0) states without going through the emulator of host operating system 32". However, assume now that the VIF bit in register 3W' is initially -14in its CLI (0) state and thpt the VIP bit is initially in its pending (1) state. Assume further that software program 28 thereafter initiates a STI instruction. Under these circumstances, microprocessor 2W and host operating system 32" are designed to respond to the PENDING state of the VIP bit, the CLI state of the. VIF bit and to the subsequently initiated STI instruction for automatically executing the subsequently initiated STI instruction and the awaiting interrupt request by means of the emulation software forming part of the host operating system without first changing the state of the VIF bit from its CLI state to its STI state. In other words, during the period that the emulation software executes these instructions, the VIF bit remains in its CLI state until the interrupt instructions have been executed and then and only then does the host operating system switch the VIF bit to its STI state. assuming no CLI instructions have been initiated in the meantime. Also, - now been executed, the since the previously awaiting interrupt request ha-L host operating software switches the VIP bit to its NONPENDING state, assuming that there are no other interrupt request awaiting execution.

It should be apparent that the manner in which computer system 36 handles interrupts, as described immediately above, differs from the way in which they are handled by system 34. Specifically, in system 36, when an interrupt instruction is pending and the virlual interrupt flag is in its CLI state, the subsequent STI instruction and the pending interrupt call are immediately executed upon by the emulation software without first changing the state of the virtual interrupt flag. This corresponds to the way in which the computer system 24 handles the same situation and, hence, is compatible with system 24, as contrasted with system 34 which, as stated previously, is not compatible with system 24 in this respect. This makes it easier and potentially more accurate to modify software programs that have previously been written for the 386 microprocessor forming part of system 24. Moreover, this approach allows the 386 microprocessor to distinguish between Stl instructions initiated directly from those initiated through POPF, as did the 386 microprocessor. This is important since following execution 1 -15of STI pending interrupts are accepted after a delay of one instruction, whereas following execution of POPF pending interrupts are accepted immediately. The 386 microprocessor proposal (Figure 3) does not have this capability.

Having described computer system 36 and the way in which it differs from proposed system 34, existing system 34 and original system 10, it is to be understood that the present invention is not limited to improvement in Intel Corporation's 386 microprocessor and its associated components, its 80486T1.1 microprocessor, or any related microprocessor, although the present invention is especially applicable to such microprocessors. However, it should be apparent from those aspects of systems 10, 24, 34 and 36 that the present invention relates only to the handling of interrupts and that only these features have been described. Obviously, each system includes oter components not relevant to the present invention. Those components and any components not shown but necessary tothe way in which these systems operate to handle interrupts would be obvious to one with ordinary skill in the art. Moreover, with particular regard to the STI and CLI instructions specifically, it is to be understood that the present invention handles them (either trapping them or not) in exactly the same way whether these instruction are issued by a particular DOS application directly or as a result of a POPF instruction. It is to be further understood that the present invention is not limited to the virtual mode of operation of the computer system. The new System 36 like System 24 is designed to operate in the protected mode or newer DOS applications specifically wdtten for the 386 microprocessor 26, taking advantage of the larger (32 bit) memory in this latter microprocessor. In System 24, when operating in the protected mode on this newer software (as opposed to the older software written for the 8086 system 10, STI and CLI instructions are trapped in the emulator 32 in the same way and under the same circumstances as they are trapped when the system operates on 8086 software in the virtual mode. The improvements in handling these particular instructions by system 36 in the virtual mode have been extended to the way in which they are handled in the protected mode.

In other words, whether the computer system 36 (Figure 4) is operating in virtual mode on 8086 software or in protected mode on 386 software, the STI and CLI instructions are handled in the same way.

HEiving described the way in which computer system 36 operates to handle interrupt instructions and its advantages over the prior art and previously proposed systems, attention is directed to Figure 5. This figure depicts a flow chart of the way in which system 36 handles interrupts in the manner described previously. Note specifically that this flow chart not only includes the differences between system 34 and 36, as described in conjunction with Figure 4, but also their similarities, as described in more detail in conjunction with Figure 3. In view of this particular flow chart and the teachings herein, one with ordinary skill in the art could readily practice the invention.

Turning now to Figure 5, a flow chart is illustrated there, depicting the way in which computer system 36 shown in Figure 4 handles STI and CLI instructions in accordance with the present invention. While this flow chart should be self-explanatory, a brief description will be provided here. As seen there, the first decision to be made is whether the instruction is a STI or a CLI. If it is a CLI instruction, the VIF flag 30" is made or maintained at 0 immediately (without going through emulation) and the process ends. If the instruction is a STI, then the VIP bit is read to determine if it is a 1 or 0. If the VIP bit is 0, the VIF bit is set to 1 and the process ends. If the VIP bit is a 1, then the process traps for emulation before ending the process.

1 t

Claims

1. In a computer system including a given microprocessor which is specifically designed to operate in a virtual operating mode that allows a software program previousty written for an earlier designed single program microprocessor to execute in a protected, paged, mufti-lasKing environment under a particularly designed host operating software program, said system further including means for executing certain sensitive interrupt related instructiong including CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI) initiated by said previously written program using emulation software forming part of said host program in order to emulate the way in which said instructions would have been executed by said earlier microprocessor, the improvement comprising:

(a) an EFLAGS register forming part of said given microprocessor and including (i) a VIRTUAL INTERRUPT FLAG (VIF) bit which operates between a STI state for enabling the execution of interrupt instructions initiated by said previously w ritten program and a CLI state for disabling the execution of said interrupt instructions; and (ii) a VIRTUAL INTERRUPT PENDING (VIP) bit which operates between a PENDING state during which interrupt requests are awaiting execution and a NONPENDING state in which no such interrupt requests are awaiting execution; (b) means forming parl of said given microprocessor and said host operating software for changing the state of the VIF bit of said EFLAGS register without the use of said emulation software, so long as the VIP bit is in its NONPENDING state; and (c) means forming part of said given microprocessor and said host operating software and responsive to the PENDING state of said VIP bit, the CLI state of said VIF bit and a STI instruction subsequently initiated by said previously written software program for automatically executing the STI instruction and an awaiting interrupt request by means of said emulation software without first changing the state of said VIF bit from a CLI state to STI state.

2. In a method of operating a computer system including a given microprocessor which is specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected. paged, multi-tasking environment under a particularly designed host operating software program, said system further including means for executing certain sensitive interrupt related instructions including CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI) initiated by said previously written program using emulation software forming part of said host program in order to emulate the way in which said instructions would have been executed by said earlier microprocessor, the improvement comprising the steps of:

(a) providing an EFLAGS register forming part of said given microprocessor and including (i) a VIRTUAL INTERRUPT FLAG (VIF) bit which operates between a STI state for enabling the execution of interrupt instructions initiated by said previously written program and a CLI state for disabling the execution of said interrupt instructions; and (ii) a VIRTUAL INTERRUPT PENDING (VIP) bit which operates between a PENDING state during which interrupt requests said previously written program are awaiting execution and a NONPENDING state in which no such interrupt requests are being executed or are awaiting execution; (b) changing the state or changes in state of the VIF bit of said EFLAGS register without the use of said emulation software, so long as the VIP bit is in its NONPENDING state; and 1 (c) in response to the PENDING state of said VIP bit, the CLI state of said VIF bit and a STI instruction subsequently initiated by said previously written software program automatically executing the subsequently initiated STI instruction and an awaiting interrupt request by means of said emulation software without first changing the state of said VIF bit from a CLI state to STI state.

3.. In a computer system including a given microprocessor which is specifically designed to operate in a protected operating mode that allows a given software program previously written for a large memory microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program, said system further including means for executing certain sensitive interrupt related instructions including CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI) initiated by said given program using emulation software forming part of said host program, the improvement comprising:

(a) an EFLAGS register forming part of said given microprocessor and including (i) a VIRTUAL INTERRUPT FLAG (VIF) bit which operates between a STI state for enabling the execution of interrupt instructions initiated by said given program and a CL] state for disabling the execution of said interrupt instructions; and (ii) a VIRTUAL INTERRUPT PENDING (VIP) bit which operates between a PENDING state during which interrupt requests are awaiting execution and a NONPENDING state in which no such interrupt requests are awaiting execution; (b) means forming part of said given microprocessor and said host operating software for changing the state of the VIF bit of said EFLAGS register without the use of said emulation software, so long as the VIP bit is in its NONPENDING state; and (c) means forming part of said given microprocessor and said host operating software and responsive to the PENDING state of said VIP bit, the CLI state of said VIF bit and a ST1 instruction subsequently initiated by said given program for automatically executing the STI instruction and an awaiting interrupt request by means of said emulation software without first changing the state of said VIF bit from a CLI state to ST1 state.

4. in a method of operating a computer system including a given microprocessor which is specifically designed to operate in a protected operating mode that allows a given software program written for a large memory microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program, said system further including means for executing certain sensitive interrupt related instructions including CLEAR INTERRUPT (CLI) and SET INTERRUPT (STI) initiated by said given program using emulation software forming part of said host program, the improvement comprising the steps of:

(a) providing an EFLAGS register forming part of said given microprocessor and including (i) a VIRTUAL INTERRUPT FLAG (VIF) bit which operates between a ST1 state for enabling the execution of interrupt instructions initiated by said given program and a CLI state for disabling the execution of said interrupt instructions; and Q1) a VIRTUAL INTERRUPT PENDING (VIP) bit which operates between a PENDING state during which interrupt requests are awaiting execution and a NONPENDING state in which no such interrupt requests are being executed or are awaiting execution', (b) changing the state or changes in state of the VIF bit of said EFLAGS register without the use of said emulation software, so long as the VIP bit is in its NONPENDING state; and (c) in response to the PENDING state of said VIP bit, the CLI state of said VIF bit and a STI instruction subseque.ntly initiated by said 1 -21previously written software program automatically executing the subsequently initiated STI instruction and an awaiting interrupt request by means of said emulation software without first changing the state of said VIF bit from a CLI state to STI state.