GB2259621A - Optical switch matrix arrangement - Google Patents

Abstract

An optical switch matrix arrangement comprises an array of optical switches, each switch being switchable between N, e.g. 2, states in which a light signal is directed selectively between a first node and any one of N further nodes of the switch. The arrangement further comprises oscillator means for oscillating each switch between the N states, the switches being arranged in ranks in a tree-like configuration with the N further nodes of a first switch in a first rank being each connected to a first node of one of N further switches in a second rank. The oscillator means is arranged to oscillate the switches in the second rank between the N states at a frequency that is 1/N x the frequency with which the switches in the first rank are oscillated. <IMAGE>

Description

Optical Switch Matrix Arransement The invention relates to an optical switch matrix arrangement for use, for instance, as a sampler or a multiplexer/demultiplexer of analogue optical data, or for use in processing digital optical data.

A known arrangement of this type is shown schematically in Figure 1, and is used for processing packets of digital data D spaced apart in time for reasons which will be explained later on. Each optical switch S1, S21-22 and S31-34 is arranged to selectively direct a light signal between an input node IN and one of the output nodes ON1, ON2, or vice versa. The switches may be formed using well known photographic mask techniques upon a suitable substrate. In one type of switch a voltage is applied between a pair of electrodes to alter the refractive index and thereby direct a light signal one way or the other. The switches are cascaded in a tree-like configuration with the output nodes ON1, ON2 of the switch S1 in the first rank being each connected to one of the input nodes IN of the two switches S21-22 in a second rank.The output nodes ON1, ON2 of the two switches S21-22 in the second rank are similarly connected to the input nodes IN of four switches S31-34 in the third rank, and so on. There can, of course, be more than the three ranks shown. The switches are driven by an oscillator or clock CLK operating at a suitable frequency.

In the known arrangements, each successive rank of switches is driven at twice the speed of the preceding rank. In this way the string of eight packets of data D shown is chopped in half at each rank and sorted so that each successive packet is placed on each successive output node ON1, ON2 of the third rank of switches S31-34.

A problem arises in that the switches in the highest order rank, which are the most numerous are driven at the highest speed. This causes difficulties in the design of the electrodes on the substrate. The maximum frequency of switching is governed by the well known resistance/capacitance RC time constant term. At relatively low frequencies of switching, pairs of parallel electrodes can be relatively large in area and the applied control voltage can accordingly be relatively low. As the frequency is increased, the electrodes must be reduced in area and the control voltages raised. At the highest frequencies, when the RC term limits transmission entirely, microwave type waveguides must be used to transmit the control signals which of necessity take up a larger area on a substrate upon which the matrix is located than control lines and a simple pair of electrodes.Where several such waveguides are required, as with a high order rank of switches, the need to provide the large area waveguides can make the matrix physically large, limit the frequencies used and make operation unreliable or impossible. It is for this reason that in the known use of these matrices, the digital data packets are spaced apart in time to provide a delay to minimise the chance of losing any data.

In one aspect the invention provides an optical switch matrix arrangement comprising an array of optical switches, each switch being switchable between N states such that a light signal is directed selectively between a first node and any one of N further nodes of the switch, the arrangement further comprising oscillator means for oscillating the switch between the N states, the array being such that the switches are arranged in ranks with the N further nodes of each switch in one rank are each respectively connected to a first node of one of N further switches in an adjacent rank, the oscillator means being arranged to oscillate the switches in the said adjacent rank between the N states at a frequency that is 1/N x the frequency with which the switches in the said one rank are oscillated.

It is much preferred that each switch includes two further nodes so that N equals 2. Accordingly, each successive rank oscillates at half the frequency of its predecessor. In this way, by oscillating the first rank at relatively high frequency, e.g. of the order of GHz for which large area waveguide type construction is required, the most numerous pairs of electrodes, i.e. in the higher order ranks, can be of straightforward low area parallel electrode design which can be run at relatively low voltages, simplifying the design and enhancing reliability.

It is also much preferred that the arrangement includes phase delay means for altering the phase of the oscillating signal applied to the switches within any particular rank.

An embodiment of the invention will now be described with reference to the accompanying drawings in which; Figure 2 shows schematically an optical switch matrix arrangement according to the invention; Figure 3 is a timing diagram of the clock pulses applied to each of the respective switches in the matrix; and Figures 4a and 4b show a typical low and a high frequency electrode arrangement respectively and are drawn to the same scale.

The optical switch matrix arrangement comprises optical switches S1, S21-22, and S31-34 each having an input or first node IN and two output or further nodes ON1, ON2 and arranged in ranks in tree-like configuration in a generally similar fashion to those described with reference to Figure 1. There is accordingly one switch S1 in the first rank, two switches S21-22 in the second rank and four switches S31-34 in the third rank. The matrix of switches may be formed using well known photographic mask techniques upon a wafer of, for instance, Lithium Niobate (LiNbo3), Gallium Arsenide (GaAs) or Indium Phosphide (InP).The switches may, for example, work by the application of a control voltage which alters the refractive index and accordingly allows a light signal to pass between the input node IN and one or other of the output nodes ON1, ON2.

A clock or oscillator CLK is arranged to drive the four switches S31-S34 in the third rank at a first frequency. Phase delays PD45, PD90 and PD135 are arranged to introduce a 450, 900 and 1350 phase lag to, respectively as shown, the second switch from the top, S32, third switch from the top, S33, and the top switch, S31, in the third rank, for reasons which will be explained later on. A multiplier M22 is arranged to multiply the output from the oscillator cI by two and apply that signal to the two switches S21-22 in the second rank. A phase delay device PD90 is arranged to introduce a 900 phase lag between switch S21 and 822. A further multiplier M12 is arranged to further multiply the output signal from multiplier M22 by two and then apply that to switch S21 in the first rank.

In use, an optical signal OS comprising, for instance, packets of digital data spaced in time, or a high bandwidth continuous analogue signal is applied to the input node IN of the switch S1 in the first rank. As shown, the optical signal OS is to be split into eight discrete portions. The frequency of the oscillator will be selected according to the spacing apart in time or frequency required of each of the optical signal portions. Switching the first switch S1 at the highest frequency will cause optical signal portions 1, 3, 5 to appear on ON1 and portions 2, 4, 6 and 8 on ON2.

By oscillating switches S21 and S22 at half the speed of S1, optical signal portions 1 and 5 will appear on ON1 of S21, and portions 3 and 7 on ON2. Similarly the other optical signal portions 2, 4, 6 and 8 appear on the appropriate output nodes of switch S22. The 900 phase lag provided by PD90 will ensure that a rising edge of a clock pulse will coincide with the beginning of optical signal portions 1 and 2 and the ensuing portions in each respective sequence.

Finally, supplying the optical signal portions to the switches in the third rank ensures that one portion only appears upon one output node. The phase delays will ensure that a rising edge of the clock pulse will coincide with the beginning of the respective required optical signal portion, as is shown clearly in Figure 3.

The arrangement described can be used, for example, both to demultiplex and multiplex packets of digital data, or to demultiplex or multiplex an optical analogue signal, according to whether the signals are applied to the first or input node of S1, or applied individually to each of the output or further nodes of switches S31 to S34.

Figure 4a shows a plan view from above of a typical electrode arrangement for low frequency use with one optical switch. Waveguides (not shown) for directing optical signals between the first and further nodes of the switch would be present, as shown, underneath the electrodes which comprise a planar ground electrode EG and a further planar electrode EV to which a control signal would be applied.

Figure 4b shows, to a similar scale as Figure 4a, a typical electrode arrangement for high frequency use where the applied control signals might be of the order of GHz.

The difference in size is very clearly shown.

It will of course be appreciated that the oscillator may be arranged to directly drive one of the intermediate ranks and accordingly preceding ranks may be driven by means of a multiplier, or any other suitable oscillator arrangement may be used. For example, the oscillator may drive the switch in the first rank and that signal will then be successively divided for each successive rank. The oscillator may output signal resembling a sine wave, rather than the square wave shown. Although the invention has been described with reference to a switch having two output nodes, so that N = 2, it is envisaged that a switch could be constructed having more than two output or further nodes and where the oscillator frequency would need to be multiplied for preceding ranks by a number greater than 2.

Claims (6)

1. An optical switch matrix arrangement comprising an array of optical switches, each switch being switchable between N states such that a light signal is directed selectively between a first node and any one of N further nodes of the switch, the arrangement further comprising oscillator means for oscillating the switches between the N states, the array being such that the switches are arranged in ranks with the N further nodes of each switch in one rank being each respectively connected to a first node of one of N further switches in an adjacent rank, the oscillator means being arranged to oscillate the switches in the said adjacent rank between the N states at a frequency that is 1/N x the frequency with which the switches in the said one rank are oscillated.

2. An optical switch matrix arrangement, according to claim 1, comprising phase delay means for altering the phase of the oscillating signal applied to the switches within a rank.

3. An optical switch matrix arrangement, according to any preceding claim, in which N = 2.

4. An optical switch matrix arrangement, according to any preceding claim, in which a multiplier is provided for multiplying the oscillating signal from a succeeding rank.

5. An optical switch matrix arrangement, according to any of claims 1 to 3, in which a divider is provided for dividing the oscillating signal from a preceding rank.

6. An optical switch matrix arrangement substantially as described with reference to the drawings.