GB2259405A - Semiconductor read only memory - Google Patents

Abstract

A mask read only memory (mask ROM) in a semiconductor memory device has parallel diffusion regions 23 of a given conductivity type extending in a first direction and separated from one another by isolation regions 21. Parallel word lines extend in a second direction perpendicular to the first direction. Bit lines 31, 33 extend in the first direction over the word lines 25 and respective isolation regions 21 between diffusion regions 23, and contact word lines 25 through respective contact regions 27, 29. Each of the bit lines 31, 33 does not overlie the diffusion regions 23 adjacent the isolation region 21 that it does overlie. Thus, since the bit line 33 is separated from the diffusion regions 23 by a given interval, more efficient programming in a program region 35 can be attained, and turn around time (TAT) can be greatly reduced. <IMAGE>

Description

7,r r 4r c MEEMORY DEVICES The present invention relates to semiconductor

memory devices, and more particularly to mask read only memory devices.

Generally, in order to reduce a TAT (Turn Around Time) of a mask read only memory (hereinafter referred to as a mask ROM), a method for programming data after metal etching is employed.

Figure 1 of the accompanying diagrammatic drawings is a layout illustrating a conventional NAND type mask ROM in which a plurality of MOS transistors are serially connected. A diffusion region 3 is separated from another diffusion region by an isolation region 1 made of a field oxide layer. The adjacent diffusion regions extend parallel to one another in a first direction, the isolation region 1 also extending in the first direction. Word lines 5 of a polysilicon layer extend in parallel in a second direction which makes a right angle with the first direction. Bit lines 11 and 13 of a metal layer each extend in the first direction over a respective isolation region 1 and diffusion regions 3 adjacent to the isolation region 1, and contact with word lines 5 through first and second contact regions 7 and 9. A word line 5 and a diffusion region 3 adjacent thereto constitute a program region 15 where impurities are implanted when given data is programmed in a mask ROM.

In this case, when programming data before the polysilicon layer constituting the word lines are formed, or after an n-type (or p-type) diffusion region of high concentration is formed, desired data can be programmed.

However, in the case of programming data after bit lines are formed by patterning a metal layer with a photolithography process, impurities may not pass into a region where a bit line and a diffusion region overlap. Therefore, desired data can not be programmed in a program region.

Preferred embodiments of the invention aim to provide a mask ROM 5 capable of programming data even after forming a bit line.

In accordance with one aspect of the present invention, a bit line is formed only on an isolation region between diffusion regions.

According to another aspect of the present invention, there is provided a mask read only memory device comprising:

a plurality of diffusion regions of a given conductivity type extending parallel to one another in a first direction, the or each pair of adjacent diffusion regions being separated from one another by a respective isolation region; a plurality of mutually spaced word lines extending parallel to one another in a second direction perpendicular to said first direction; and a bit line extending in said first direction and contacting with one of said word lines through a respective contact region, the bit line overlying the word lines and a respective isolation region, but not overlying the diffusion regions that are separated by that isolation region.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figure 2 of the accompanying diagrammatic drawings, which is a layout 1 schematic view of one example of a mask ROM embodying the present invention.

Referring to Figure 2, diffusion regions 23 extend in a first direction parallel to one another, and are separated by isolation regions 21 formed with a field oxide layer, the isolation region 21 extending also in the first direction. Word lines 25 of a polysilicon layer extend parallel to one another in a second direction which makes a right angle with the first direction. Bit lines 31 and 33 of a metal layer extend in the first direction within a region corresponding to a respective isolation region 21 and are disposed over an arrangement of word lines 25, and contact with the word lines 25 through first and second contact regions 27, 29.

A word line 25 and a diffusion region 23 adjacent thereto constitute a program region 35 where impurities are implanted when programming data in a mask ROM. Moreover, since the respective bit line 33 is separated from the adjacent diffusion regions 23 by a given interval, impurities for programming the data can still be implanted into the bottom of the respective word line 25.

As described above, in a mask ROM, desired data can be easily programmed in a program region by forming a bit line over the upper portion of an isolation region without overlapping with a diffusion region. Therefore, a TAT of a memory device can be greatly reduced. Furthermore, since spacing between bit lines is enlarged, capacitance between the bit lines can be reduced.

While a preferred embodiment of the present invention has been particularly shown and described, it will be understood by those skilled in the art that foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), andlor all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (2)

CLAINIS

1. A mask read only memory device comprising:

a plurality of diffusion regions of a given conductivity type extending parallel to one another in a first direction, the or each pair of adjacent diffusion regions being separated from one another by a respective isolation region; a plurality of mutually spaced word lines extending parallel to one another in a second direction perpendicular to said first direction; and a bit line extending in said first direction and contacting with one of said word lines through a respective contact region, the bit line overlying the word lines and a respective isolation region, but not overlying the diffusion regions that are separated by that isolation region.

2. A mask read only memory device substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.