GB2255478A

GB2255478A - Apparatus for data transfer between personal computers.

Info

Publication number: GB2255478A
Application number: GB9106028A
Authority: GB
Inventors: David Chao; Nick Hunn
Original assignee: HUNN N; TDK Grey Cell Ltd
Current assignee: HUNN N; TDK Grey Cell Ltd
Priority date: 1991-03-21
Filing date: 1991-03-21
Publication date: 1992-11-04
Also published as: GB9106028D0

Abstract

The method increases the rate at which data can be transferred from the existing Parallel Output Port of a Personal Computer by up to a factor of two. This is achieved by employing external transmitting and receiving hardware to permit the transmission of complete bytes. It splits each 8 bit word into two 4 bit segments at the receiving node, for reading into the parallel part of the receiving PC. Any transmitter node can be reconfigured in situ to respond as a receiver by use of Field Programmable Gate Arrays or other reprogrammable logic devices.

Description

APPARATUS FOR DATA TRANSFER BETWEEN PERSONAL COMPUTERS The invention provides a method of transferring data files between personal computers. It increases the rate at which such data can be transferred using the existing Parallel Output Port of the Personal Computer by up to a factor of two. This is achieved by employing external transmitting and receiving hardware to permit the transmission of complete bytes.

A number of different methods exist for transferring files between Personal Computers, most of which have some limitations. At the simplest level, data can be transferred by physically exchanging floppy discs, as long as these are of the same size and type. At a more complex level, data can be transferred through the serial ports, but this is slow, as many serial ports are limited to a transfer rate of 9,600 bits per second. Alternatively, techniques exist to send data via the parallel port, which can support data rates in excess of 56,000 bits per second. However, the parallel port on the vast majority of Personal Computers is not bidirectional. Although data can be output as an 8-bit word, it can only be read in by using some of the control lines on the port which function as inputs. These limit the maximum number of bits which can be input at any time to 5.Systems which implement data transfer using the parallel port have always had to compromise by breaking down the data byte into two segments of 4 bits and transmitting these one after the other.

This invention doubles the potential data transfer rate by transmitting the complete 8 bit data byte. This is achieved by adding an external unit to each PC, which can either transmit or receive a full 8 bit word. This is then broken in half within the receiving node into two separate 4 bit segments, which can be read one after the other into the receiving computer. While this is taking place, the external hardware requests the next byte from the transmitting computer. By this method, the potential data transfer rate is doubled, as the processing into two segments can be performed at high speed in the receiver node hardware.

Another important aspect of the invention is the way in which it allows data to be transferred between two computers, both of them fitted with transmitters. The hardware in the transmitter nodes is implemented using field programmable gate arrays (FPGA's). These devices have the abitlty to be programmed to perform different digital functions. By reprogramming them in situ, it is possible to convert the transmitter nodes into receiver nodes. This ability is exploited to transfer files between computers. Any number of computers can be connected together, all configured in the quiescent state as transmitters. When file transfer is required, one of the Personal Computers will run a software program which will result in data being output from the computer's parallel data port to re-configure the FPGA in that node as a receiver. Any one of the transmitters can then make contact with this receiver, and initiate data transfer. At the end of the data transfer, a special data packet is received, which will cause the receiving computer to return the FPGA to its original status as a transmitter. In this manner, file transfer can be initiated between any two nodes, regardless of the total number of nodes, or the order in which they are connected.

Claims

1. A data transfer system consisting of two or more nodes connected externally to the parallel ports of personal computers and to each other, which permits transmission of full 8 bit words from the parallel port of the transmitting Personal Computer, and then splits each 8 bit word into two 4 bit segments at the receiving node, allowing them to be read into the parallel port of the receiving Personal Computer.

2. A data transfer system according to Claim 1, wherein any transmitter node can be reconfigured in situ to respond as a receiver, by the use of Field Programmable Gate Arrays or other reprogrammable logic devices.