GB2249840A - Universal digital input channel - Google Patents

Abstract

To detect the on/off state of a switch (SW1) in a circuit including a source (Ve) and a varistor (RV1), a bridge (BR) rectifies the voltage existing across the varistor (RV1) and energises a circuit including two transistors (TR1, TR2) and two LED's (D1, ISD1), one of the LED's (ISD1) being an opto-isolator device in an output circuit including an amplifier (ICA). With the switch on, both LED's emit light and an electrical output (01) is produced by the amplifier (ICA). <IMAGE>

Description

UNIVERSAL DIGITAL INPUT CHANNEL This invention, Universal Digital Input Channel relates to an electronic circuit employed for inputting ON/OFF type digital data to electronic and computing machines for processing.

It is primarily aimed at industrial automation applications where, field data from typically remote switches and binary output sensors, need to be converted to a suitable signal for interfacing to supervisory and/or control systems.

2. Introduction There are three broad categories of signals to which, computing and control systems interface. These are analogue, digital and pulse types respectively.

Analogue signals such as temperature, pressure, speed, level etc., constitute the most prevalent category and generally embody a broad spectrum of amplitude and frequency varying variables encountered in most natural and man made processes.

Digital or two-state signals largely exist within the domain of man made systems and thus, can only assume one of two mutually exclusive states such as ON/OFF, HIGH/LOW etc. They can be regarded as a special type of analogue signals with pre-defined amplitude conventions. In the field, steady state digital signals typically originate from switches or sensors designed to approximate often inherently analogue variables into two state representations above or below a desired threshold.

Pulse signals constitute digital signals with a broad variation in frequency domain.

3. Signal Interfacing Techniques Most electronic/computer based supervisory and control systems require a relatively large number of signal inputs. The state or value of the input variables are fed to a hardware/software control algorithm. This in turn generates a number of output states/values to be conditioned and interfaced to the process in order to mantain it within desired operating conditions.

Analogue signals typically require careful input conditioning in order to provide a true representation of the measured variable. The conditioning is often in the form of amplitude scaling, frequency limiting/filtering and analogue to digital conversion which lies beyond the scope of the present document.

Digital variables on the other hand are easier to detect and interface. For example, the ON or OFF state of a switch is readily determined by it's ability to complete an electrical circuit when closed (ON). This technique is widely employed in interfacing digital signals to electronic/computer supervisory and/or control systems. A voltage source is typically applied via the switch/sensor whose state is to be determined, to a current/voltage sensitive device/circuit. The closure of the switch completes the electrical circuit allowing voltage to appear accross or current to flow through the sensing device/circuit thus changing it's state. Figure 1 represents the principles of this method of detection.

4. Digital Signal Interfacing: The ability of a switch or a binary sensor such as a Thermostat to complete an electrical circuit upon closure, is widely employed to detect the state of such devices in electronic/computing supervisory and/or control systems. Normally a DC voltage source of limited amplitude is applied to such circuits as the excitation energy. The state of a switch is thus determined through an appropriate method of detecting the current flow through the circuit. The ON or OFF state of the switch corresponding to flow or no-flow of electrical current in such a circuit is thus determined through a current/voltage sensing device in the same circuit.

Figure 1 represents the general principles of ON/OFF type signal interfacing to supervisory and control systems.

Programmable Logic Controllers ( PLC's ) are computer based machines, in widespread use throughout industry. These are often equipped with a limited number of digital ( ON/OFF ) input and output channels. The digital input channels on PLC's predominately employ the principles of state detection highlighted above.

5. Universal Digital Input Channel ( UDIC ): This innovation relates to an electronic circuit employed to detect the state of a switch by the application of any AC or DC excitation voltage from a few volts up to the mains level. Most digital input channels can cope with DC or AC excitation voltages of limited range.

The Universal Digital Input Channel ( UDIC ) differs from the common circuits, in it's ability to cope with DC and AC excitation voltages ranging from a few volts to a few hundred volts dynamically. This versatility is achieved through exploitation of a novel solid-state circuitry.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which; Figure 1 represents general principles of digital state detection, Figure 2 represents a typical UDIC circuit arrangement.

A typical field switch SW1 in series with the excitation voltage source Ve is applied to the inputs I1,I2 of the UDIC in Figure 2. The excitation voltage source may be of AC or DC type with RMS values from a few volts to 240 volts maximum. The UDIC inputs are not polarity sensitive.

The Varistor RV1 is rated at just above 240V RMS and is intended to absorb impulse noise. The bridge rectifier BR rated at 1 Ampere maximum is employed to rectify the AC inputs. TR1 and TR2 are N channel depletion mode MOSFET transistors. They are equivalent to normally ON switches each rated at V(BR)Dss > 240V.

Resistors R1 & R2 are biasing elements for TR1,TR2 while R1 is intended for static current limiting. The LED D1, is employed as status indicator which is in series with the opto-isolator ISO1.

The optical device is chosen to provide high voltage galvanic isolation between the input and output of UDIC.

5.1. Circuit Operation; The principles of operation of UDIC are now described with reference to the circuit of Figure 2 in which, a field switch SW1 in series with an AC/DC excitation voltage source are connected to the input terminals I1,I2 for illustartion only.

When SW1 is open ( OFF ), no current would flow through the circuit composed of the Ve, SW1 and UDIC. The status indicator D1 would not be lit and the UDIC output at Ol would be LOW.

Upon closure of SW1, the electrical circuit would be completed and AC or DC current would flow through the input stage of UDIC. Voltage spikes and transients greater than 240V would be absorbed by RV1. Current would flow through SW1, BR, TR1, R2, R1, D1, ISO1, TR2 and R5. At low voltage/current levels, TR1 and TR2 are almost fully ON, posing very little resistance. Hence, under these conditions, the magnitude of current would be determined by the voltage applied at I1,I2 less the drop across Dl,ISO1 divided by the value of R1. With the values shown in Figure 2, the input current would be of the order of 7 mA at 24V DC nominal excitation voltage. This is termed the " Static " mode of operation.

However, as the excitation voltage is increased, there would be a tendency for the current in the input stage of UDIC to increase. Owing to the presence of TR1 & TR2 in the UDIC, the increase in current due to a rise in excitation voltage would be counteracted by the increasing negative bias produced by R2 & R5.

This bias applied between the gate and source of the depletion MOSFETs, would gradually force them into less conductive region, thus dynamically increasing the circuit ( UDIC ) impedance. This increase in circuit impedance in turn limits the current flow, protecting SW1 and UDIC from damage which would otherwise be caused by large currents at high excitation voltages ( > 100V ).

It is this " Dynamic " impedance characteristic which enables UDIC to cope with excitation voltages from 12 volts to 240 volts AC or DC without damage.

The closure of SW1 would produce a HIGH voltage at the output 01.

5.2. Special Considerations; In a typical UDIC implementation, the value of R1 would determine the " Static " i.e. low voltage ( in the region of few tens of volts ) current flow in the circuit. The value of R1 limiting resistor is calculated to provide sufficient current flow through the circuit under " Static " conditions. This corresponds to the lowest nominal excitation voltage which in the case of UDIC is rated at 12V RMS.

The biasing resistors R2 and R5 are typically much smaller in value than R1 and their values determine the maximum current through the input stage of UDIC at high excitation voltages ( > 100V RMS ) i.e. the " Dynamic " mode of operation. The highest nominal excitation voltage in the case of UDIC is rated at 240V RMS which implies that Mains voltage can be safely employed as the external excitation voltage in series with the field switch.

The sensitivity of the circuit in the " Static " mode of operation can be further adjusted via R4 which, supplies a ground path for the base current of the opto-transistor in the opto-coupler.

A UDIC channel can typically cope with excitation currents ranging from 2mA to lOmA maximum. It is also necessary to closely match the VGS(tb) of the TR1 & TR2 in order to ensure reasonable load sharing between the devices in the " Dynamic " mode of operation.

5.3. Application Specific Features; The optional filtering circuit shown in figure 2 may be of simple RC type networks employed to debounce the field switch SW1.

Some operational specifications such as the isolation voltage between the front-end and the output stage largely depend upon the circuit layout as well as the isolation specifications of the opto-isolator employed in the circuit.

Depending on the real-estate available on the Printed Circuit Board ( PCB ), a large number of UDIC channels may be designed on a single board for simultaneous parallel operation.

This may be of interest in the transmission of parallel digital data over long distances using high voltages to compensate for line drops.

If AC voltage is to be used for excitation, application of a llOV AC, safety transformer is recommended. These transformers provide a ground referenced centre tap on their secondary thus, reducing the probability of electrical shock in the event of contact with the 110V output.

Claims (1)

1. 6. Claims

   Universal Digital Input Channel ( UDIC ) provides an innovative, cost effective and convenient method for interfacing ON/OFF type data to electronic/computer based supervisory/control systems.

   UDIC employs a novel yet simple and low cost solid-state circuitry and provides non-polarised input terminals for convenience and ease of field wiring.

   Application of UDIC removes the requirement for often expensive special purpose power supplies employed as excitation voltage source in most digital input schemes.

   Application of UDIC permits the use of any convenient voltage source from 12V DC ( Battery ) up to 240V AC Mains voltage in interfacing ON/OFF data to supervisory/control systems.

   UDIC provides a universal circuit for sensing the status of ON/OFF type data while, galvanically isolating the front-end interface circuitry from the rest of the supervisory/control system.

   Application of UDIC leads to a considerable reduction in inventory of digital input interfaces for the manufacturer as well as the user. This would be of particular relevance to Programmable Logic Controllers ( PLC's ) which typically employ a broad range of digital input interfaces for various excitation voltage levels and AC/DC types.