GB2249418A

GB2249418A - Bit- or word-line layout of a semiconductor memory

Info

Publication number: GB2249418A
Application number: GB9023721A
Authority: GB
Inventors: Dong-Sun Min; Dong-Soojun; Soo-In Cho; Yong-E Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-10-31
Filing date: 1990-10-31
Publication date: 1992-05-06
Also published as: GB9023721D0; DE4034693A1

Abstract

In order to reduce the inter-bitline (and/or word line) capacitance of a semiconductor memory at least two pairs of adjacent bit lines B0, B0, B1, B1 are twisted at the same point along their length. Sense amplifiers SAU, SAD may be disposed at either end of the bitlines and are connected to that pair of bitlines which are there adjacent. <IMAGE>

Description

2 24 ',) 4 1; 1 SEMICONDUCTOR MEMORY DEVICE The present invention relates

to a semiconductor memory device and is particularly useful when applied to a DRAM (Dynamic Random Access Memory).

In a conventional DRAM, each memory cell comprises a capacitor and a MOS transistor connected between bit and word lines in the form of a matrix. The bit lines are parallel with each other and have the same length. Also, each pair of bit lines is connected to a respective flip-flop type sense amplifier.

As the development of the DRAM has a tendency toward high integration density, the size of each element thereof becomes ever more minute. Thus, the space between the bit lines becomes narrower and the storage capacitor of the memory cell is smaller. Consequently, incorrect operation of the sense amplifier has resulted from the mutual coupling capacitance between a bit line of a working sense amplifier and bit lines thereabove or thereunder during memory cell access and operation of the sense amplifier.

Fig. 1 shows a circuit diagram of a conventional folded bit line structure. In Fig. 1, memory cells MC10 MC12 and MC20 - MC22 are connected at the intersections of bit lines BO, 9-0,.... B2, 9-2 and word 2 lines W1 and W2._ Also, several pairs of bit lines (BO, 13-5), (B1, -B-1) and (B2, 02) are connected to sense amplifiers SAO to SA2 respectively. Each memory cell comprises a MOS transistor M and a storage capacitor C, which is connected in parallel with the drain-source path of the MOS transistor M. Each drain of the MOS transistors is connected to a different bit line BO, F-0, B2, i-2, and each gate of the memory cells MC10 MC12 and MC20 MC22 respectively is connected to one of the word lines W1 and W2. One terminal of the storage capacitor C is connected to a common voltage terminal VP. Capacitances CBS represent schematically the coupling capacitances between each bit line and the substrate, capacitances CBB represent schematically the coupling capacitances between each two adjacent bit lines, and Cs indicates the storage capacitance of each storage capacitor C.

If the memory cells MC10 - MC12 are selected by a signal applied to the word line W1, the charges in the storage capacitors C of these selected memory cells are transferred to the bit lines BO - B2 through the MOS transistors M, respectively. Thus, each voltage of the respective bit line BO - B2 is increased or decreased by aVs (AVs = (VS - VB ) CS), relative to the CBs + 2CBB+C s Potential on the other bit lines BO - 9725, where Vs indicates the voltage of the storage capacitor C and VB 3 indicates the voltage of the bit line before the selection of memory cells.

When the voltage of the bit lines BO - B2 is increased as much as AVS relative to that of the other bit lines '90 - 9-2 by the memory cells MC10 - MC12, the sense amplifiers SAO - SA2 are activated in order to decrease the voltage of the bit lines fo - M which.is already lower by as much as aVS than that of the bit lines BO - B2. At this time, the voltage at the bit line BI is decreased due to the effect of the coupling capacitance CBB in relation to its adjacent bit lines TO and T-1 at the decreased voltage. This effect becomes a more serious problem the more the space between the bit lines BO - B2 and 90- - 9-2 and the capacitance of memory cells MC10 MC12 and MC20 - MC22 are decreased.

In order to quantify this effect, a coupling ratio a indicating the degree of the coupling noise between the bit lines BO - B2 and 9-0 is represented as follows:

a =. C BB (%)... (1) Cs +CBS +2CBB In equation (1), if the space between the bit lines BO - B2 and 9-0 921 is reduced, the coupling 4 capacitance CBB is then increased and thus the coupling ratio a is also increased in response to the decrease of the storage capacitance CS of the memory cells MC10 - MC12-and MC20 - MC22.

As mentioned above, if the coupling noise between the bit lines is increased, the operational margin of the sense amplifier is reduced and thus the sense amplifiers are prone to operate incorrectly. In order to solve this problem, a memory circuit employing a twisted bit line structure as shown in Fig. 2 has already been developed.

In Fig. 2, each pair of bit lines such as (B0, IM), (B1, M1), (B2, -9-2) and (B3, U-3) is twisted 2N times or more (N: integer) and the sense amplifiers SAO - SA3 are connected to one end of each pair of bit lines (B0, UO), (B1, Bn), (B2, JB-72) and (B3, M). Each pair of bit lines (B0, 90), (B1, E), (B2, U22) and (B3, T35) is twisted twice; alternate pairs (B0, 905), (B2, 9-2), (B4, etc. are twisted at the same positions and the other pairs (B1, 911), (B3, 9-3), etc. are twisted at different positions; consequently, adjacent pairs of bit lines are not simultaneously twisted at their intersection with the same word line; the coupling capacitance can be reduced about 50% relative to the folded bit line structure as shown in Fig. 1.

Therefore, even though the inter-coupling capacitanc within each pair of bit lines is maintained, the inter-coupling capacitance between different adjacent pairs of bit lines can be eliminated. Thus, the total coupling capacitance of the bit line is reduced by about 50% and the coupling noise occurring between adjacent bit lines can be reduced considerably. However, in order to remove the inter-coupling capacitance, the twisting of each bit line pair should be made at least twice. Thus, the layout area of the memory cell array is greatly increased and it is difficult to achieve a high integration of the memory cells.

The aim of the present invention is therefore to provide a semiconductor memory device which can reduce the coupling noise without suffering from a layout area much greater than that of the conventional folded bit structure.

According to the present invention, there is provided a semiconductor memory device comprising: bit lines arranged in parallel and twisted, at the same lengthwise position as a unit of at least two adjacent pairs of bit lines each of which pairs consists of bit lines which are adjacent at one end; word lines intersecting the bit lines; sense amplifiers connected to the ends of the respective bit line pairs; and 6 memory cells connected at the intersections of the bit lines with the word lines.

These and other objects, features, and advantages of the present invention will become more apparent from the following description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a circuit diagram of a conventional DRAM with folded bit lines; Fig. 2 is a circuit diagram of a conventional DRAM with twisted bit lines; and Fig. 3 is a circuit diagram of a DRAM with twisted bit lines embodying the present invention.

Fig. 3 shows a circuit diagram of a DRAM having a twisted bit line structure embodying the present invention. In Fig. 3, upper sense amplifiers SAU are located in a row at the upper side and lower sense amplifiers SAD are located in a row at the lower side of a substrate. Bit lines (BO, M) and (B2, Iff-2) are connected to respective upper sense amplifiers SAU, while other bit lines (B1, YU and (B3, ff-3) are connected to respective lower sense amplifiers SAD. Memory cells MC10 - MCK3 are respectively connected at the intersections of the bit lines BO - B3 and 50 B with the word lines W1 - WK.

1 7 The pairs of bit lines (BO, fO) and (R2, -B3-7) connected to the upper sense amplifiers SAU and the other pairs of bit lines (B1, 9-1) and (B3, 9-3) connected to the lower sense amplifiers SAD are twisted once at the same lengthwise position as each other. Each bit line crosses at least one other. That is, the bit lines (BO, FO') and (B2, 9-2) of each pair are adjacent where they are connected as a pair to the respective upper sense amplifier SAU, and similarly the bit lines (B1, iff) and (B3, -B-7) are adjacent to each other where they are connected as pairs to the lower sense amplifiers SAD, but the bit lines are all twisted at the same lengthwise position in such a manner that the pairs of bit lines (BO, TO) and (B2, E-2) are led outside the pairs of bit lines (B1, 9-1) and (133, B3) respectively, and vice versa. The bit lines (BO, IBM) exchange transverse positions with the bit lines (B1, -B-1) so that each pair is adjacent at a different side of the substrate for connection to its sense amplifier; and the four bit lines as a group or unit are twisted at the same position. This is also true of the bit lines (B3, B3) and (B4, E-4), which together constitute a second unit. In effect, one pair of bit lines is interposed between the two separated bit lines constituting the other pair, looking in one direction, and vice versa looking in the other direction. Thus, after this twisting, the bit lines are arranged to be adjacent to a new bit line.

8 In this example, for the greatest saving in chip area, each unit of bit lines is arranged to fold at the same position on the chip, lengthwise of the bit lines.

Accordingly, both the inter-coupling capacitance and the inter-coupling capacitance are reduced by about 50%, so that the total coupling capacitance is also reduced by about 50% and the coupling noise can be reduced efficiently. Moreover, since the sense amplifiers SAU and SAD are separately arranged on respective upper and lower sides, the size of each sense amplifier SAU and SAD can be increased, and an ampliflcation margin can be increased. Moreover, all bit lines are twisted only once, as part of a unit of four bit lines, so that the increment in the overall memory cell area is reduced to a half compared to that of the conventional twisted bit line structure in which the bit lines are twisted twice.

The relationship between the incremental coupling noise and the memory cell area, and the respective bit line structure is shown in Table 1 below:

bit line chip coupling noise between bit lines structure area interintra- total coupling coupling noise noise folded 0 A N A N 2AN bit line conventional twisted AA 0 16 N 'd N bit line twisted bit line according to Y2A A Y2A N Y2AN A N the present invention Ibble 1 9 Referring to Table 1, the chip area of the conventional twisted bit line structue is larger by AA than that of the folded bit line structure and the chip area of the twisted bit line structure embodying the present invention is larger by only 1/2.4A than that of the folded bit line structure.

On the other hand, the inter-coupling noise and the inter-coupling noise in the folded bit line structure are both N and thus the total coupling noise becomes 2.dN. Next, in the conventional twisted bit line structure, there is no inter-coupling noise and the inter-coupling noise is 4 N. Consequently in the twisted bit line structure according to the present invention, the inter-coupling noise and the inter-coupling noise are both 1/2AN. For the twisted bit line structures of both the conventional structure and that embodying the present invention, the total coupling capacitance is dN.

Heretofore, the present invention has been illustrated in terms of twists of the bit lines, but even in the case of twists of the word lines the use of the present invention can obtain corresponding results. As before, a plurality of the upper sense amplifiers SAU are located in a row at the upper side and a plurality of the lower sense amplifiers SAD are located in a row at the lower side. The bit lines (B0, U-0) and (B2, 15-7) are respectively connected to each upper sense amplifier SAU, and the bit lines (B1, T11) and (B3, W3) are respectively connected to each lower sense amplifier SAD. The memory cells MCIO - MCK3 are connected at the intersections of the bit lines BO - B3 and UO 9-3 with the word lines W1 WK. In this case, however, the word lines are twisted as a unit of four adjacent word lines at the same position, instead of twisting the bit lines. After this twisting, each word line is arranged to be adjacent to a new word line. Also, according to the present invention, four adjacent word lines and two pairs of bit lines can be twisted simultaneously.

It is a significant feature of the invention that, once the bit or word lines have been twisted at one position, there is no need for them to be twisted again, so that adjacent lines, once separated by twisting, need not become adjacent again.

As mentioned hereinabove, according to the present invention, the intercoupling noise and the inter-coupling noise can be reduced efficiently and the increment of the chip area due to twisting can be minimized by twisting all the bit lines only once as a unit of at least four adjacent bit lines.

t The present invention is in no way limited to the embodiment described hereinabove. Various modifications of disclosed embodiment as well as other embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention.

12

Claims

1. A semiconductor memory device comprising: bit lines arranged in parallel and twisted, at the same lengthwise position as a unit of at least two adjacent pairs of bit lines each of which pairs consists of bit lines which are adjacent at one end; word lines intersecting the bit lines; sense amplif-Jers connected to the ends of the respective bit line pairs; and memory cells connected at the intersections of the bit lines with the word lines.

2. A semiconductor memory device according to Claim 1, wherein the bit lines at one end thereof are arranged in parallel in a different sequentia,l order from their arrangement at the opposite end thereof, due to the twisting occurring at only one position between the said ends.

3. A semiconductor memory device according to Claim 1 or 2, wherein the twisting of two pairs of bit lines consists of interposing one pair of bit lines between the two separated bit lines constituting the other pair.

4. A semiconductor memory device according to Claim 1 2 or 3, wherein the sense amplifiers are connected to the respective bit line pairs at the ends at which the w 1 13 bit lines are adjacent.

5. A semiconductor memory device according to Claim 1, 2, 3 or 4, wherein the sense amplifiers are divided into two groups located respectively at upper and lower sides of the device corresponding to respective ends of the bit lines.

6. A semiconductor memory device according to Claim 5, wherein each of the sense amplifiers is connected to a respective one of the pairs of bit lines at the end at which it is interposed between the separated bit lines of a different pair of bit lines.

7. A semiconductor memory device comprising: bit lines which are arranged in parallel; word lines intersecting the bit lines and twisted, at the same lengthwise position as a unit of at least four adjacent word lines; sense amplifiers connected to the ends of the pairs of bit lines; and memory cells connected at the intersections of the bit lines with the word lines.

8. A semiconductor memory device according to Claim 7, wherein the word lines at one end thereof are arranged in parallel in a different sequential order from their arrangement at the opposite end thereof, due to the 14 twi s ti ng.

9. A semiconductor device according to Claim 8, wherein the sense amplifiers are divided into two groups located respectively at upper and lower sides of the device corresponding to respective ends of the word lines.

10. A semiconductor device according to Claim 7, 8 or 9, in which the bit lines are arranged in parallel and twisted at the same lengthwise position, as a unit of at least two adjacent pairs of bit lines each of which pairs consists of bit lines which are adjacent at one end.

11. A semiconductor memory device substantially as described herein with reference to Figure 3 of the accompanying drawings.

12. A semiconductor memory device according to any preceding claim in which the memory cells are DRAM cells.