GB2239748A - Direct frequency synthesiser - Google Patents
Direct frequency synthesiser Download PDFInfo
- Publication number
- GB2239748A GB2239748A GB9000317A GB9000317A GB2239748A GB 2239748 A GB2239748 A GB 2239748A GB 9000317 A GB9000317 A GB 9000317A GB 9000317 A GB9000317 A GB 9000317A GB 2239748 A GB2239748 A GB 2239748A
- Authority
- GB
- United Kingdom
- Prior art keywords
- clock
- output
- filter
- waveform
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B1/00—Details
- H03B1/04—Reducing undesired oscillations, e.g. harmonics
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/548—Trigonometric functions; Co-ordinate transformations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Software Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A direct frequency synthesiser includes an accumulator 2 having an input receiving a digital word representative of the desired frequency, a clock controlling the successive adding of the digital word to the contents of the accumulator 2 to provide a periodically varying value at the output of the accumulator, means 10, 12, 14 for providing from the periodically varying value, values representing a waveform of desired shape, a digital to analog converter (DAG) 8 providing the waveform in analog form, and a clock-operated filter (not shown) coupled to the input or the output of the DAC 8 having means for deriving a clock signal from the waveform at the input or output of the filter, which clock signal is employed to enable operation of the filter. <IMAGE>
Description
DIRECT FREQUENCY SYNTHESISER This invention relates to a direct frequency synthesiser.
Direct frequency synthesisers are known and are for example described in IEEE Journal of Solid-State Circuits, Vol. 23 No. 3 June 1988 "A Direct Digital Synthesiser with 100 MHz Output Capability"
P.H. Saul, M.S.J. Mudd pp 819 to 821. Such a synthesiser is shown in
Figure 1 as comprising an accumulator 2 for receiving a digital word at an input 4 representative of the desired frequency, which word is successively added to the contents of the accumulator under the control of the system clock to provide a periodically varying output value having the form of a sawtooth wave. The output value is converted by means of a ROM 6 to digital values representing a desired waveform, e.g. triangular, sine, square, which digital values are applied to a Digital to Analog converter 8 which provides an analog waveform at its output.
Figure 2 shows a modification of the known synthesiser of
Figure 1 and forms the subject of our copending application < (F20778). Similar parts are indicated by similar reference numerals.
The output of accumulator 2 is output via gate system 10 which provides an equal-sided triangular waveform to first and second integrators 12, 14 which are equivalent to low pass filters in order to generate an output sine waveform.
In both the known systems of Figure 1 and the system of
Figure 2 forming the subject of our copending application < (F20778) there may be a need for further filtering to produce a more pure waveform. More specifically, there may be a sign:ficant amount of spurious radiation at frequencies harmonically related to the clock frequency of the synthesiser. It is an object of the invention to overcome this problem.
The present invention provides a direct frequency synthesiser comprising an accumulator having an input for receiving a digital word representative of the desired frequency, clock means for controlling the successive adding of the digital word to the contents of the accumulator to provide a periodically varying value at the output of the accumulator, means for providing from said periodically varying value, values representing a waveform of desired shape, digital to analog conversion means (DAC) for providing .said waveform in analog form, and a clock-operated filter means coupled to the input or the output of the DAC having means for deriving a clock signal from the waveform at the input/output of the filter means, which clock signal is employed to enable operation of the filter means.
Thus in accordance with the invention, a clock-operated filter means is provided to further filter the output waveform of the synthesiser. The filter may either be coupled to the input of the DAC, in which case the filter will be a digital filter of any type, or it may be coupled to the output of the DAC, in which case it will be a clockoperated analog filter, for example a switched capacitor type. In any event, the clock signal for operating the filter is derived from the filter input signal by providing a frequency multiplication device for generating a higher harmonic of the input waveform. The advantage is that such a clock signal will in general be different from the system clock frequency and thus the filtering effect will be operative against spurious radiation created by the system clock and will not have "blind-spots" at harmonics of the system clock frequency.
It would in principle be possible for the clock-operated filter means to perform whole or part of the function of the waveform providing means.
A preferred embodiment of the invention will now be described with reference to the accompanying drawings, wherein:
Figure 1 is a block diagram of a known frequency synthesiser;
Figure 2 is a block diagram of a frequency synthesiser according to our copending application < > (F20778);
Figure 3 is a first embodiment of a clock operated filter to be used in accordance with the invention;
Figure 4 is a second embodiment of a clock operated filter to be used in accordance with the invention;
Figure 5 is a third embodiment of a clock operated filter to be used in accordance with the invention; and,
Figure 6 is a fourth embodiment of a clock operated filter to be used in accordance with the invention.
Referring now to the drawings, the simplest variant proposed here is to add analogue filtering after the DAC 8. This is shown diagrammatically in figure 3. The nominally sinewave output from the DAC 8, including some spurious frequencies, is passed into two circuits, one circuit 20 of which squares it up and frequency multiplies to some small factor times the input, minimally two, but preferably eight or sixteen. This frequency is used to drive the clock input of an analogue filter 22, a switched capacitor type, preferably of the type known as a "commutating" or "N-path" filter. This class of filter has a capability for operation at relatively high frequencies and can have very high Q and very narrow passband.They have the disadvantage of some clock related breakthrough on the output frequency, but in this case, such a signal is of no real consequence since it is at the desired output frequency or a harmonic of it. More important will be the suppression of the off-frequency spurious lines.
This should be very substantial, and will depend in each case on the parameters chosen.
A further improvement of the scheme is shown in figure 4.
Since it is generally undesirable to use a clock containing jitter in the filter, the squarer/multiplier 20 is fed from the filter 22 output (referred to as "recursion"). It is necessary to provide a filter which will pass some signal to the output in the absence of a clock. This leads to an overall lower spurious level than figure 3.
Both the circuits of figure 3 and 4 could be realised in digital form prior to the DAC (figures 5 and 6). The filters 24 and digital squarers and frequency multipliers 26 will be of conventional digital form and several types could be used. Again, feedback from the system output to the clock could be used as shown in figure 6.
Claims (6)
1. A direct frequency synthesiser comprising an accumulator having an input for receiving a digital word representative of the desired frequency, clock means for controlling the successive adding of the digital word to the contents of the accumulator to provide a periodically varying value at the output of the accumulator, means for providing from said periodically varying value, values representing a waveform of desired shape, digital to analog conversion means (DAC) for providing said waveform in analog form, and a clock-operated filter means coupled to the input or the output of the DAC having means for deriving a clock signal from the waveform at the input/output of the filter means, which clock signal is employed to enable operation of the filter means.
2. A synthesiser as claimed in claim 1 wherein the clock-operated filter means comprises a clock operated analog filter of the switched capacitor type coupled to the output of the DAC.
3. A synthesiser as claimed in claim 1 wherein the clock-operated filter means is a digital filter coupled to the input of the DAC.
4. A synthesiser as claimed in claim 1 wherein the clock signal deriving means comprises a squarer/frequency multiplier in digital or analog form.
5. A synthesiser as claimed in claim 1 wherein the clock signal deriving means is coupled to receive the output signal from the clock-operated filter means.
6. Frequency synthesisers as claimed in claim 1 and substantially as described with reference to the accompanying drawings.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9000317A GB2239748B (en) | 1990-01-06 | 1990-01-06 | Direct frequency synthesiser |
GB9311017A GB2265511B (en) | 1990-01-06 | 1993-05-28 | Direct frequency synthesiser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9000317A GB2239748B (en) | 1990-01-06 | 1990-01-06 | Direct frequency synthesiser |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9000317D0 GB9000317D0 (en) | 1990-03-07 |
GB2239748A true GB2239748A (en) | 1991-07-10 |
GB2239748B GB2239748B (en) | 1993-12-15 |
Family
ID=10668938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9000317A Expired - Fee Related GB2239748B (en) | 1990-01-06 | 1990-01-06 | Direct frequency synthesiser |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2239748B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0624954A1 (en) * | 1993-05-12 | 1994-11-17 | Alcatel Telspace | Arrangement for reducing the spurious spectral lines contained in a digital frequency synthesizer output signal |
US5469479A (en) * | 1992-02-27 | 1995-11-21 | Texas Instruments Incorporated | Digital chirp synthesizer |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2217127A (en) * | 1988-04-07 | 1989-10-18 | Plessey Co Plc | Direct frequency synthesiser |
-
1990
- 1990-01-06 GB GB9000317A patent/GB2239748B/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2217127A (en) * | 1988-04-07 | 1989-10-18 | Plessey Co Plc | Direct frequency synthesiser |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5469479A (en) * | 1992-02-27 | 1995-11-21 | Texas Instruments Incorporated | Digital chirp synthesizer |
EP0624954A1 (en) * | 1993-05-12 | 1994-11-17 | Alcatel Telspace | Arrangement for reducing the spurious spectral lines contained in a digital frequency synthesizer output signal |
FR2705175A1 (en) * | 1993-05-12 | 1994-11-18 | Alcatel Telspace | Device for reducing the parasitic lines of the output signal of a digital frequency synthesizer. |
Also Published As
Publication number | Publication date |
---|---|
GB2239748B (en) | 1993-12-15 |
GB9000317D0 (en) | 1990-03-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
730A | Proceeding under section 30 patents act 1977 | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20040106 |