GB2236922A - Frequency synthesisers - Google Patents

Abstract

A frequency synthesiser includes a first divider 12 which divides the oscillations of a reference oscillator 10 and whose output is compared with that of a second divider 16 which divides the oscillations from a VCO 14. A dc voltage is produced by a differential phase detector 18 which varies in accordance with the rate of change of the phase difference between the outputs of the dividers 12, 16. At predetermined intervals, a high proportion of the circuitry, in particular the second divider 16, is switched off by a power control circuit 22 in order to effect a substantial power saving, and during these time intervals. the VCO 14 is allowed to free run with its control voltage being stored in an analogue storage device 20. A register 24 stores the moduli for the variable dividers 12, 16 in order to generate the required frequency. The divider 16 is reset in response to the zero-crossing in one direction of the output of divider 12. <IMAGE>

Description

FREQUENCY SYNTHESISERS This invention relates to frequency synthesisers which may be used to set stable oscillation frequencies, for example, in radio receivers.

It is known to use crystal controlled oscillators in locked oscillator mode to derive the required injection signals for the frequency mixers in radio receivers. In this type of arrangement, signals from a reference oscillator and from a voltage controlled oscillator (VCO), which may be frequency divided as required, are fed to a comparator. The frequency or phase difference produces a dc output which is used to control the VCO, typically by biasing a voltage controlled diode in the VCO until the two signals are synchronized and then phase locked. This approach has limitations in respect of switch off/recovery time, high power requirements and adjacent channel noise.

Also, in certain applications, there is a requirement for controlled oscillators to provide a number of different frequencies, so as to cover a number of transmission channels. One such application arises in the radiopaging field, in which it is being proposed to provide radiopaging receivers capable of scanning a number of frequencies. Providing a different oscillator crystal for each frequency would be very expensive, and thus a suitable frequency synthesising technique would be advantageous. However, most existing frequency synthesisers have relatively high power consumption, which renders them unsuitable for use in radiopaging receivers, in which power economy considerations are paramount.

According to the present invention there is provided a frequency synthesiser comprising: a reference oscillator; first dividing means for dividing oscillations from the reference oscillator to provide a first divided signal; a voltage controlled oscillator having its frequency controllable by a control signal; second dividing means for dividing oscillations from the voltage controlled oscillator; and means for detecting the rate of change of phase difference between the first and second divided signals to provide the control signal for the voltage controlled oscillator.

A preferred embodiment of this invention, to be described in greater detail hereinafter, provides a frequency synthesiser which overcomes the above problems by providing means for minimising the power consumption by switching off a large part of the circuitry for a high percentage of the time, and by using a differential phase locking technique instead of the traditional phase locked loop.

The preferred frequency synthesiser includes a first divider to divide the oscillations from a frequency reference source by a predetermined number. Also included is a second divider used to divide the oscillations from a VCO. A phase detector is used to measure the phase difference between the two divided signals. The absolute value of this phase difference is ignored but the change between two successive readings of phase difference is used to update an analogue voltage storage device such as a capacitor which, in turn, provides the control voltage for the VCO.

The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure 1 is a diagram of a frequency synthesiser in accordance with an embodiment of the invention; and Figure 2 is a timing diagram showing the operation of the frequency synthesiser of Figure 1.

Referring to Figure 1, the frequency synthesiser includes a reference oscillator 10 which may, for example, be a 32768 Hz CMOS clock oscillator connected to feed its oscillation output to a first divider 12. A voltage controlled oscillator (VCO) 14 is connected to a second divider 16. The second divider 16 may take various forms, but the most convenient may include a dual modulus divider followed by main and auxiliary counters as used in many well-known phase locked loop synthesiser circuits. The first divider 12 is most likely to be a simple binary counter circuit but may be more complex if required.

Both the dividers 12, 16 may be programmed via a register 24, if required. A differential phase detector 18 compares the time difference between the zero crossings of each divider output. If two successive time differences are unequal, the synthesiser is not locked and the VCO control voltage is updated by a change in voltage which is proportional to the change in time difference. The differential phase detector 18 may comprise an exclusive-OR circuit receiving the two divider outputs and an integrator arranged to integrate the output of the exclusive-OR circuit. The output of the integrator is then a DC voltage which is proportional to the time difference. This DC voltage is applied to an analogue store 20, which may simply be a capacitor, the output of which is connected to the control input of the VCO 14.

The output of the VCO 14, as well as being applied to the input of the second divider 16, provides the output of the frequency synthesiser at an output terminal 26. A power control circuit 22 controls the supply of power to the first and second dividers 12, 16.

The operation of the circuit shown in Figure 1 will now be described, initially without making reference to the power control circuit 22, and assuming that the data input register 24 is producing a constant output for the two dividers 12, 16.

The first divider 12 divides the reference frequency by a predetermined integer m, while the second divider 16 divides the VCO frequency by another predetermined integer n. The output frequencies of the two dividers 12, 16 will be equal when the synthesiser is locked. In this illustrative example, a positive zero crossing at the output of the first divider 12 resets the second divider 16, which then produces a positive zero crossing itself after a short period of time, set to within predetermined limits. The succeeding negative zero crossings of both the divider outputs are then used to determine the magnitude and sign of the frequency error. Figure 2 is a timing diagram which illustrates the locked and unlocked states of the synthesiser. A time t1 is set by the first divider 12, this being one half of a period of the divided frequency.If the frequency of the reference oscillator is f(REF), then tl=m/(2.f(REF)). The second divider 16 sets a time t2 which is similarly defined. If the frequency of the VCO 14 is f(VCO), then t2=n/(2.f(VCO)). When t1=t2 the synthesiser is locked and produces a VCO frequency given by the equation: f(VCO) = f(REF) . n m In the unlocked state when t1 is not equal to t2, the frequency is given by: f(VCO) = f(REF) . n . t1 m . t2 The error is therefore:: df(VCO) = f(REF) . n ~ f(REF) . n . t1 m m . t2 = f(REF) . n . (1 - t1/t2) m = f(REF) . n . (dt2 - dot1) m (tl + dt2 - dtl) where dtl is the time difference between the positive zero crossings of the dividers and dt2 is the time difference between the negative zero crossings. To a close approximation, therefore, the frequency error, df(VCO), is proportional to the difference between the two periods of time, dt2 and dtl, assuming that t1 is much greater than dt1 and dt2.

In this illustrative example, an "exclusive or" operation is performed on the divider outputs, followed by an integration to provide a de output voltage which is proportional to dt2 - dtl. This output is then filtered and amplified as required and applied to the control input of the VCO 74 via the analogue store 20.

The delay time dtl between the positive zero crossing of the first divider 12 and reset of the second divider 16 causing a positive zero crossing therein is dependent on the architecture of the second divider 16 and also the necessity to wait for a zero crossing of the VCO frequency which should coincide with the start of the time t2.

The operation of the power control circuit 22 will now be described, again with reference to Figure 2. Once the control voltage at the control input of the VCO 14 has been updated in the manner described above, it is possible to shut down the power to a large part of the circuitry for a predetermined time interval t3. This is done by the power control circuit 22 and is especially important for the second divider 16 which is normally a device with high power consumption.

During the interval t3, the control input to the VCO 14 is held by the analogue store 20, and the VCO 14 is allowed to free run until the next control voltage update. At the end of the time interval t3, the entire cycle is then repeated.

A significant advantage of the circuit as described is that, as long as the VCO control voltage is held in the analogue store 20, if power to the rest of the circuit, including the VCO 14, is discontinued and subsequently re-applied, the locking time is minimised, since the VCO control voltage is immediately available. This feature is particularly useful in applications such as receivers in radiopaging systems in which it is desirable for the major power consuming components to be switched off during periods when the desired transmissions are not being received.

The choice of actual values for the time intervals tl and t3 will now be discussed. Constraints on the time interval tl are frequency stability, lock time and power consumption. For optimisation of lock time and power consumption, tl must be made as short as possible.

However, the delay characteristics of the logic circuitry being used and the quality of the reference signal will place an effective minimum on tl. Lock time will be proportional to tl + t3 and related also to the VCO characteristic, filtering, and the required frequency change.

The time interval t3 can be made very short if a fast lock time is required, but this makes an impact on power consumption. It is therefore preferable to retain as high a value of the time interval t3 as possible under constant frequency conditions, and reduce its value when a fast frequency change is required. The minimum value of the time interval t1 will in general have been defined by the frequency stability required and will therefore place a limitation on the minimum lock time.

Mean power consumption is given by: p = p1 . t1 + p3 . t3 W + + t3 where pl and p3 are the respective power consumptions during the time intervals t1 and t3.

As the power consumption pl includes that of the second divider 16 operating at a high clock rate, it will be much higher than the power consumption p3. Thus, it can be seen that for minimum power consumption, the value of t1/t3 should be minimised. The free-running drift characteristics of the VCO 14 impose a maximum limit on the value of t3.

Another advantage of the circuit as described is that, under constant frequency conditions, the output frequency signal at the output terminal 26 has very low noise. This is significantly better than traditional phase locked loop circuits, which often suffer from poor noise performance, especially on adjacent channels.

If it is desired to extend the frequency coverage, it is possible to include frequency mixers, dividers and/or multipliers inside and/or outside the control loop, in a similar manner to that effected in traditional phase locked loop synthesisers.

As described above, the frequency synthesiser shown in Figure 1 generates a single frequency, according to the programmed moduli of the first and second dividers 12, 16 as requested by the register 24.

However, if the synthesiser is to generate more than one frequency, the register 24 may receive suitable "data in" signals at its control input, whereby the moduli supplied by the register 24 will depend on which frequency has been selected by the "data in" signals. Also, predetermined correction data, to compensate for reference oscillator frequency/temperature characteristics, can additionally (or alternatively) be held in the register 24 In the preferred embodiment as described above, since the phase detector is arranged effectively to measure rate of change of phase rather than absolute phase as in some previously-proposed arrangements, it may be said that the reference and VCO signals are never in fact phase locked but only frequency locked. This means that the lower limit on sample length is defined by the device technology used and very high battery economy ratios (ratio of power on to power off times), for example 1:1,000, are attainable.

Claims (9)

1. A frequency synthesiser comprising: a reference oscillator; first dividing means for dividing oscillations from the reference oscillator to provide a first divided signal; a voltage controlled oscillator having its frequency controllable by a control signal; second dividing means for dividing oscillations from the voltage controlled oscillator; and means for detecting the rate of change of phase difference between the first and second divided signals to provide the control signal for the voltage controlled oscillator.

2. A frequency synthesiser according to claim 1, wherein the second dividing means includes a reset function responsive to a zero-crossing in one direction of the first dividing means which is operable to reset the second dividing means.

3. A frequency synthesiser according to claim 2, wherein the reset function is operable to reset the second dividing means after a predetermined delay.

4. A frequency synthesiser according to claim 1, claim 2 or claim 3, including an analogue store connected to the rate of change of phase difference detecting means for holding the control signal.

5. A frequency synthesiser according to claim 4, wherein the analogue store comprises a capacitive arrangement.

6. A frequency synthesiser according to claim 4 or claim 5, including means for switching off power to at least the second dividing means during a predetermined time interval.

7. A frequency synthesiser according to any one of the preceding claims, including a register for supplying a modulus to the first and/or second dividing means to set the dividing factor thereof.

8. A frequency synthesiser according to any one of the preceding claims, wherein the rate of change of phase difference detecting means comprises means for performing an "exclusive or" operation on the first and second divided signals, and means for integrating the signal from the "exclusive or" operation to provide an output signal whose magnitude is proportional to the rate of change of the phase difference between the first and second divided signals.

9. A frequency synthesiser substantially as hereinbefore described with reference to the accompanying drawings.