GB2220102A - "Method of making a bipolar transistor" - Google Patents
"Method of making a bipolar transistor" Download PDFInfo
- Publication number
- GB2220102A GB2220102A GB8913801A GB8913801A GB2220102A GB 2220102 A GB2220102 A GB 2220102A GB 8913801 A GB8913801 A GB 8913801A GB 8913801 A GB8913801 A GB 8913801A GB 2220102 A GB2220102 A GB 2220102A
- Authority
- GB
- United Kingdom
- Prior art keywords
- insulation film
- region
- bipolar transistor
- substrate
- aligned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009413 insulation Methods 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000010276 construction Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The bipolar transistor, comprising a substrate (101) having a base region (104) and an emitter region (105) which are respectively electrically connected to first (106) and second (109) conductive or semi-conductive wiring material, is made by a method comprising forming the first wiring material (106) in electrical connection with the base region (104) removing a portion of the first wiring material (106) in a region aligned with the emitter region (105) of the substrate (101); forming an annular insulation film (108) in said aligned region and thereafter forming the second wiring material (109) radially inwardly of the annular insulation film (108) so as to be in electrical connection with the emitter region (105), the annular insulation film (108) electrically insulating the first and second wiring materials from each other. <IMAGE>
Description
"METHOD OF MAKING A BIPOLAR TRANSISTOR"
The present invention relates to a method of making a bipolar transistor and to a semiconductor device with bipolar transistors integrated at a part of or the entire region of a substrate.
The construction of a prior bipolar transistor is shown in the accompanying Figure 2. The transistor of
Figure 2 comprises a substrate 201 which is provided with a collector 202, a base 204 and an emitter 205.
The base 204 and the collector 202 are directly connected to respective electrodes constituted by metal wiring members 210, while the emitter 205 is connected to its electrode 210 by way of polycrystalline silicon material 209. The transistor is provided with insulation films 207, 200 and with a device isolation area 203.
In order to both enhance the speed of a transistor and improve the current amplification factor, it is necessary to shorten the travel time of the carriers within the base by lowering the impurity concentration of the base or by reducing the base length. Such a change in the construction, however, increases the base resistance, so that an improvement of the performance can hardly be expected. In particular, in the construction of the prior bipolar transistor shown in
Figure 2 in which there is a considerable distance between the metal electrode 210 of the base 204 and the emitter 205, this disadvantage is very marked.
According to#the present invention, there is therefore provided a method of making a bipolar transistor comprising a substrate having a base region and an emitter region which are respectively electrically connected to first and second conductive or semi-conductive material, the said method comprising forming the said first material in electrical connection with the base region of the substrate; removing a portion of the said first material in a region aligned with the emitter region of the substrate; forming an annular insulation film in said aligned region; and thereafter forming the said second material radially inwardly of the annular insulation film so as to be in electrical connection with the emitter region, the annular insulation film electrically isolating the said first and second materials from each other.
The first material may be a metal silicide, and the metal thereof may be W, Mo,Ti or Ta.
Preferably, after the formation of the first material, a first insulation film is formed thereon; a portion of both the first material and the first insulation film is removed in the said aligned region; a second insulation film is formed on the first insulation film so as to fill the aligned region; and a central portion of the second insulation film in the aligned region is removed so as to form the annular insulation film.
Preferably, the annular insulation film is a side wall insulator which has been produced by dry etching without mask of the second insulation film.
Preferably, the second insulation film is completely removed except in the part thereof which forms the annular insulation film.
The invention also comprises a bipolar transistor when made by the method set forth above.
The present invention enables the base resistance to be reduced and the performance of the transistor to be improved.
The invention is illustrated, merely by way of example, in the accompanying drawings, in which:
Figure 1 is a sectional view of a first embodiment of a bipolar transistor in accordance with the present invention;
Figure 2 is a sectional view of a prior bipolar transistor;
Figures 3(A), 3(B) and 3(C) are sectional views of successive stages in the formation of the bipolar transistor of Figure 1;
Figure 4 is a sectional view of a second embodiment of a bipolar transistor in accordance with the present invention; and
Figures 5(A), 5(B) and 5(C) are sectional views of successive stages in the formation of the embodiment shown in Figure 4.
The construction of a first embodiment of a bipolar transistor in accordance with the present invention will now be explained with reference to Figure 1. A first wiring material layer 106 composed of a semiconductor material is brought into direct electrical contact with a base 104 of a substrate 101 and extends to the vicinity of an emitter 105 of the substrate 101.
The transistor is provided with a collector 102, a device isolation area 103, and electrodes or terminals 110. A second wiring material layer 109 composed of a semiconductor material is directly electrically connected to the emitter 105. The first wiring material layer 106 and the second wiring material layer 109 are isolated from each other by a first insulation film 107 and by an annular insulation film 108, the insulation film 108 being a side wall film, i.e. being provided on the side wall of the second wiring material layer 109.
The manufacturing process employed to produce a bipolar transistor in accordance with the present invention will now be explained with reference to Figure 3.
In Figure 3, only the elements essential for explaining the present invention are shown and a collector, an epitaxial layer etc. are omitted. As shown in Figure 3(A), after a device isolation area 302 is formed on a substrate 301, a base region 303 is formed.
Thereafter, a first wiring material layer 304 of a semiconductor material and a first insulation film 305 are provided over the entire surface of the substrate 301.
Next, a portion of the first wiring material layer 304 and of the first insulation film 305 in a region 309 which is aligned with what is to be an emitter region 308 are removed by photolithography and etching, and a second insulation film 306 is provided over the entire surface of the first insulation film 305 as shown in
Figure 3(B), the second insulation film 306 filling the aligned region 309. The whole of the second insulation film 306 outside the aligned region 309, together with the part of the second insulation film 306 which is disposed in a central portion of the aligned region 309 is next etched away completely by dry etching without a mask so as to form an annular side wall film 307, as shown in Figure 3(C).Impurities for an emitter 308 are then implanted in the substrate 301 and a second wiring material 109 (Figure 1) is provided over the entire surface, and thereafter a further or outer insulation film 100. The process thereafter is the same as that usually used for manufacturing bipolar transistors.
Thus, the construction shown in Figure 1 is achieved.
A second embodiment of the present invention is shown in Figure 4, which is a sectional view. In the said second embodiment, a metal silicide layer 410 is provided on a base 409 formed in a substrate 401. A first insulation film 406 and an annular side wall insulation film 407 are used for isolating the metal silicide layer 410 and a semiconductor material 411 from each other. A collector 402, a device isolation area 403, metal wirings or electrode terminals 404, 412 and 413, and an outer insulation layer 405 have the same construction as in a known device and the present invention is not restricted to the particular form of these elements shown in Figure 4.
The manufacturing process for producing the embodiment shown in Figure 4 will be explained with reference to Figure 5.
In Figure 5, only. the elements essential for explaining the present invention are shown. A device isolation area 502 and a base 503 are first formed in a substrate 501. Thereafter, the entire surface is covered with a metal layer 504. By annealing, a portion 505 of the metal layer 504 is reacted with silicon in the underlayer, thereby becoming a metal silicide, the metal silicide portion 505 being formed over the base 503 and over a region 501 aligned with an emitter region (not shown in Figure 5 but corresponding to the emitter 408 of Figure 4). Only the metal of the layer 504 which has not been turned into a metal silicide is etched by an appropriate solution while leaving the metal silicide portion 505. A first insulation film 506 is next provided over the entire surface, and a portion of the first insulation film 506, together with the part of the metal silicide portion 505 in the region 110, is removed by photolithography and etching. Thereafter, a second insulation film 507 is provided over the entire surface of the first insulation film 506 as shown in Figure 5(B) so as to fill the region 510.
By etching away other parts of the second insulation film 507, a portion thereof, which forms an annular side wall portion 509, is formed in the region 510, as shown in Figure 5(C).
Through processes such as the formation of an emitter 408 and an emitter electrode 412 and wiring thereafter by ordinary methods, the construction shown in Figure 4 is obtained. The metal layer 504 for obtaining a metal silicide, may for example, be a Ti, W,
Mo or Ta layer. As a solvent for etching only the metal of the layer 504 while leaving the metal silicide, a mixed solution of ammonia and hydrogen peroxide, for example, is suitable.
As is clear from Figure 1, since it is possible to bring the first wiring material layer 106 as close to the emitter 105 as possible, the base resistance is lowered to a considerable extent. It is therefore easy to lower the base concentration and reduce the base length, thereby enhancing the performance. In addition, since it is possible to control the width of the side wall film 108 by controlling the thickness of the film 306 shown in Figure 3(B), the said width can be freely selected in accordance with the sideways spread of the diffusion layer.
In the construction shown in Figure 4, since the resistance of a metal silicide is much lower than the impurity diffusion resistance of a conventional base, it is possible to greatly reduce the base resistance.
Furthermore, since it is possible to reduce the distance between the metal silicide layer 410 and the emitter 408 to a greater extent than the distance between the electrode 210 and the emitter 205 shown in Figure 2, the base resistance is further reduced. In addition, since it is possible to control the distance between the metal silicide and the emitter by controlling the thickness of the insulation film 507 shown in Figure 5, the optimum distance between the metal silicide layer 410 and the emitter 408 can be set to take account of the sideways spread of the emitter diffusion layer 408.
Thus, the present invention enables a transistor to be produced which is capable of reducing the base resistance and has a high speed and a high current amplification factor.
Claims (10)
1. A method of making a bipolar transistor comprising a substrate having a base region and an emitter region which are respectively electrically connected to first and second conductive or semiconductive material, the said method comprising forming the said first material in electrical connection with the base region of the substrate; removing a portion of the said first material in a region aligned with the emitter region of the substrate; forming an annular insulation film in said aligned region; and thereafter forming the said second material radially inwardly of the annular insulation film so as to be in electrical connection with the emitter region, the annular insulation film electrically isolating the said first and second materials from each other.
2. A method as claimed in claim 1 in which the first material is a metal silicide.
3. A method as claimed in claim 2 in which the metal of the metal silicide is W, Mo, Ti or Ta.
4. A method as claimed in any preceding claim in which, after the formation of the first material, a first insulation film is formed thereon; a portion of both the first material and the first insulation film is removed in the said aligned region; a second insulation film is formed on the first insulation film so as to fill the aligned region; and a central portion of the second insulation film in the aligned region is removed so as to form the annular insulation film.
5. A method as claimed in claim 4 in which the annular insulation film is a side wall insulator which has been produced by dry etching without mask of the second insulation film.
6. A method as claimed in claim 4 or 5 in which the second insulation film is completely removed except in the part thereof which forms the annular insulation film,
7. A method of making a bipolar transistor substantially as hereinbefore described with reference to Figures 1 and 3-5 of the accompanying drawings.
8. A bipolar transistor when made by the method of any preceding claim.
9. Any novel integer or step, or combination of integers or steps, hereinbefore described and/or as shown in the accompanying drawings, irrespective of whether the present claim is within the scope of, or relates to the same or a different invention from that of, the preceding claims.
10. A semiconductor device composed of bipolar transistors provided at a part of or the entire region of a substrate comprising:
a first wiring material consisting of a semiconductor material or a metal silicide which is electrically connected directly to the portion above a diffusion layer in a part of the base region of said bipolar transistor;
a second wiring material consisting of a semiconductor material which is electrically connected directly to the emitter region of said bipolar transistor; and
a first insulator, a part of or all of which is directly on a said first wiring material, and a side wall insulator produced by dry-etching-without-mask of a second insulator deposited on said substrate, in order to electrically isolate between a first and a second wiring materials.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15879888A JPH027527A (en) | 1988-06-27 | 1988-06-27 | Transistor |
| JP15879988A JPH027528A (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8913801D0 GB8913801D0 (en) | 1989-08-02 |
| GB2220102A true GB2220102A (en) | 1989-12-28 |
| GB2220102B GB2220102B (en) | 1992-01-29 |
Family
ID=26485805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8913801A Expired - Fee Related GB2220102B (en) | 1988-06-27 | 1989-06-15 | Method of making a bipolar transistor |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR900001034A (en) |
| GB (1) | GB2220102B (en) |
| HK (1) | HK41194A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2081507A (en) * | 1980-08-04 | 1982-02-17 | Fairchild Camera Instr Co | High speed bipolar transistor and method of making same |
| EP0071010A2 (en) * | 1981-07-27 | 1983-02-09 | International Business Machines Corporation | Method for planarizing an integrated circuit structure |
| EP0096155A2 (en) * | 1982-06-07 | 1983-12-21 | International Business Machines Corporation | Transistor having emitter self-aligned with an extrinsic base contact and method of making it |
| EP0107416A2 (en) * | 1982-09-30 | 1984-05-02 | Fujitsu Limited | Method of producing semiconductor device |
| EP0109766A1 (en) * | 1982-10-22 | 1984-05-30 | Fujitsu Limited | Semiconductor device with a passivated junction |
| EP0170250A2 (en) * | 1984-07-31 | 1986-02-05 | Kabushiki Kaisha Toshiba | Bipolar transistor and method for producing the bipolar transistor |
| EP0189486A1 (en) * | 1984-08-10 | 1986-08-06 | Hitachi, Ltd. | Method of producing bipolar semiconductor devices |
| EP0231740A2 (en) * | 1986-01-30 | 1987-08-12 | Texas Instruments Incorporated | A polysilicon self-aligned bipolar device and process of manufacturing same |
| EP0252206A2 (en) * | 1986-07-09 | 1988-01-13 | Hitachi, Ltd. | Method of fabricating semiconductor structure |
| GB2209872A (en) * | 1987-09-16 | 1989-05-24 | Oki Electric Ind Co Ltd | A method for fabricating a bipolar transistor |
-
1989
- 1989-05-15 KR KR1019890006455A patent/KR900001034A/en not_active Application Discontinuation
- 1989-06-15 GB GB8913801A patent/GB2220102B/en not_active Expired - Fee Related
-
1994
- 1994-04-28 HK HK41194A patent/HK41194A/en not_active IP Right Cessation
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2081507A (en) * | 1980-08-04 | 1982-02-17 | Fairchild Camera Instr Co | High speed bipolar transistor and method of making same |
| EP0071010A2 (en) * | 1981-07-27 | 1983-02-09 | International Business Machines Corporation | Method for planarizing an integrated circuit structure |
| EP0096155A2 (en) * | 1982-06-07 | 1983-12-21 | International Business Machines Corporation | Transistor having emitter self-aligned with an extrinsic base contact and method of making it |
| EP0107416A2 (en) * | 1982-09-30 | 1984-05-02 | Fujitsu Limited | Method of producing semiconductor device |
| EP0109766A1 (en) * | 1982-10-22 | 1984-05-30 | Fujitsu Limited | Semiconductor device with a passivated junction |
| EP0170250A2 (en) * | 1984-07-31 | 1986-02-05 | Kabushiki Kaisha Toshiba | Bipolar transistor and method for producing the bipolar transistor |
| EP0189486A1 (en) * | 1984-08-10 | 1986-08-06 | Hitachi, Ltd. | Method of producing bipolar semiconductor devices |
| EP0231740A2 (en) * | 1986-01-30 | 1987-08-12 | Texas Instruments Incorporated | A polysilicon self-aligned bipolar device and process of manufacturing same |
| EP0252206A2 (en) * | 1986-07-09 | 1988-01-13 | Hitachi, Ltd. | Method of fabricating semiconductor structure |
| GB2209872A (en) * | 1987-09-16 | 1989-05-24 | Oki Electric Ind Co Ltd | A method for fabricating a bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2220102B (en) | 1992-01-29 |
| HK41194A (en) | 1994-05-06 |
| GB8913801D0 (en) | 1989-08-02 |
| KR900001034A (en) | 1990-01-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20070615 |