GB2215544A

GB2215544A - Apparatus for the correction of frequency independent errors in quadrature zero I.F. radio architectures

Info

Publication number: GB2215544A
Application number: GB8805748A
Authority: GB
Inventors: Andrew Philip Cheer; Alexander Brian Barber
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-03-10
Filing date: 1988-03-10
Publication date: 1989-09-20
Anticipated expiration: 2008-03-10
Also published as: GB8805748D0; GB2215544B

Abstract

The apparatus comprises a DC correction stage, a phase correction stage and an amplitude correction stage. Each stage uses comparator fed integrator feedback loops to modify the signal received in the channels. The feedback loops give accurate and efficient correction. The apparatus forms part of a demodulator of the digital signal processors used in such radio architectures. <IMAGE>

Description

APPARATUS FOR THE CORRECTION OF FREQL#NCY INT)EPENT?EN'W ERRORS IN QUADRATURE ZERO I.F. RADIO ARCSTECIURES The present invention relates to apparatus for the correction of frequency independent errors in quadrature zero I.F. radio architectures using digital signal processing (DSP).

A typical zero I.F. (direct conversion) receiver structure is shown in Figure 1. Quadrature baseband signal channels are derived from the RF input IP using a splitter S and two analogue mixers M1, M2 driven by quadrature local oscillators LO. The baseband signals (I & Q) are then low pass filtered by filters LPFI and LPF2 analogueto-digital (AID) converted by converters AIDS, A/D2 and digitally filtered by the DSP circuits comprising channel filters 1 and Q and a demodulator D, to provide the final bandwidth before demodulation.

Three sources of error result from the analogue mixing process.

These are: DC offsets at the output of the mixers, Phase errors due to a non-ideal quadrature local oscillator, and Amplitude errors due to any imbalance between the two mixers. This is depicted in vector form in Figure 2 with DC (1 & Q), phase and amplitude errors of a,b,t, and 8 respectively. A basic method of correction is shown in Figure 3, where W 1 and W2 represent weighting functions whose magnitudes are calclulated from statistical properties of the input signals to correct for any error.

UK patent application GB2150719A discloses a Hilbert transform correction system and a method for calculating the weights W1 and W2. The method is relatively computationally complex and is therefore unsuitable for digital filter integration.

An object of the present invention is to provide a minimal code error correction algorithm for execution by apparatus within the demodulator of digital signal processors.

According to the present invention there is provided apparatus for the correction of frequency independent errors in quadrature zero I.F. radio architectuees, wherein the apparatus comprises a DC correction stage arranged to receive and modify two channel input signals and output the signals to a phase correction stage arranged to modify and output the signals to an amplitude correction stage arranged to modify the signals and generate corrected output signals.

According to an aspect of the present invention each stage includes a comparator fed integrator feedback loop.

An embodiment of the present invention will now be described with reference to the accompanying drawings in which: Figure 1 shows a block diagram a typical zero I.F. receiver structure, Figure 2 shows a vector error diagram, Figure 3 shows a basic correction system, Figure 4 shows a basic feedback section; and, Figure 5 shows a block diagram of a feedback correction system according to the present invention.

Figures 1, 2 and 3 have already been described in relation to the prior art and the problems or error associated therewith.

Referring to Figure 5, the correction system comprises three stages, a DC correction stage, Phase correction stage and an Amplitude correction stage. Each stage of correction incorporates a comparator fed integrator feedback loop as shown in Figure 4. The integrator feedback acts as a high pass filter (i.e. a DC rejector) while the comparator provides control of the effective filter time con#stant.

For an increased comparator step the loop time constant decreases and the effective filter breakpoint frequency increases.

The problem of correcting for phase and amplitude errors therefore reduces to the generation and removal of D.C. terms proportional to the error in each case. For phase correction a product detector is used while any long term difference between the I and Q vector magnitudes is used to correct for amplitude. The I and Q channel signals before correction are from figure 2.

I = a + (1+6) Acos (cot), Q = b + Asin (#t+#) DC rejection from both channels is directly implemented using the loops of Figure 4 giving I = (1+8) Acos (#t), Q = Asin (#t+#) The product of the two zero mean signals (II & Ql) gives I1.Ql = el = (1+6) Acos (cot). Asin (cot+) Expanding the expression el = (1+8) A2 [ cos (cot) sint + sin (owt) cos (cot) cos9)3 (l+8)A2 [ cos(2cot) + 1) sint + sin(2cot) cost) ] 2 This gives the DC term (1+6)A2 sint or ll+OA2 for small 9 2 2 Adding a small amount of the I channel signal to the Q channel provides a means of correcting for the phase error as shown in Figure 3.

Amplitude correction is applied to either channel in a similar manner (Figure 5) by integrating any magnitude difference and adding this to either channel. In the amplitude correction stage the absolute values AB & are used. If the value is negative it is multiplied by -1, and if positive it remains the same.

The feedback configuration of Figure 5 can be implemented very efficiently in digital signal processor code and the comparator step size adjusted to improve accuracy. The present invention gives very good results without reducing -channel filtering time unacceptably.

The present invention estimates the required weighting functions directly and efficiently using the incremental feedback structure to improve accuracy.

Claims

1. Apparatus for the correction of frequency independent errors in quadrature zero I.F. radio architectures wherein the apparatus comprises a DC correction stage arranged to receive and modify two channel input signals and output the signals to a phase correction stage arranged to modify and output the signals to an amplitude correction stage arranged to modify the signals and generate corrected output channel signals.

2. Apparatus as claimed in claim 1, wherein the DC correction stage comprises two comparator fed integrator feedback loops which receive and modify a respective input channel signal.

3. Apparatus as claimed in claim 2, wherein the integrator feedback in each loop acts as a high pass filter, and the comparator controls the filter time constant.

4. Apparatus as claimed in claim 3, wherein the phase correction stage comprises a comparator fed integrator feedback loop arranged to add an amount of the signal from one channel to the signal in the other channel to correct the signal phase.

5. Apparatus as claimed in claim 4, wherein the amplitude correction stage comprises a comparator fed integrator feedback loop arranged to integrate a magnitude difference in the signal of one channel and add the difference to the signal in the other channel to correct the signal amplitude.

6. Apparatus as claimed in claims 1 to 5, wherein the apparatus forms part of a demodulator located in digital signal processing circuits of an architecture shown in Figure 1 of the accompanying drawings.

7. Apparatus for the correction of frequency independent errors in quadrature zero I.F. radio architectures substantially as hereinbefore described.

8. Apparatus as hereinbefore described with reference to Figures 3, 4 and 5 of the accompanying drawings.