GB2213343A - Picture signal correcting circuits - Google Patents

Description

r) r 1 _ '. a --,,,- Z 1 6 I'D 4 J K1 331 2 0 1 PICTURE SIGNAL CORRECTING

CIRCUIT The present invention generally relates to picture signal correcting circuits for example for use in a television receiver or video tape recorder.

In a television receiver, a television signal received by a television antenna and selected in accordance with a desired channel television signal, is converted into a corresponding intermediate-frequency signal. This intermediatefrequency signal is detected in a video detecting circuit to derive therefrom a picture (video) signal. The picture signal is processed by a picture signal correcting circuit to expand the synchronizing (sync) signal thereo-f to increase the chrominance signal levell and to conduct other signal processing steps. As a result, the correct synchronization between the sync signal of the television signal received by the television receiver and the sync signal generated therein can be realized, and also care is taken not -ure on a cat to display a monochromatic pict hode-ray tube while receiving a colour television signal.

It is an object of the present invention to provide an improved picture signal correcting 4- to be desC circuit. With the circui. Iribed -ial hereinafter, the differential phase and different gain of the picture signal correcting circuit are improved and the circuit simplified.

According to the present invention there is provided a picture signal correcting circuit comprising a constant-K low-pass filter into which a picture signal is input and a frequency near an upper limit frequency of the picture signal is equal to a t - the cut-off frequency thereof; a trans_JSL1or circuit collector of which is grounded, an output signal derived from said low-pass filter is input into the K1 331 base thereof, and an output signal is derived from the emitter thereof: a first resistor one end of which is connected to a power supply and the other end of which is connected to one end of a capacitor; said capacitor one end of which is connected to said first resistor and the other end of which is connected to an output terminal; a second resistor connected between the emitter of said transistor and the output terminal; and, a diode a cathode of which is connected to the emitter of said transistor and an anode of which is connected to a junction between said first resistor and said capacitor, whereby a low imnedance load is connected to said output terminal.

The constant-K low-pass filter, the collector-grounded transistor circuit, the first resistor, the capacitor, the second resistor and, the diode are arranged in this order to form the sync signal expanding circuit. The low-pass filter is formed in such a manner that a Deak is lDresent near the chrominance signal --Frequency, since the transistor circuit functions as a high impedance load for the low-pass filter. An impedance matching effect can be achieved with the sync signal expanding circuit by the low output impedance of the transistor circuit. The sync signal is expanded by the input impedance RL connected to the output terminal and the sync signal ex-oanding circuit, thereby to correct the signal level of the picture signal.

A picture signal correcting circuit embodying the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which:

Figure I is a picture signall correcting circuit embodying the invention; and, Figure 2 is a previously proposed picture f?' K1 331 signal correcting circuit.

Figure 2 shows a previously proposed picture signal correcting circuit in which a sync signal expanding circuit 2 is so arranged that a bias voltage which is produced by dividing a power supply voltage by employing a resistor R,, a diode D, and a resistor l29 is applied to an input terminal 1. This input terminal 1 is connected to an emitter of a transistor Trl via a resistor R3. A capacitor Cl is connected between a junction of the resistor p, and diode D, and the emitter of the transistor Trj. The values of the capacitor Cl and the resistor R, are selected so that the time which is det const Germined by multiplying the ance capacitance of the capacitor Cl by the resist of the resistor R1, is sufficiently greater than the time period of the picture signal.

The picture signal fed into the sync signal expanding circuit 2 has a Pedestal levell set slightly higher than the bias voltage applied to the input terminal 1, and a signal level of the top uortion of the sync signal is adjusted to be lower than this bias voltage applied to the input terminal 1. As a consequence, when the picture signal is fed to the - the cathode side of input terminal 1, the voltage at the diode D is increased during the time period other than the sync signal period, and also is higher than the voltage at the anode side thereof which is kept constant by the resistor R, and capacitor Cl. The diode D thus becomes nonconductive. The picture signal is then fed via the resistor P3 to the emitter of the transistor Trj. During the time period of the sync signal, the voltage at the cathode side of the diode D is decreased, this diode D therefore now becomes conductive. Thus, the picture K1 331 4 - signal is supplied to the emitter of the transistor Tr, via an iMDedance circuit. This impedance circuit has a low impedance, and includes the series circuit of the diode D and capacitor Cl, and the parallel circuit of the resistor R 3 A load circuit 3 is formed by the transistor Trl, the base of which is grounded. This load circuit 3 functions as an emitter input type low impedance load for the sync signal expanding circuit 2. Accordingly, the signal level of the picture signal fed to the input terminal 1 is lowered during the time period other than the sync signal period by dividing this input picture signal by the input impedance of the resistor R3 and the sync signal expanding circuit 2. Since the input picture signal is supplied via the impedance circuit having a low impedance and formed by the diode D and capacitor Cl to this load circuit 3, the signal level thereof is substantially unaltered and supplied to the emitter of the transistor Tr-1. As aresult of the she s. -12' t h e above described operation, -1. Jgnal level oPicture signal fed to the iniDut terminal 1 is expanded during the sync signall period, as compared with that during the time period other than the sync signal period.

An impedance converting circuit A i.- formed by a transistor Tr2, and employed to match the high Output iMDedance of the load 3 with a low output impedance of a frequency characteristic correcting circuit 5.

The frequency characteristic correcting circuit 5 is mainly constructed of a constant-K filter formed by an inductor Ll and a capacitor C2, so as to cut off the Upper limit frequency of the picture signal. A load circuit 6 forming a high Q :i K1 331 - 5 input impedance/low output impedance circuit is formed by a transistor Tr3, and functions as a load for the frequency characteristic correcting circuit 5. As the high impedance load is connected -f to the constant-K low-pass filter, the chrominance signal is amplified by producing a peak within a pass band adjacent to the cut-off frequency of the lowpass filter,.ie, near the chrominance signal frequency. It should be noted that the resistor R4 connected parallel with the inductor 11 of the constant-K filter is a damper resistor for correcting the amplification of the chrominance signal.

Thus, the picture signal, the signal level of which has been corrected, is fed out from an output terminal 7.

The above-described previously proposed picture signal correcting circuit, requires three stages of the transistor circuits to provide the load circuit or impedance converting circuit. Accordingly, there is the drawback that a large number of circuit components are employed.

Another drawback of this picture signal correcting circuit is that since the picture signal must be passed through a large number of transistor circuits, the di-t'ferential phase and dif'-ferent.ial gain of the picture signal correcting circuit are reduced.

In Figure 1 parts similar to,those in Figure 2 are similarly referenced. The picture signal correcting circuit shown in Figure 1 has an input terminal 1, a frequency charateristic constant-K low-pass filter, a transistor circuit 8 having a high input impedance and a low output impedance, a sync signal expanding circuit 2, and an output terminal 7. An input impedance IL of the 6 - K1 331 succeeding stage is connected to the ouput terminal.

In the picture signal correcting circuit shown in Figure 1, the picture signal, the pedestal level of which is kept constant, is fed to the input terminal 1, the unwanted signal present outside the picture signal band is blocked by the frequency characteristic of the correcting circuit 5 and the high input impedance of the transistor circuit 8, and also the level of the chrominance signal frequency is increased and fed out from the emitter of the transistor Tr4.

A bias voltage which is slightly lower than the pedestal level of the video signal output from this emitter but higher than the signal level of the top portion of the sync signal is applied to the emitter of the transistor Tr,1, by the resistor R,, the diode D, and the resistor R2 that constitute the sync signal expanding circuit -9. As a result, the diode D becomes conductive during the sync signal Jgnal is fed out via the diode D and perLod, the s. capacitor Cl to the outDut terminal 7, for application to the load resistor R, substantially W without attenuation. During the time Deriod other than thel sync signal - period, the diode D becomes tive, and the pict nonconduct Ware signal is output via the resistor R 3 at the output terminal 7. This signal voltage is divided by the resistor P3 a load resistor RI, and then the divided signal voltage applied to the load resistor RT. Under the abovedescribed circuit operation, the sync signal contained in the picture signal input into the input terminal 1, is not substantially attentuated but the signal other than the sync signal is attenuated. Both of these signals are supplied to the load resistor RL so that the sync signal can be 1 j K1 331 7 - 1 expanded.

With the circuit described above, the frequency characteristic correcting circuit constructed of the constant-K low-pass filter is arranged on the input side, whereas the sync signal expanding circuit 2 is arranged at the output side. As a consequence, only a one-stage transistor circuit is employed for the load and the impedance conversion. The entire circuit is thus simplified, thereby reducing the total number of the circuit elements employed in this simplified circuit. Moreover, since only a single-stage transistor circuit is required in the picture signal correcting circuit, the deterioration of the signal differential phase and also the differential gain occurring in this transistor circuit can be reduced to its minimum allowable value.

K1 331

Claims (4)

1. CIAIMS 1

   A picture signal correcting circuit comprising:

   a constant-K low-pass filter for receiving a picture signal in which the upper limit frequency is substantially eqUal to the cut-off frequency of the filter:

   a transistor circuit having a collector which is grounded, a base which is connected to receive the output signal from said low-pass filter, and an emitter providing an output signal:

   a first resistor one end of which is connected to a power supply terminal and the other end of which is connected to one end of a capacitor; said caDacitor having one end which is connected to the other end of said first resistor and the other end of which is connected to an output terminal for receiving a low impedance load:

   second resistor connected between the emitter of said transistor and the output terminal; and, diode, the cathode of which is connected to the emitter of said transistor and the anode of which is connected to a junction between said first resistor and said caDacitor.
2. 2. A picture signal correcting circuit as claimed in Claim 1, wherein said transistor circuit includes an NPN transistor.
3. 3. A picture signal correcting circuit as claimed in Claim 1 or in Claim 2 wherein said constant-K low-pass filter includes inductive means, and a second capacitor, and a resistor connected parallel to said inductive means for correctinE amplification of the picture signal.
4. 4. A picture signal correcting circuit t 1 1 11 i m 1 i K1 33. 1 a substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

   1 Published 1989 at The Patent Office, State House, 6671 High Holborn, London WClR4TP. Further copies maybe obtained from The Patent OMce. Sales Branch. Bt Mary Cray, Orpington. Kent BR5 3RD. Printed by Multiplex techniques ltd, St Mary Cray, Kent, Con. 1187