GB2207570A - Emitter coupled logic device - Google Patents

Description

1.. r 11 22075 t U 1 1 EMITTER COUPLED LOGIC DEVICES.

This invention relates to logic circuits and particularly to emitter coupled logic (ECL) circuits.. Such circuits are considered high speed relative to other forms of logic circuits but have a lin-dting speed of switching which is given by the formula.

2.2 x R.ps/pf.

Where R is load resistance per picofarod of capacitance, and the time is given in pico seconds.

Other disadvantages of high speed ECL switching circuits are that, at high frequencies, an emitter follower can appear inductive leading to possible instability or even oscillation; and, because the output transistor can be turned off, current pulses are taken from the supply.

Commercially available members of the ECL family are ECL IOK, ECL IOKH, ECLIII and ECLLOOK in ascending order of speed capability. However, all these devices suffer from aforesaid disadvantages.

It is an object of the present invention to provide an emitter coupled logic device wherein the aforesaid disadvantages are minimised whilst providing an increase in switching speed.

According to the present invention, an emitter coupled logic device comprises first and second emitter follower transistors and a long tailed pair of transistors, a first input to the device driving the first emitter follower transistor so that it acts as an active load for 2 1 1 the first transistor of the long-tailed pair, 'and driving the second transistor of the long-tailed pair, and a second input to the device driving the second emitter follower transistor so that it acts as an active load for the second transistor of the long-tailed pair, and driving the first transistor of the long-tailed pair, each of the emitter follower transistors providing a respective output which outputs act in "push-pull" manner.

The first and second inputs may be complementary.

Preferably, the gain of the long-tailed pair is arranged to be unity.

Resistors may be provided to act as "pull-downs" for the bases of the transistors of the long-tailed pair.

Each transistor of the long-tailed pair may be driven by its respective input through a respective transistor and diode-coupled transistor.

The overall current through the long-tailed pair may be controlled by an active load. Alternatively, a known bias circuit may be used to provide a specific output temperature coefficient.

The invention will be described further, by way of example, with reference to the accompanying single figure which illustrates schematically, an emitter coupled logic device in accordance with the present invention.

Referring to the drawing, an emitter coupled Jogic device comprises a first emitter follower transistor Q3 and a second emitter follower transistor Q4. An input 10 drives transistor Q3 and a complementary input 11 drives transistor Q4. Transistors Q3 and Q4 acts as respective active loads for transistors Q, and Q2 forming a ,k 3 long-tailed pair. The transistors Q, and Q2 are, in turn, driven by the inputs 11 and 10 respectively through transistor Q5 and diodecoupled transistor Q9 and through transistor Q6 and diode coupled transistor Q10. The emitter follower transistors Q3 and Q4 provide respective complementary outputs 12, 13 of the device.

Resistors R1 and R2 act as pull-downs ensuring that the bases of the transistors Q, and Q2 of the long-tailed pair respond quickly.

Resistor R3 and diode-coupled transistor Q8 control a transistor Q7 in the tail of the long-tailed pair to define the pull-down current of the pair.

In operation, the emitter follower transistor Q3 acts as an active load for the long-tailed pair transistor Q, whilst the emitter follower transistor Q4 acts as an active load for the long-tailed pair transistor Q2. As can be seen, the inputs 10 and 11 are fed differentially. Assuming a signal on the input 10, the emitter follower transistor passes the signal directly to the output 12. Simultaneously, the signal input at input 10 drives the transistor Q6 and through the diode-coupled transistor Q10 applies the signal to the base of the transistor Q2 of the long-tailed pair.

An inverse input signal is applied to the base of the emitter follower transistor Q4 and via the transistor Q5 and the diode coupled transistor Q9 to the base of the transistor Q, of the long-tailed pair.

The cross-symmetry of the circuit means that the emitter follower transistors Q3 and Q4 are driven in anti-phase and the outputs operate therefore in a "push-pull" manner.

4 1 In comparison with conventional emitter coupled logic, wherein active pull-up is provided, the device according to the invention also provides active pull-down.

The invention is not confirned to the precise details of the foregoing example and variations may be made thereto. Tor instance, the gain of the long-tailed pair as above described is substantially unity. However, by the provision of an appropriate fixed resistance between the transistors Q3 and Q, andlor between the transistors Q4 and Q2, this gain may be adjusted.

Whilst the input 11 has been shown as the complement of the input 10, a reference voltage may alternatively be applied thereto.

If desired, it is possible to replace the bias circuit defined by the resistor R3 and diode-coupled transistor Q8 controlling the tail transistor Q7 with a single resistor in the tail. Alternatively, a more complex bias circuit giving a specific output temperature coefficient may be provided.

As compared with a conventional ECL circuit, the device above described is balanced (whereby power pulses are minimised or avoided), faster and more stable as the emitter follower transistors operate at substantially the same part of their operating characteristic throughout the operating cycle.

Claims (8)

CLAIMS:

1. An emitter coupled logic device comprises first and second emitter follower transistors and a long tailed pair of transistors, a first input to the device driving the first emitter follower transistor so that it acts as an active load for the first transistor of the longtailed pair, and driving the second transistor of the long-tailed pair, and a second input to the device driving the second emitter follower transistor so that it acts as an active load for the second transistor of the long- tailed pair, and driving the first transistor of the long-tailed pair, each of the emitter follower transistors providing a respective output which outputs act in "push-pulF' manner.

2. A device as claimed in claim 1 wherein the first and second inputs are arranged to receive complementary signals.

3. A device as claimed in claim 1 or 2 wherein the gain of the long-tailed pair of transistors is arranged to be unity.

4. A device as claimed in claim 1, 2 or 3 further including respective resistors for pulling down the bases of the long-tailed pair of transistors.

5. A device as claimed in any of claims 1 to 4 wherein each of the transistors of the long-tailed pair is arranged to be driven, from its respective input, through a respective transistor and diode-coupled transistor. 6. A device as claimed in any preceding claim further including an active load for controlling the current flowing through the longtailed pair of transistors.

6

7. A device as claimed in any of claims 1 to 5 further including a bias circuit for providing a specific output temperature coefficient for controlling the current flow through the long-tailed pair of transistors.

8. An emitter coupled logic device substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing.

Published 198C at The Pa;ent Oftice, State lio-asc. 66 71 Higl Holborn. London WC1R 4TP. urzJ..,er copies may be obtained from The Patent O:Mce, Sales Branch, St Mary Cray. Orpington. Xent BR5 3RD. Printed by Multiplex techniques ltcl, St Mary Cray, Kent. Con. 1187.