GB2199695A - Dynamic random access memory with selective well biasing - Google Patents
Dynamic random access memory with selective well biasing Download PDFInfo
- Publication number
- GB2199695A GB2199695A GB08729622A GB8729622A GB2199695A GB 2199695 A GB2199695 A GB 2199695A GB 08729622 A GB08729622 A GB 08729622A GB 8729622 A GB8729622 A GB 8729622A GB 2199695 A GB2199695 A GB 2199695A
- Authority
- GB
- United Kingdom
- Prior art keywords
- well
- array
- peripheral control
- biasing
- storage cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 31
- 230000002093 peripheral effect Effects 0.000 claims description 24
- 238000003491 array Methods 0.000 claims description 18
- 230000015654 memory Effects 0.000 claims description 12
- 210000000352 storage cell Anatomy 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 230000005055 memory storage Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 description 13
- 210000004027 cell Anatomy 0.000 description 11
- 238000013461 design Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
1 2199695 DYNAMIC RANDOM ACCESS MEMORY WITH SELECTIVE WELL BIASING til r I
This invention pertains to integrated circuits, but more specifically, to dynamic random access memories having separate memory arrays and peripheral control circuits arranged in respective impurity wells, e.g. a region of doped impurities in a semiconductor substrate.
In the design and fabrication of dynamic random access memories (DRAMs), there continuously exists a need to solve recurring difficulties with the introduction of each new generation of DRAM device. The dif f iculties ensue from design changes to increase data storage capacity by increasing packing density and/or improving operating performance. For instance, with the advent of one-megabit and four-megabit one-transistor DRAM devices, higher packing densities required the development of trench storage capacitors, instead of planar capacitors disposed in the plane of the substrate surface, for use in the memory cell arrays. Trench capacitors extend vertically into the body of the semiconductor substrate and enable storage of charge in a smaller planar area of the substrate to attain high packing density.
A typical one-transistor DRAM, for example, includes several storage arrays wherein each cell in each array includes a storage capacitor and an access (transfer) transistor. The DRAM also includes a region of peripheral control circuits associated with each storage array for transferring charge to and from the cells. The transferred charge repr esents binary information, e.g. a logic "I" or "Off. Both the storage arrays and the peripheral control circuits are fabricated on the same substrate. optimum circuit operating parameters, such as biasing voltages, of the storage array and the 1 2 peripheral control circuits, however, do not necessarily coincide. As a result, optimizing conditions for one generally sacrifices the performance of the other.
As exemplary of a difficulty encountered, it is desirable to reduce the voltage level applied across the storage capacitors in order to minimize dielectric breakdown, punch-through, and other deleterious effects. A ground bias is preferred for the storage arrays. At the same time, it is desirable to apply a negative biasing voltage to peripheral circuits to improve signal margins for such circuits as the sense amplifiers. A backbiasing generator generally is used to produce the biasing voltage. An onchip back-bias generator, however, produces undesirable noise which couples the storage nodes of the array storage capacitors. Moreover, in the case of a p-type substrate employing CMOS structures for peripheral control circuits, NMOS circuits on the substrate have a tendency to latch up if a ground bias is employed, and the circuit becomes more -susceptible to problems due to large parasitic capacitance.
In certain types of prior art designs, it has been known to selectively pump respective p-wells on a substrate. For example, an article titled "A
Selectively Pumped P-Well Memory Array Technology For High-Density Static RAMs" by Wang, et al., IEEE 1986, discloses a construction for optimizing circuit speed and reducing array leakage in an SRAM (static random access memory) device. It employs an on-chip biasing generator for applying one-half of the supply voltage Vdd to selected memory cell arrays, but does not address peculiar problems of DRAM devices, discussed herein.
Accordingly, it is an objective of the present invention to overcome the difficulties encountered in j the design and fabrication of high-density DRAM devices. It is another objective of the present invention to improve operating performances of high density DRAM devices employing trench technology for the memory storage arrays.
It is a further objective of the present invention to provide a system for optimizing the operating performance of respective groups of circuits arranged in respective impurity wells on an n-type substrate. In this regard, the present invention aims to optimize the performance of peripheral control circuits by for the of a proialviding a first selected well biasing voltage these circuits, while at the same time, reducing voltage across the capacitors in the storage arrays 15 memory device.
2 0 SUMMARY OF THE INVENTION
In accordance with the present invention, a selective biasing scheme is provided for a dynamic random access memory fabricated as a CMOS (complementary metal-oxidesemiconductor) circuit on an n-type substrate which includes at least one doped impurity region in the substrate defining a first well for carrying the circuits of the memory storage array, and at least a second region of doped impurities for defining asecond well carrying the peripheral control circuits associated with the memory storage arrays. The first and second wells are substantially electrically isolated from one another while selective biasing potentials are applied to the respective wells. The first well carrying the memory storage arrays is grounded in order to minimize the risk of capacitor dielectric breakdown and/or punchthrough, while the second well carrying the peripheral control circuits has a back-bias voltage applied thereto 4 to improve, inter alia, signal margins.
In the case of an n-type substrate having p-wells for carrying the storage arrays and NMOS peripheral control circuits, a negative biasing potential couples the peripheral wells and a ground potential couples the storage wells. Accordingly, the memory storage arrays take full advantage of smaller voltage drop across the storage nodes while the peripheral control circuits take full advantage of a biasing voltage to improve signal 10 margins.
Other advantages, aspects and objectives of the present invention will become more readily apparent upon review of the succeeding description taken in connection with the accompanying drawings. The invention though is 15 pointed out with particularity by the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 depicts an integrated circuit structure employing CMOS technology wherein respective wells in the substrate are selectively biased in accordance with 20 the present invention.
Figure 2 depicts a circuit schematic of the integrated circuit of Figure 1.
DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
Figures 1 and 2 depict a typical application of the principles of this invention in a CMOS one-transistor DRAM circuit fabricated on an n-type substrate with respective p-wells for carrying the storage arrays and the peripheral control circuits.
A starting substrate 60 is n-type and includes a p30 well 64 and 64 complementary n-region 66 and p-well 62. Corresponding regions 62, 64, and 66 also are shown diagrammatically in the circuit diagram of Figure 2. In k n It, -4 a CMOS structure employing complementary metal oxide technology, respective n-regions and p-wells carry complementary signals through respective n-channel and p-channel devices in the regions 62 and 66. Grounded p- well 64 carries the arrays of memory storage cells, whereas a negative biasing voltage VBB' preferably 5VDD' from the back-biasing generator 63 couples the pwell 62. The back-bias generator 63 is known to produce on- chip noise, but it nevertheless is essential to the operation of the field effect transistors in the region 62.
The p-well 64 includes a memory cell comprising an access transistor and a trench capacitor 68 vertically etched in the body 60 of the silicon substrate. In p- well 64, the trench capacitor 68 comprises a doped n+ polysilicon core 70 separated from the body 60 of the substrate by a thin capacitor dielectric 72. Binary data represented by charge packets, are carried to and from the storage capacitor 68 by way of conductive layers 82 and 76. A heavily doped p+ region 74 of boron encompasses the trench in the body of the substrate 60. The boron doped p+ region 74 is recessed or submerged - from the surface of the substrate body 60 thereby to form, in a preferred structure, a submerged storage plate trench capacitor cell described' in my copending application titled "Submerged Storage Plate Memory Cell" filed of even date, incorporated herein. An n-channel field-effect-transistor (FET) transfers data to and from the trench cell 68 by way of a thin layer of conductive polysilicon 76 connected to the source region 78 of the FET. A drain region 80 constitutes the means by which charge packets are transferred to and from the cell via a polycide conductor 82 under control of a signal applied to gate 84 of the field effect transistor. In a
6 conventional manner, the gate 84 is spaced from the surface of the semiconductor substrate by a thin insulating layer 86, such as a silicon oxide/nitride composite. Although not shown, a second trench cell lies to the right of trench cell 68 in a particular layout pattern to maximize further the packing density.
Peripheral control circuits lie in the corresponding p-well 62 and n-well 66. Conductors 88 and 90 carry complementary signals to and from a sense amplifier (not shown) via respective contacts with source and drain regions 91 and 92. The region 92 is the source of a field effect transistor which also includes a gate 93 and drain 94. A thin insulator separates the gate '93 from the surface of the substrate 60 above a p-channel region between the source and drain regions 92 and 94. A corresponding arrangement also exists on the substrate at a position laterally spaced from the transistor just described. Thick field oxide regions 96 form channel stops in the integrated circuit. Likewise, an oxide layer 97 provides insulation and support for polycide conductors whereas a passivation layer 98 provides support for contacts 88, 89, and 90 as well as protection for the underlying components on the substrate. Region 64 is grounded at grounding node 65 whereas region 62 couples a 5VDD source from a backbiasing generator 63. Region 66 is biased to the full supply voltage VDD and connects to the supply voltage source 67 through the body 60 of the substrate. To the extent illustrated, corresponding parts of the schematic diagram of Figure 2 are labeled with corresponding reference numerals to show correlation between the physical structure and circuit schematic in order to aid understanding of the invention.
Thus, in accordance with an important aspect of the 1 7 present invention, a negative biasing potential VBB couples the p-well 62 to enable fast and accurate operation of FETs located therein while the p- well 64 is grounded at node 65 to minimize the voltage across the dielectric 72 between the storage plate 70 and region 74 disposed about the trench in the substrate 60.
As it will be appreciated f rom the above that as a result of the present invention, a selective biasing scheme provides certain advantages not otherwise attainable by prior art designs. It will be equally apparent and is contemplated that modifications and/or changes may be made in the illustrative embodiment without departure from the invention. Accordingly, it is especially intended that the foregoing description and accompanying drawings are illustrative of the preferred embodiments only, not limiting in that the true spirit and scope of the invention is determined by reference to the appended claims and their legal equivalent'.
1 1 8
Claims (4)
1. In a dynamic random access memory fabricated on a substrate as an integrated circuit, said memory including at least one array of storage cells and at least one peripheral control circuit for transferring data with said array, the improvement comprising: first well means for providing a doped region for carrying said array of storage cells, second well means for providing a doped region for carrying said peripheral control circuit, said second well means being substantially electrically isolated from said first well means, array biasing means,for providing a biasing potential to said first well means, and peripheral biasing means for providing a different biasing potential to said second well means.
2. In a dynamic random access memory fabricated on an n-type substrate as an integrared circuit, said memory including at least one array of storage cells and at least one peripheral control circuit for trans- ferring data with said array, the improvement comprising: first well means in said substrate for providing a doped region in which said array of storage cells is fabricated, second well means for providing a doped region for carrying said peripheral control circuit, said second well means being substantially electrically isolated from said first well means, grounding means for applying a ground potential to said first well means, and biasing means for applying a predetermined biasing potential to said second well means.
3. In a dynamic random access memory fabricated on an n-type substrate as an integrated circuit, said memory including a plurality of arrays of storage cells and a plurality of respctive CISOS peripheral control 1 1 1 1 9 circuits associated with said arrays of storage cells for transferring data therewith, the improvement conprising: a first p-well for providing a first p-type doped region for carrying said arrays of storage cells, a second p-well and a complementary n-well for providing complementary doped regions for carrying said CMOS peripheral contrQl circuits, sikid first region and complementary regions being substantially electrically isolated, grounding means for applying a ground potential to said first p-well, and biasing means for applying predetermined biasing potentials to said complementary regions.
4. In a dynamic random access memory fabricated on a substrate as an integrated circuit, said memory in- cluding at least one array of storage cells and at least one region of peripheral control circuits for transferring data with the storage cells, the improvement comprising: at least two electrically isolated wells of doped -impurities in the substrate wherein one well carries said peripheral control circuits and a second well carries said memory storage arrays, said doped impurity regions being substantially electrically isolate, grounding means for applying a ground potential to the doped impurity regions carrying the storage array, and back biasing means for applying the predetermined biasing potential to another of said doped impurity regions carrying the peripheral control circuits.
Published 1988 at The Patent Office, State House. 6671 High Holborn, London WC1R 4TP. Further copies may be obtained from The Patent Office, Sales Branch. St Mazy CrFy. 0-pingl,-,n, Rent BR5 3r1D_ Printed by MultiDlex techmoues Ittl. St Marv Cray. Kent. Con. 1187.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US74787A | 1987-01-06 | 1987-01-06 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8729622D0 GB8729622D0 (en) | 1988-02-03 |
| GB2199695A true GB2199695A (en) | 1988-07-13 |
| GB2199695B GB2199695B (en) | 1990-07-25 |
Family
ID=21692854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8729622A Expired - Fee Related GB2199695B (en) | 1987-01-06 | 1987-12-18 | Dynamic random access memory with selective well biasing |
Country Status (5)
| Country | Link |
|---|---|
| KR (1) | KR880009440A (en) |
| DE (1) | DE3744376A1 (en) |
| FR (1) | FR2609351A1 (en) |
| GB (1) | GB2199695B (en) |
| NL (1) | NL8800008A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2246014A (en) * | 1990-07-12 | 1992-01-15 | Samsung Electronics Co Ltd | Capacitors for dram cells |
| GB2256968A (en) * | 1991-06-19 | 1992-12-23 | Samsung Electronics Co Ltd | Connections in semiconductor memory devices |
| EP0550894A1 (en) * | 1992-01-09 | 1993-07-14 | International Business Machines Corporation | Trench DRAM cell array |
| EP0550870A1 (en) * | 1992-01-09 | 1993-07-14 | International Business Machines Corporation | Trench DRAM cell array |
| EP0563879A1 (en) * | 1992-03-30 | 1993-10-06 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of fabricating the same |
| US5432365A (en) * | 1988-02-15 | 1995-07-11 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
| EP0681331A2 (en) * | 1994-04-29 | 1995-11-08 | Texas Instruments Incorporated | Improvements in or relating to dynamic random access memory devices |
| US7005338B2 (en) * | 2002-09-19 | 2006-02-28 | Promos Technologies Inc. | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0066429A2 (en) * | 1981-05-22 | 1982-12-08 | Hitachi, Ltd. | Semiconductor memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57194565A (en) * | 1981-05-25 | 1982-11-30 | Toshiba Corp | Semiconductor memory device |
| JPH0671067B2 (en) * | 1985-11-20 | 1994-09-07 | 株式会社日立製作所 | Semiconductor device |
-
1987
- 1987-12-18 GB GB8729622A patent/GB2199695B/en not_active Expired - Fee Related
- 1987-12-26 KR KR870014950A patent/KR880009440A/en not_active Application Discontinuation
- 1987-12-29 DE DE19873744376 patent/DE3744376A1/en not_active Withdrawn
-
1988
- 1988-01-05 NL NL8800008A patent/NL8800008A/en not_active Application Discontinuation
- 1988-01-06 FR FR8800058A patent/FR2609351A1/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0066429A2 (en) * | 1981-05-22 | 1982-12-08 | Hitachi, Ltd. | Semiconductor memory |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5432365A (en) * | 1988-02-15 | 1995-07-11 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
| GB2246014A (en) * | 1990-07-12 | 1992-01-15 | Samsung Electronics Co Ltd | Capacitors for dram cells |
| GB2256968A (en) * | 1991-06-19 | 1992-12-23 | Samsung Electronics Co Ltd | Connections in semiconductor memory devices |
| US5348905A (en) * | 1992-01-09 | 1994-09-20 | International Business Machines Corporation | Method of making diffused buried plate trench DRAM cell array |
| US5264716A (en) * | 1992-01-09 | 1993-11-23 | International Business Machines Corporation | Diffused buried plate trench dram cell array |
| EP0550870A1 (en) * | 1992-01-09 | 1993-07-14 | International Business Machines Corporation | Trench DRAM cell array |
| EP0550894A1 (en) * | 1992-01-09 | 1993-07-14 | International Business Machines Corporation | Trench DRAM cell array |
| EP0563879A1 (en) * | 1992-03-30 | 1993-10-06 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of fabricating the same |
| US5691550A (en) * | 1992-03-30 | 1997-11-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5959324A (en) * | 1992-03-30 | 1999-09-28 | Kabushiki Kaisha Toshiba | Semiconductor device including an improved terminal structure |
| EP0681331A2 (en) * | 1994-04-29 | 1995-11-08 | Texas Instruments Incorporated | Improvements in or relating to dynamic random access memory devices |
| EP0681331A3 (en) * | 1994-04-29 | 1997-09-03 | Texas Instruments Inc | Improvements in or relating to dynamic random access memory devices. |
| US5894145A (en) * | 1994-04-29 | 1999-04-13 | Texas Instruments Incorporated | Multiple substrate bias random access memory device |
| US7005338B2 (en) * | 2002-09-19 | 2006-02-28 | Promos Technologies Inc. | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
| US7057231B2 (en) | 2002-09-19 | 2006-06-06 | Promos Technologies, Inc. | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8729622D0 (en) | 1988-02-03 |
| NL8800008A (en) | 1988-08-01 |
| FR2609351A1 (en) | 1988-07-08 |
| GB2199695B (en) | 1990-07-25 |
| DE3744376A1 (en) | 1988-07-14 |
| KR880009440A (en) | 1988-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7241658B2 (en) | Vertical gain cell | |
| US6804142B2 (en) | 6F2 3-transistor DRAM gain cell | |
| US7224024B2 (en) | Single transistor vertical memory gain cell | |
| US7030436B2 (en) | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means | |
| US7199417B2 (en) | Merged MOS-bipolar capacitor memory cell | |
| US5909400A (en) | Three device BICMOS gain cell | |
| US7257043B2 (en) | Isolation device over field in a memory device | |
| JP3089570B2 (en) | Integrated circuit comprising a plurality of transistor structures with shared electrodes | |
| US8035139B2 (en) | Dynamic random access memory having junction field effect transistor cell access device | |
| US6136638A (en) | Process technology architecture of embedded DRAM | |
| GB2269049A (en) | Semiconductor memory device | |
| KR100706456B1 (en) | Plateline sensing | |
| GB2199695A (en) | Dynamic random access memory with selective well biasing | |
| US7642588B2 (en) | Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same | |
| US6002636A (en) | Semiconductor memory drive capable of canceling power supply noise | |
| Horiguchi et al. | Process technologies for high density, high speed 16 megabit dynamic RAM | |
| US6097048A (en) | Dynamic random access memory cell suitable for integration with semiconductor logic devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |