GB2198900A - Circuit arrangement with two serially connected high-voltage transistors - Google Patents

Abstract

A pair of high voltage bipolar power transistors (TR1, TR2) are serially connected through an inductor (L) to a supply with associated components connected to the transistors which determine various periods of operation. In order to ensure that the transistors (TR1, TR2) are rendered non-conducting simultaneously sensors (S1,S2) sense their change in base current to produce pulses in monostable multivibrators (M1, M2) whose relative phases are compared in a digital phase comparator (PC). The drive for each transistor (TR1, TR2) from its associated driver stage (DR1, DR2) is via an associated amplitude control device (AC1, AC2) which controls the amplitude of the drive pulses for the transistors one of the devices (AC2) being variable and controlled by the output of the phase comparator (PC). The amplitude of the drive pulse is changed to change the amount of charge carriers in the transistor (TR2) until their storage times are equal to ensure the simultaneous non-conduction of the transistors (TR1, TR2). <IMAGE>

Description

DESCRIPTION: "CIRCUIT ARRANGEMENT WITH TWO SERIALLY CONNECTED HIGH-VOLTAGE TRANSISTORS" The invention provides a circuit arrangement comprising first and second high-voltage bipolar power transistors connected in series, drive means for repeatedly cutting off each of the transistors, which drive means are connected to a signal source for producing a pulsatory drive signal for each of the transistors, the drive means for each transistor comprising a device having a characteristic which is used in the control of the drive signal for its associated transistor, and a stage for controlling the characteristic of at least one of the devices depending on the relative cut-off times of said transistors in the absence of said control in order to ensure that the transistors are automatically cut-off substantially simultaneously.

A circuit arrangement of the above type is described in Published European Patent Application No. 0 110 461 Al. The arrangement described in that published application senses the voltage at the junction of the two switches and compares it with a reference voltage, the resulting comparison being used to control the device provided in one or each of the transistor base connections. With this arrangement the devices are delay elements whose delay period can be changed so that both transistors are cut-off simultaneously.

It is an object of the present invention to provide a circuit arrangement of the above type in which the transistors are cut-off in a different controlled manner.

The invention provides a circuit arrangement comprising first and second high-voltage bipolar power transistors connected in series, drive means for repeatedly cutting off each of the transistors, which drive means are connected to a signal source for producing a pulsatory drive signal for each of the transistors, the drive means for each transistor comprising a device having a characteristic which is used in the control of the drive signal for its associated transistor, and a stage for controlling the characteristic of at least one of the devices depending on the relative cut-off times of said transistors in the absence of said control in order to ensure that the transistors are automatically cut-off substantially simultaneously, characterised in that said devices control the amplitude of the drive current applied to the base of each transistor to substantially equalise the charge carrier storage times for the first and second transistors such that said transistors cut-off substantially simultaneously.

With the arrangement according to the invention the applicants have realised that the problem of the charge carrier storage time being increased with increase in drive current can be used to advantage to equalise the storage times of two transistors and so ensure simultaneous cut-off of the transistors.

A particular embodiment may be characterised in that each amplitude control device comprises a capacitor and a parallel resistive path, the resistive path in the said one controlled device comprising a transistor whose conductivity is controlled from the control stage.

The above and other features of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram, partly in block form, of a circuit according to the invention, Figure 2 shows various waveforms associated with the operation of the arrangement of Figure 1, and Figures 3 and 4 are modifications of the arrangement of Figure 1.

Figure 1 is a diagram, partly in block schematic form, of a line deflection circuit having a line output stage for energising a line deflection coil Ly. The line output stage comprises first and second high voltage npn bipolar power switching transistors TR1 and TR2 with the collector of transistor TR1 being connected to a voltage supply B+ through an inductor L whilst its emitter is connected to the collector of transistor TR2 whose emitter is connected to earth. The inductor L may be the primary of a transformer the secondary windings of which supply respectively the eht supply for the final anode of a display tube associated with the deflection circuit and the low voltage supply or supplies for other parts of the circuit.A diode D1 and a retrace capacitor CR1 are each connected in parallel with the transistor TR1 whilst a diode D2 and retrace capacitor CR2 are similarly connected in parallel with transistor TR2. A trace capacitor CT and the deflection coil Ly are serially connected between the collector of transistor TR1 and earth.

The line output stage operates in known manner with the voltage stored in trace capacitor CT producing the required sawtooth current through deflection coil Ly which initially flows through the diodes D1 and D2 for a first part of a trace period and subsequently through the transistors TR1 and TR2 through a second part of a trace period. The retrace period is initiated at the instant transistors TR1 and TR2 become non-conducting, these transistors having been previously rendered conducting prior to or at the commencement of the second part of the trace period by positive going drive pulses applied to their bases. During the retrace period the inductance and capacitance in the line output stage resonate to produce a half sine wave flyback pulse which is followed by the start of a further trace period.For optimum operation the two transistors TR1 and TR2 should become non-conducting simultaneously otherwise there will be unequal power sharing between the two transistors which could lead to the damage of one transistor or at least the peak voltage will be reduced which in turn would reduce the eht supply when derived from this stage. Although both transistors may receive at the same time a signal to cut them off simultaneous non-conduction may not be achieved as the storage times of the charge carriers in the transistors may not be equal and may vary with time and temperature. In order to ensure simultaneous non-conduction the transistors are driven in the manner as further described.

A line oscillator stage LO produces pulses at line frequency which pulses are applied from its output to the respective input of a first (DR1) and a second (DR2) driver stage. The drive pulse output of driver stage DR1 is applied to the input of an amplitude control device AC1 in which the amplitude of the forward drive base current is set to a given level, the drive pulse from the device AC1 being applied via a first sensor S1 to the base of transistor TR1.

In a similar manner the drive pulse output of the second driver stage DR2 is applied to the input of a second amplitude control device AC2 in which the amplitude of the forward drive base current can be varied depending upon a signal applied to its control input C, the resulting drive pulse from the device AC2 being applied by way of a second sensor S2 to the base of transistor TR2. Each of the sensors S1, S2 senses the base current of its associated transistor TR1, TR2 and the resulting signal is applied to the input of an associated pulse generator in the form of a gated monostable multivibrator M1, M2. As each transistor TR1, TR2 becomes non-conducting there is a drop in its base current which is sensed by the sensors S1, S2 and applied to the associated monostable M1, M2 to trigger it into its non-stable state.In addition to the input from the sensor, each monostable receives at a further input a gating pulse from the output of the oscillator LO to ensure that the multivibrator is not triggered by other pulses during the remaining part of the line period. The pulse outputs from the monostables M1, M2 are applied to respective inputs of a digital phase comparator PC in which the relative phases of the pulses are compared and a voltage produced whose amplitude depends on their phase difference.

This voltage is applied from the output of the phase comparator PC to the control input C of the device AC2 to vary the amplitude of the forward drive base current applied to transistor TR2 to ensure it becomes simultaneously non-conducting with transistor TR1. The manner in which this is achieved will be described with reference to Figure 2.

Figure 2 shows various idealised waveforms associated with the line deflection circuit of Figure 1 with Figure 2A showing the output of the line oscillator LO for application to the driver stages DR1 and DR2 and also for gating the monostables M1 and M2.

The base current for transistor TR1 is shown in Figure 28 which starts to reduce in magnitude at times tl, t10 on receipt of the negative going edge in the drive pulse which is inverted by driver stage DR1 with respect to the pulse shown in Figure 2A. The charge carriers in transistor TR1 are then removed with the base current reversing in polarity until times t2, t20 when the transistor comes out of saturation and the transistor is very rapidly cut-off to initiate the flyback period. At times t3, t30 during the following scan period transistor TR1 becomes forward biased when a positive drive pulse is applied to the base of this transistor and derived from the line oscillator pulse in Figure 2A. This cycle is then repeated.Figure 2C shows the voltage induced by the sensor S1, a sharp rise or fall in this voltage being produced with the changes in transistor TR1 base current. Monostable M1 is triggered by a positive going edge in the presence of a gating pulse (Figure 2A), this condition occurring at times t2, t20 and the pulses produced at the output of monostable M1 are shown in Figure 2D, these pulses being limited in duration by the negative going edge of the gating pulses.

The base current for transistor TR2 is shown in Figure 2E which also starts to reduce at times tl, t10 it being assumed that the storage time for the charge carriers in transistor TR2 is shorter than that for the transistor TR1 and that transistor TRZ comes out of saturation at times t2', t20'. Figure 2F shows the voltage induced by the sensor S2 and Figure 2G the resulting pulses produced by monostable M2 which pulses commence earlier than the corresponding pulses from monostable M1. The relative phase of these two pulse outputs are compared in the phase comparator PC and the resulting control signal applied to the control signal input C of the amplitude control device AC2, it being initially assumed that device AC2 gives the same amplitude forward drive base current as device AC1.

The drive current applied to the base of a line output transistor (TR1, TR2) has an effect on the quantity of charge carriers in the transistor and when the drive current is in excess of that required to cause the transistor to just saturate the transistor contains an excess of charge carriers and the storage time required to remove these charge carriers at transistor cut-off is increased.In the case of the high voltage bipolar switching transistors it is normal for the drive current to be greater than that required for a nominal transistor to be just saturated in order to cater for te spread in characteristics found with transistors of the same type and it wilL be appreciated that due to the spreads in these characteristics the storage times for two transistors when driven with the same drive current may differ as shown in Figures 2B and 2E.With the arrangement of Figure 1 the output from the phase comparator PC is arranged to control the amplitude control device AC2 such that the forward drive current applied to the base of transistor TR2 during each scan period is increased to increase the quantity of charge carriers in the transistor and so increase the storage time until it corresponds to that of transistor TR1, this being shown by the broken lines in Figure 2E. In this way the storage times of the transistors TR1 and TR2 are equalised and these two transistors become non-conducting simultaneously.

In the description of the arrangement of Figure 1 only amplitude control device AC2 is described as providing a variation of the forward drive current amplitude. It is possible to make the other amplitude control device AC1 also variable which would be controlled by a complementary control signal from the phase comparator PC such that as the amplitude of the forward drive current from device AC2 increased the amplitude of the drive current from AC1 is decreased. With such an arrangement the degree of control can be less than that provided by device AC2 when that is the only one which is variable.

Figure 3 shows in more detail parts of the line deflection circuit shown in Figure 1, corresponding reference symbols indicating like components in the two figures. In Figure 3 the drive stages DR1, DR2 are formed by a driver transistor TR3 whose base is connected to the output of the line oscillator LO whilst its emitter is connected to earth. The collector of transistor TR3 is connected through the primary windings, connected in parallel, of respective driver transformers T1, T2 and a resistor R1 to the positive terminal of a low voltage supply B.The lower end of the secondary winding of transformer T1 is connected to the junction between transistors TR1 and TR2 whilst its upper end is connected to the input of amplitude control device AC1 which consists of a resistor R2 connected in parallel with a capacitor Cl. The resistor R2 and capacitor C1 together with the leakage inductance of transformer T1 are selected to provide the required drive for transistor TR1. The sensor S1 comprises a current transformer with the primary winding (which may in practice be a straight conductor) connected between the device AC1 and the base of transistor TR1.

The lower end of the secondary winding of transformer T2 is connected to earth whilst its upper end is connected to the input of amplitude control device AC2 which comprises a capacitor C2 connected in parallel with the series arrangement of a resistor R3 and a npn transistor TR4 which together with the leakage inductance of transformer T2 are selected to provide the drive for transistor TR2, the base of transistor TR4 forming the control input C for this device. Sensor S2 takes the same form as sensor S1 with the primary winding being connected between the device AC2 and the base of transistor TR2.One end of the secondary windings of each of the sensors S1 and S2 are connected to earth whilst the other end of each secondary winding is connected to their associated monostable M1, M2 which in this case take the form of a dual monostable multivibrator. The output of the phase comparator PC controls the degree of conduction of transistor TR4 and hence its resistance to vary the amplitude of the drive current at the base of transistor TR2 and hence its charge carrier storage time.

Figure 4 is a modification of the arrangement shown in Figure 1 and in which corresponding components are given the same reference symbols. In Figure 4 the inductor L is divided to form two separate inductors L' and L" which are respectively connected between the supply terminal B+ and the collector of transistor TR1 and the emitter of transistor TR2 and earth. The phase comparator is replaced by a comparison stage CP one input of which is connected to the junction between the emitter of transistor TR1 and the collector of transistor TR2 whilst the other input is connected to a reference voltage Vr. The output of the comparison stage CP is connected to the control input C of variable amplitude control device AC2. This means of providing a control signal for the device AC2 is the same as thar described in the above European Patent Application No. 0110461 Al. As with Figure 1, both amplitude control devices AC1 and AC2 may be made variable.

Claims (3)

CLAIMS:

1. A circuit arrangement comprising first and second high-voltage bipolar power transistors connected in series, drive means for repeatedly cutting off each of the transistors, which drive means are connected to a signal source for producing a pulsatory drive signal for each of the transistors, the drive means for each transistor comprising a device having a characteristic which is used in the control of the drive signal for its associated transistor, and a stage for controlling the characteristic of at least one of the devices depending on the relative cut-off times of said transistors in the absence of said control in order to ensure that the transistors are automatically cut-off substantially simultaneously, characterised in that said devices control the amplitude of the drive current applied to the base of each transistor to substantially equalise the charge carrier storage times for the first and second transistors such that said transistors are cut-off substantially simultaneously.

2. A circuit arrangement as claimed in Claim 1, characterised in that each amplitude control device comprises a capacitor and a parallel resistive path, the resistive path in the said one controlled device comprising a transistor whose conductivity is controlled from said control stage.

3. A circuit arrangement substantially as herein described with reference to the accompanying drawings.