GB2194388A - Integrated circuit devices - Google Patents

Integrated circuit devices Download PDF

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Publication number
GB2194388A
GB2194388A GB8620291A GB8620291A GB2194388A GB 2194388 A GB2194388 A GB 2194388A GB 8620291 A GB8620291 A GB 8620291A GB 8620291 A GB8620291 A GB 8620291A GB 2194388 A GB2194388 A GB 2194388A
Authority
GB
United Kingdom
Prior art keywords
devices
integrated circuit
mounting structure
silicon
heat transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8620291A
Other versions
GB8620291D0 (en
Inventor
Peter Henry Saul
David John Pedder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB8620291A priority Critical patent/GB2194388A/en
Publication of GB8620291D0 publication Critical patent/GB8620291D0/en
Priority to PCT/GB1987/000588 priority patent/WO1988001437A1/en
Publication of GB2194388A publication Critical patent/GB2194388A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A mounting structure for a plurality of integrated circuit devices, the structure comprising a semiconductor material heat sink body (2) having a surface provided with recessed well areas which are capable of locating the said integrated circuit devices (3) with respect to one another, the circuit devices (3) having electrical connection points which are located on a side of each device which is positioned away from said heat sink body (2), the said connection points being electrically connected by means of solder bump interconnectors (6) to a common interconnect member (7) so as to provide electrical interconnections between the said devices (3) and external connection means for the devices (3) in the structure. This gives good heat sink operation and is particularly useful for high power dissipation devices.

Description

SPECIFICATION Integrated circuit device This invention relates to integrated circuit devices.
In the construction of a mounting for an integrated circuit device, one problem that arises is the need to provide in a single assembly the facilities both for electrical interconnection and good heat dissipation. One proposal intended to overcome the problem has been that of a 'silicon motherboard' which does offer a convenient multi-chip interconnection arrangement but it is one in which the thermal properties are somewhat inferior as compared with those of a conventional integrated circuit package. Where high power dissipation chips are intended to be mounted, it is of course particularly important that the mounting will allow a good dissipation of the heat likely to be generated in service.
The present invention was devised to provide a silicon motherboard assembly suitable for connecting numbers of integrated circuit chips and in which heat transfer problems were able to be reduced.
According to the invention, there is provided a mounting structure for a plurality of integrated circuit devices, the structure comprising a first silicon motherboard providing primarily good electrical contacts to the said devices, and each of the devices having a heat transfer face on a side away from said motherboard for enabling all of the devices to be brought into heat transfer contact with a suitable heat sink body.
Preferably, said heat transfer faces of said devices are thermally connected to a second silicon motherboard.
The said first silicon motherboard may comprise two or more smaller boards arranged to provide electrical interconnections or external connections to the integrated circuit devices of the plurality carried on the substrate. At least one of the said smaller boards may carry an additional semiconductor device. The additional device may comprise an input/output buffer for an integrated circuit device of the plurality carried on said substrate.
By way of example, a particular embodiment of the invention will now be described with reference to the accompanying drawing, the single Figure of which shows in cross-section and greatly enlarged an integrated circuit device mounting structure.
As depicted in the Figure, the mounting structure comprises a body 1 which incorporates means for heat sinking and which is made for example of a ceramic material with an external shape corresponding to that of a conventional integrated circuit package such as a dual-in-line, pin grid array, tape automatic bond or a leaded or leadless chip carrier.
The ceramic body 1 supports a silicon substrate slice 2 and in turn this supports three potentially active silicon devices 3. The bond ing between the carrier body 1 and the substrate 2, and also between the substrate 2 and the silicon devices 3 is effected by an alloy or epoxy resin bonding material which has good heat transfer properties. To the left and right hand ends of the substrate slice 2, silicon 'jumper' chips 4 are positioned.
Each of the silicon devices 3 and the jumper chips 4 is provided with solder bump interconnectors 6.
The solder bump interconnectors 6 are electrically connected together to join the required circuit components by a silicon interconnect slice 7 which extends above all the devices 3 and chips 4 on the substrate slice 2. Additional connections may also be made between circuit terminations on the chips 4 and electrical points on the ceramic body 1 by bond wires 8.
In operation of the integrated circuit device mounting structure, it will be observed that all the electrical interconnections are made to points on the upper surfaces of the devices 3 and chips 4. Conversely, all the heat generated in the operation of the devices is conducted away from the lower surfaces of the devices 3 and chips 4. Since the body 1 incorporates means for heat sinking, all the generated heat is conducted away in a downward direction and the thermal contact points are therefore designed to be the best that can be achieved without these points needing to have any associated electrical conduction properties.
The integrated circuit mounting structure of the invention has been found to be particularly suitable for mounting high power dissipation devices since it enables resulting heat transfer problems to be reduced and it thus has advantages over the currently available silicon motherboard systems. Since, the silicon devices 3 are connected to a first silicon motherboard constituted by the interconnect slice 7 for the electrical connections and additionally to a second silicon motherboard constituted by the silicon substrate 2 for heat transfer connections an extremely rigid structure can be provided. Because the structure is made of silicon throughout, thermal expansion mismatch problems are unlikely to occur.
In addition, an electrical screening effect is provided by the presence of the electrically conducting motherboards on each side of the devices 3.
The foregoing description of an embodiment of the invention has been given by way of example only, and a number of modifications may be made without departing from the scope of the invention as defined in the appended claims. For instance, the said first silicon motherboard constituted by the interconnect slice 7 may be made up of a number of smaller boards. The jumper chips 4 are in tended to serve an interconnection function but they could be readily made alternatively to serve as active chips in their own right. One advantageous configuration would be for the jumper chips to incorporate input/output buffer devices.
In practice, some manufacturing difficulty might be expected to occur in providing a number of chips for the mounting structure which are of identical thickness. In fact, silicon slice thickness is now readily controllable and it is repeatable in manufacture so this is un likely to cause any problem. In an extreme case, etching or polishing of the thickest slices down to a common thickness specifica tion might be necessary.
An accurate location of the chips on the lower substrate is also important. The required accuracy could be achieved, for example, by the etching of receiving wells on the substrate which would exactly define the required chip positions.

Claims (6)

1. A mounting structure for a plurality of integrated circuit devices, the structure com prising a first silicon motherboard providing primarily good electrical contacts to the said devices, and each of the devices having a heat transfer face on a side away from said motherboard for enabling all of the devices to be brought into heat transfer contact with a suitable heat sink body.
2. A mounting structure as claimed in Claim 1, in which said heat transfer faces of said devices are thermally connected to a second silicon motherboard.
3. A mounting structure as claimed in Claim 1 or 2, in which the said first silicon mother board comprises two or more smaller boards arranged to provide electrical interconnections or external connections to the integrated cir cuit devices of the plurality carried on the structure.
4. A mounting structure as claimed in Claim 3, in which at least one of said smaller boards carries an additional semiconductor device.
5. A mounting structure as claimed in Claim 4, in which said additional semiconductor de vice comprises an input/output buffer for an integrated circuit device of the plurality carried on said structure.
6. A mounting structure for a plurality of integrated circuit devices substantially as here inbefore-described with reference to the ac companying drawing.
GB8620291A 1986-08-20 1986-08-20 Integrated circuit devices Withdrawn GB2194388A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8620291A GB2194388A (en) 1986-08-20 1986-08-20 Integrated circuit devices
PCT/GB1987/000588 WO1988001437A1 (en) 1986-08-20 1987-08-20 Integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8620291A GB2194388A (en) 1986-08-20 1986-08-20 Integrated circuit devices

Publications (2)

Publication Number Publication Date
GB8620291D0 GB8620291D0 (en) 1986-10-01
GB2194388A true GB2194388A (en) 1988-03-02

Family

ID=10602999

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8620291A Withdrawn GB2194388A (en) 1986-08-20 1986-08-20 Integrated circuit devices

Country Status (2)

Country Link
GB (1) GB2194388A (en)
WO (1) WO1988001437A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907065A (en) * 1988-03-01 1990-03-06 Lsi Logic Corporation Integrated circuit chip sealing assembly
DE3851335D1 (en) * 1988-12-05 1994-10-06 Heinz Karl Diedrich Vacuum container for cryogenically cooling a package for an electronic assembly.
JP2726141B2 (en) * 1990-06-05 1998-03-11 三菱電機株式会社 Semiconductor device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0007993A1 (en) * 1978-07-12 1980-02-20 Siemens Aktiengesellschaft Conductor plate for mounting and electrically connecting semiconductor chips
US4246597A (en) * 1979-06-29 1981-01-20 International Business Machines Corporation Air cooled multi-chip module having a heat conductive piston spring loaded against the chips
US4561011A (en) * 1982-10-05 1985-12-24 Mitsubishi Denki Kabushiki Kaisha Dimensionally stable semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2312172A1 (en) * 1975-05-22 1976-12-17 Ibm Monolithically integrated circuits assembly production - involves large monocrystal substrate with metallic pattern and pin soldering system
JPS58143556A (en) * 1982-02-22 1983-08-26 Fujitsu Ltd Package for high-density integrated circuit
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0007993A1 (en) * 1978-07-12 1980-02-20 Siemens Aktiengesellschaft Conductor plate for mounting and electrically connecting semiconductor chips
US4246597A (en) * 1979-06-29 1981-01-20 International Business Machines Corporation Air cooled multi-chip module having a heat conductive piston spring loaded against the chips
US4561011A (en) * 1982-10-05 1985-12-24 Mitsubishi Denki Kabushiki Kaisha Dimensionally stable semiconductor device

Also Published As

Publication number Publication date
GB8620291D0 (en) 1986-10-01
WO1988001437A1 (en) 1988-02-25

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)