GB2181890A

GB2181890A - Semiconductor power device

Info

Publication number: GB2181890A
Application number: GB08619843A
Authority: GB
Inventors: Antonio Caruso; Salvatore Musumeci; Paolo Spirito; Gian Franco Vitale
Original assignee: SGS Microelettronica SpA
Current assignee: STMicroelectronics SRL
Priority date: 1985-09-26
Filing date: 1986-08-14
Publication date: 1987-04-29
Also published as: DE3632642A1; DE3632642C2; FR2587842A1; GB8619843D0; IT1202313B; GB2181890B; FR2587842B1; IT8506614A0

Abstract

A semiconductor power device comprises a substrate 1 forming a drain and an epitaxial layer 2 with a concentration of impurities of 4 x 10 EXP 13 atoms/cm<3>, both of first conductivity type. First and second gate regions 3, 4 of second conductivity type are formed in the epitaxial layer and define therebetween a channel 6 of width W less than 10 mu m and length L greater than the width. A source region 5 of first conductivity type is located above the channel and bridges the gate regions 3, 4. The source region has a depth H of more than 1 mu m and a surface concentration of impurities of more than 5 x 10 EXP 18 atoms/cm<3>. The device forms an enhancement bipolar mode field effect transistor capable of withstanding high voltages when turned off while exhibiting low forward resistance and hence saturation voltage drop for high currents during conduction. <IMAGE>

Description

SPECIFICATION Semiconductor power device The present invention relates to semiconductor power devices for instance of the type having vertical current flow between source and drain electrodes controlled by a gate electrode and required to withstand high voltages and to conduct high currents while being capable of being rapidly switched.

It is known that there are static induction devices, such as static induction transistors (SIT), bipolar static induction transistors (BSIT), bipolar junction field effect trans#istors (BJFET). These do not exist, in the current state of the art, as power devices, and, in particular, do not simultaneously satisfy the requirements of possessing both high cut-off or blocking voltages between the drain and source VDS when there is no reverse biasing voltage at the gate, or in the "normally off condition, and very low conduction resistances RONT despite the very high resistivity of the epitaxial layer of the drain region when the biasing voltage at the gate is forward with respect to the drain and a gate current is flowing.

According to the invention, there is provided a semiconductor power device as defined in the appended claim 1. Preferred embodiments of the invention are defined in the other appended claims.

It is thus possible to provide a power transistor of the BMFET type which is normally off having high cut-off voltages and low saturation voltages in which the epitaxial layer of the drain region has a concentration of impurities of less than 4 x 10 EXP 13 atoms/cm3 and a thickness of more than 10,lem, the channel has a width of less than 4 pm and a length greater than its width, and the source region has a surface concentration of impurities of more than 5 x 10 EXP 18 atoms/cm3 and a thickness of more than 1 itm such that the interface between the source region and the channel is reflective for the minority carriers in the epitaxial layer, or in which normally off operation is combined with operation in which the conductivity of the epitaxial layer is modulated.

It is also possible to provide a device in which normally off operation, for a zero gatesource biasing voltage, is associated in conduction, for a gate current or more than zero, with conductivity modulation operation.

It is further possible to provide a device which for a zero gate-source biasing voltage, is normally off and withstands, in these biasing conditions, cut-off voltages of at least 100 V applied between the drain and source.

It is also possible to provide a device which, for forward gate-source biasing voltages and gate currents which are greater than zero, conducts high drain currents over a source-drain path having a very low resistance such that the saturation voltage of the device is very low.

The present invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a section, not to scale, through part of a chip comprising a device constituting a first embodiment of the invention; and Figure 2 shows a section, not to scale, through part of a chip comprising a device constituting a second embodiment of the invention.

The same reference numerals and letters are used for equivalent components in the Figures.

Figure 1 shows a section, not to scale, through part of a chip comprising an N-channel power transistor. An expitaxially grown layer 2 with N-- doping using phosphorus having a concentration of less than 2 x 10 EXP 13 atoms/cm3 corresponding to a resistivity of more than 200 ohm cm, and a growth thickness between 20 and 120 ,um, dimensioned as a function of the source-drain cut-off voltage of the transistor, lies on a substrate 1 of monocrystalline silicon with N++ doping using antimony and having a concentration of 2 x 10 EXP 19 atoms/cm3. The assembly of the substrate 1 and the overlying epitaxial layer 2 forms the drain region of the device.In the particular case of a transistor able to withstand a cut-off voltage of 700 V, the thickness of the epitaxial layer 2 is 60 Am in combination with other characteristics of the device which will be described in detail below.

Two diffused regions 3 and 4, with Pi doping using boron, which are not in contact are located in the transistor below the surface 7 which is partially covered by an insulating layer 8 of silicon oxide. These regions have a depth of 12 ,um in the epitaxial layer 2 below the surface 7 and a surface concentration of 10 EXP 18 atoms/cm3 and together form the gate of the transistor. The narrow space remaining in the epitaxial layer 2, bounded at its edges by the adjacent gate regions 3 and 4, constitutes the channel 6.

A diffused region 5 with N+ doping using phosphorus with a surface concentration of 10 EXP 20 atoms/cm3 and having a depth H = 4 iim which forms the source region of the transistor is located in the epitaxial layer 2 below the surface 7 and is centred on the transistor channel and partially bounded by the gate regions 3 and 4.

The diffused gate regions 3 and 4 and the source region 5 are constructed by ion implantation of the appropriate doping agent and a successive high temperature heat treatment; however, these regions could be constructed using any other technique. The geometry of the channel is therefore well-defined with a width W < 4 Cim and a length L greater than the width W and precisely L = 8 im in the example described.

Via windows provided in the insulating layer 8, metallizations 9 are disposed on the surface 7 to form the source electrode S and metallizations 10, 11 connected in parallel by metal tracks (not shown) to form the gate electrode G. On the surface of the substrate 1 which remains free on the opposite side of the chip, there is disposed metallization 12 which forms the drain electrode D of the power transistor.

The high resistivity of the epitaxial layer 2 and the geometrical configuration of the channel 6 will now be examined.

The minimum distance W between the two adjacent gate regions 3 and 4 is formed to be very small (C < ,um) such that the depletion region in the epitaxial layer 2, due solely to the built-in potential of each PN junction between the adjacent regions 3-2 and 4-2 is far greater than W/2. In this case the channel 6 is completely depleted of moving charges ("pinch-off").

If a sufficiently high value is selected for the resistivity of the epitaxial layer 2 and the length L of the channel 6 is greater than the minimum distance between the gates, the minimum potential of the depletion region in the channel due to the built-in voltage is sufficient to block the flow of majority carriers from the source to the drain by applying a voltage VDS which is positive with respect to the source to the drain region. This takes place, for example, up to a maximum cut-off or blocking voltage of more than 700 V, if the geometrical parameters of the channel 6 have the values W < 4 #m, L = 8 ,um and the epitaxial layer 2, as mentioned above, has a concentration of impurities of less than 2 x 10 EXP 13 atoms/cm3 and a thickness of 60 ,um.

Consequently, in this way the device is cut off even if the gate is not counter-biased with respect to the source: normally off operation.

Bearing in mind that when the gate is zero biased, and even more so when it is reverse biased, with respect to the source, the BMFET transistor is cut off and does not therefore conduct drain current ID, the operation of the transistor in conduction will now be examined bearing in mind that its normal mode of operation in the on state is with the gate forwardly biased with respect to the source.

In conduction, the structure enables the achievement of high current densities and extremely low resistance RON, despite the fact that the resistivity of the channel is very high, if the transition between the source region 5 and the channel 6 is formed such that it is highly reflective for the minority carriers, ie those carriers with a high recombination speed. This is possible by constructing the region 5 with a very high level of doping with respect to that of the expitaxial layer 2, with an abrupt transition between the two doping values and with a thickness R greater than the length of diffusion of the minority carriers in the same region 5.

In the example being described, as mentioned above, the region 5 has a thickness H = 4 #m and a surface concentration of phosphorus of 10 EXP 20 atmos/cm3. In this case, by forwardly biasing the gate with respect to the source, the device operates in a bipolar manner. In effect the gate regions 3 and 4 inject minority carriers into the epitaxial layer 2, which carriers, accumulating at the source 5~channel 6 transition, cause the supplementary injection of majority carriers by the source region 5.Since the channel 6 has a very low level of doping (10 EXP 13 atoms/cm3), high injection conditions are achieved in this channel with an approximately equal density of minority and majority carriers which is much higher than that due to the doping of the epitaxial layer 2, causing the portion of the channel 6 closest to the source region 5 to operate in the plasma zone with a negligible electrical field.

If the potential of the drain region is lower than that of the gate region, the plasma will extend throughout the epitaxial layer 2 of the drain region, giving rise to an extremely low resistance RON in practice independent of the resistivity of the epitaxial layer itself: this produces a phenomenon of conductivity modulation of the epitaxial layer 2.

The BMFET power transistor thus combines the advantages of its normal off operation, with high cut-off voltages, with that of control of conductivity enabling the achievement of very low resistances RON in the conduction state and therefore very low saturation voltages with high currents. The switching times, in the range of tens of nanoseconds, are a further advantage of the device and enable the use of the device for power switching applications in the high frequency range.

Various modifications may be made without departing from the scope of the invention. For example, with reference to Figure 1, a P-channel BMFET transistor could be constructed using the required modifications known to persons skilled in the art.

A modification of the transistor of Figure 1 is shown in Figure 2, which shows a section, not to scale, through part of a chip comprising a BMFET device which differs from the device of Figure 1 in that it has an additional epitaxial layer 21. In other words, two superimposed epitaxial layers are provided between the substrate 1 and the upper insulating layer 8: the first layer 21 lies on the substrate 1 and is doped with N- throughout its thickness, which may vary from 20 to 100 'ism, using phosphorus at a concentration of 10 EXP 14 atoms/cm3 corresponding to a resistivity of 50 ohm-cm; the second layer 2 doped with N-- using phosphorus lies-on the first epitaxial layer 21 and has a resistivity of more than 200 ohm-cm, as noted with reference to the device of Figure 1, and a thickness of 20,us.

In this case, the drain region is formed, in order, by the assembly of the substrate 1, the epitaxial layer 21 and the epitaxial layer 2.

The epitaxial layer 21 is added to improve the electrical switching characteristics of the device and to provide the safe operating area when the gate is reverse biased.

It is evident that the horizontal geometry of the transistor may have any shape as is the case for interdigitated and multicellular structures.

The invention does not relate solely to discrete devices, but also includes any semiconductor device of the type described which is monolithically integrated on a chip.

Claims

1. A semiconductor power device comprising: a substrate of monocrystalline semiconductor material of a first type of conductivity forming a drain; at least one epitaxial layer of the same type of conductivity as the substrate and lying thereon; first and second regions of a second type of conductivity opposite to the first forming a gate and being incorporated in the epitaxial layer, the first and second regions being bounded by an insulating layer which covers an upper surface of the epitaxial layer parallel to the substrate and being spaced from one another so as to define therebetween a channel within the epitaxial layer; a third region of the first type of conductivity forming a source located below the insulating layer and centred on the channel, the third region being in contact with the channel and being partially bounded by the first and second regions; and first, second and third conduction means which establish ohmic contacts with the source, gate and drain, respectively, the epitaxial layer having a concentration of impurities of less than 4 x 10 EXP 13 atoms/cm3 and a thickness of more than 10 Am, the channel having a width, defined as the minimum distance between the first and second regions, of less than 4 ,um and a length, defined as the distance between the base of the third region and the base of the first and second regions, which is greater than the width, and the third region having a depth of more than 1 #m and a surface concentration of impurities of more than 5 x 10 EXP 18 atoms/cm3 so that the interface between the third region and the channel is reflective for minority carriers in the epitaxial layer.

2. A device as claimed in claim 1, in which the epitaxial layer is a layer having a concentration of impurities of less than 4 x 10 EXP 13 atoms/cm3.

3. A device as claimed in claim 2, in which the epitaxial layer has a thickness of more than 10 Am and the device comprises a further epitaxial layer of the first type of conductivity located between the epitaxial layer in which the channel is formed and the substrate and having a higher concentration of impurities than that of the epitaxial layer.

4. A device as claimed in any one of the preceding claims, in which the first type of conductivity is N and the second type of conductivity is P so as to provide an N-channel device.

5. A device as claimed in any one of claims 1 to 3, in which the first type of conductivity is P and the second type of conductivity is N so as to provide a P-channel device.

6. A semiconductor device substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.