GB2179930A - A method of depositing an epitaxial silicon layer - Google Patents
A method of depositing an epitaxial silicon layer Download PDFInfo
- Publication number
- GB2179930A GB2179930A GB8522195A GB8522195A GB2179930A GB 2179930 A GB2179930 A GB 2179930A GB 8522195 A GB8522195 A GB 8522195A GB 8522195 A GB8522195 A GB 8522195A GB 2179930 A GB2179930 A GB 2179930A
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- substrate
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- reaction chamber
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/10—Heating of the reaction chamber or the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
- H01L21/02661—In-situ cleaning
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
Abstract
An epitaxial silicon layer may be deposited on a monocrystalline silicon substrate by Chemical Vapour Deposition at reduced pressure and low deposition temperature by a method which includes cleaning the substrate within the CVD reactor. The cleaning within the reactor is achieved by applying a heat pulse by heating the substrate to a cleaning temperature of 1000-1250 DEG C for not more than 90 seconds. Deposition of the layer is started by introducing silicon carrier gas not more than 15 seconds before the end of the heat pulse. At the end of the heat pulse the substrate temperature is allowed to fall to a desired deposition temperature between 650 DEG C and 800 DEG C for silane and 800 DEG C and 875 DEG C for trichlorsilane. Preferably radiant heating is used to heat the substrate to the cleaning temperature, and the method may be carried out in an existing radiantly heated CVD reactor. The method allows the deposition of layers of low transition depth (D) shown by SIMS profile (3) of the layer (S-I) and doped substrate. <IMAGE>
Description
SPECIFICATION
A method of depositing an epitaxial silicon layer
The present invention relates to a method of depositing an epitaxial silicon layer on a surface of a monocrystalline silicon substrate by chemical vapour deposition at reduced pressure in a reaction chamber.
A method of deposition is known which includes the steps of chemically cleaning the substrate, placing the substrate on a support in a reaction chamber, purging the reaction chamber, reducing the pressure in the reaction chamber, and cleaning the substrate surface within the reaction chamber before depositing the epitaxial silicon layer.
Such a known method is described by T.J.
Donahue and R. Reif in The Journal of Applied
Physics 57(8) 15 April 1985, pp. 2757-2765.
In this known method the substrate is chemically cleaned using a process as described in the RCA Review 31, 187 (1970) and then dipped into 1 part HF diluted with 10 parts
H20 by volume. The chemical cleaning is to remove contaminant species, particularly carbon and metals, from the substrate surface and promote the growth of a silicon oxide layer which is thinned by dipping in the dilute
HF. The cleaned, oxide coated substrate is then placed on a silicon carbide coated graphite support in a quartz reaction chamber which is purged with nitrogen. After purging, the chamber is pumped down and the substrate is heated by radiant heat lamps placed outside the reaction chamber.The substrate was heated to establish a desired deposition temperature between 6500C and 80000 and then cleaned at the deposition temperature for 5 minutes in a radiofrequency (rf) generated argon plasma of SOW power with a 300V dc bias applied to the substrate relative to rf ground. The argon pressure in the reaction chamber was 2 mTorr (0.26Pa). The rf circuit was a Veeco 1kW 13.56MHz generator coupled into the reaction chamber via an automatic matching network and an external copper plate around the reaction chamber.
The deposition of epitaxial silicon films was initiated by introducing silane at a pressure of 2-4 mTorr (0.26-0.52Pa) into the reaction chamber during the argon plasma cleaning of the substrate and the argon plasma was removed by stopping the flow of argon into the chamber. The films were then deposited with the substrate temperature held at the desired value either in a silane plasma of 20W rf power, or with the rf power off. It was reported that increased deposition rates were found for depositions made in the presence of the silane plasma.
The cleaning of the substrate with the argon plasma was found to be a critical step in the process, allowing epitaxial deposition of a silicon layer to take place at substrate temperatures as low as 650 C. If the plasma cleaning of the substrate was not carried out a polycrystalline film was obtained at all deposition temperatures in the range between 65000 and 800 C.
The facility to carry out chemical vapour deposition of epitaxial silicon layers on monocrystalline silicon substrates at temperatures in the range between 65000 and 8000C rather than at the previously used temperatures in the range between 100000 and 120000 is of considerable importance in the manufacture of silicon devices, particularly integrated circuits, because deposition at these lower temperatures greatly reduces the transfer of dopant from the substrate to the layers (known as invasion) and also greatly reduces the diffusion of dopants within the substrate.It is also important that thin layers of accurately controlled thickness may be deposited in an established manufacturing environment without recourse to more complex deposition techniques for the deposition of such thin layers, such as molecular beam epitaxy. That such depositions may be made with chemical vapour deposition equipment which is already widely used in the silicon device and integrated circuit manufacturing environment is a considerable benefit.
According to the present invention there is provided a method of depositing an epitaxial silicon layer on a surface of a monocrystalline silicon substrate by chemical vapour deposition at reduced pressure in a reaction chamber, the method including the steps of chemically cleaning the substrate, placing the substrate on a support in the reaction chamber, purging the reaction chamber, reducing the pressure in the reaction chamber, cleaning the substrate surface within the reaction chamber, and depositing the epitaxial layer, characterised in that the step of cleaning the substrate surface includes the step of applying a heat pulse by heating the substrate to a cleaning temperature between 100000 and 125000 for not more than 90 seconds, and in that during the heat pulse and within a period of 15 seconds prior to the termination of the heat pulse a stream of a silicon carrier gas is introduced into the reaction chamber to commence deposition of the epitaxial layer which deposition continues following the termination of the heat pulse when the substrate temperature is allowed to fall to a desired deposition temperature for depositing the remainder of the layer.
With a method in accordance with the invention various advantages are to be gained from the facility to deposit epitaxial layers on a monocrystalline silicon substrate. First, the substrate surface does not require chemical treatment to reduce the thickness of the protective oxide coating generated by the chemical cleaning. The retention of the thicker oxide layer reduces the risk of surface contamination during placing the substrate in the reaction cham ber. Second, the cleaning step within the reaction chamber is effected by a simple heating procedure, without the need for the generation of a plasma within the reaction chamber to clean the substrate, and third the cleaning time is reduced to a maximum of 90 seconds in contrast to the 5 minute plasma cleaning time used hitherto.
The silicon carrier gas may be silane and the desired deposition temperature at which the remainder of the epitaxial layer may be deposited is a temperature between 6500C and 800 C. It has been found that the method in accordance with the invention allows the deposition of epitaxial layers on a substrate by the decomposition of silane at a temperature as low as 6500C without the need for plasma cleaning of the substrate surface.
The silicon carrier gas may be trichlorsilane and the desired deposition temperature at which the remainder of the epitaxial layer may be deposited is a temperature between 8000C and 875 C. It has been found that the method in accordance with the invention allows deposition of epitaxial layers on a substrate by the decomposition of trichlorsilane at a temperature as low as 800 C. The presence of chloring and hydrogen chloride gas in the reaction chamber after decomposition to trichlorsilane assists the retention of a clean surface on which the epitaxial deposition progresses.
The substrate may be heated to the cleaning temperature between 1 0000C and 1 2500C by a radiant heat source. Thus the cleaning of the substrate may be accomplished with only the radiant heating source in contrast to the known method which requires the radiant heat source and a source of rf power to generate an argon plasma for the cleaning step.
Before the cleaning step the substrate may be preheated to an elevated temperature, possibly the desired deposition temperature for the epitaxial silicon layer before the step of cleaning the substrate within the reaction chamber and this heating to an elevated temperature may be accomplished by the radiant heat source used to heat the substrate to the cleaning temperature. The preheating may be used to advantage to adjust the heating power to ensure a stable deposition temperature after the heat pulse. Where the preheating is by radiant heating of the substrate the cleaning temperature may be achieved by increasing the radiant heating power.In the manufacture of silicon devices there is the advantage of faster throughput to be gained from the shorter substrate cleaning time and a cost advantage to be gained if the cleaning step in accordance with the invention may be carried out in an ~existing radiantly heated reaction chamber.
Embodiments of the method of depositing an epitaxial silicon layer in accordance with the invention will now be described, including one non-limiting Example, with reference to the drawings, in which:
Figure 1 shows schematically in cross section an epitaxial silicon layer on a surface of a monocrystalline silicon substrate,
Figure 2 is a secondary ion mass spectroscopy depth profile of part to a silicon substrate and an epitaxial silicon layer deposited thereon by a method in accordance with an embodiment of the invention described in the
Example.
In Fig. 1-a part 10 of a monocrystalline silicon substrate has on a surface 9 an epitaxial silicon layer 11 grown by a method in accordance with the invention. The method in accordance with the invention allows growth to the epitaxial layer to be made in a manner in which the resulting invasion of any dopant species present in the substrate 10 into the layer 11 is minimised. The extent of invasion is characterised by a transition depth D, which is defined as the depth of expitaxial layer required for the invading dopant species concentration to decay to a value two orders of magnitude below the concentration of dopant species in the substrate or from 1025m -3 to 1023m 3 if the concentration of dopant species in the substrate is greater than 1025m-3.
Example
A 0.05m diameter arsenic doped monocrystalline silicon substrate with an arsenic concentration of 2.4X1025 As m-3 was chemically cleaned using a process as described in the
RCA Review 31,187 (1970) then placed on a support in a chemical vapour deposition reaction chamber. The support was a body of silicon carbide coated graphite which has previously been coated with polysilicon. The reaction chamber was then purged with nitrogen and the pressure in the chamber was reduced to the base pressure of 0.25 Pa. After backfilling and purging the reaction chamber with hydrogen, the substrate was heated by radiant heaters to the temperature of 7500C the desired deposition temperature for the epitaxial silicon layer.With the hydrogen pressure in the reaction chamber at 6 Pa the substrate surface was cleaned by a heat pulse by radiantly heating the substrate to 1 0500C for a period of 50 seconds. After 40 seconds of the heat pulse cleaning of the substrate surface the hydrogen was turned off and simultaneously a stream of silane at a pressure of 6Pa was introduced into the reaction chamber to commence deposition of the epitaxial layer.
Thus the silane was present for a period of 10 seconds up to the end of the heat pulse.
At the end of the heat pulse the substrate temperature was allowed to fall to the desired deposition temperature of 7500C and the depositon of the epitaxial silicon layer proceeded for 30 minutes from the introduction of the silane. The silicon layer was thus deposited in three consecutive periods, The first for 10 seconds at the cleaning temperature of 1 0500C, the second for approximately 200 seconds while the substrate temperature fell from 10500C to 7500C and the third for approximately a further 26 minutes 30 seconds at the desired deposition temperature of 7500C while the remainder of the layer was deposited. The thickness of the epitaxial layer was found to be 0.87 micrometres, deposited at an average rate of 1.74 micrometres per hour.Comparative experiments using identically prepared substrates with the same deposition technique, except that the time at the desired deposition temperature was different from that in the Example, showed that the rate of deposition at the desired deposition temperature of 7500C wa approximately 1.2 micrometres per hour. Thus in the layer deposited as described in this Example about 0.27 micrometres were deposited during the first and second temperature periods, and the remainder of the layer of about 0.6 micrometres was deposited during the third temperature period at the desired deposition temperature.
An electron channelling pattern analysis of the layer showed it to be epitaxial with the substrate and a secondary ion mass spectroscopic (SIMS) depth profile of the epitaxial layer and underlying substrate was made to determine the arsenic dopant concentration profile across the epitaxial layer-substrate surface interface as shown in Fig. 2. The abscissa 1 of Fig. 2 represents depth from the surface of the epitaxial layer measured in micrometres, the ordinate 2 represents the concentration of arsenic atoms on a logarithmic scale in atoms per cubic metre.S on the abscissa represents the position of the surface of the epitaxial layer, I represents the position of the interface between the epitaxial layer and the substrate surface for the 0.87 micrometre thickness epitaxial layer and T the 0.6 micrometres remainder of the layer grown at the desired deposition temperature of 750 C. Curve 3 represents the arsenic concentration; the isotope of arsenic used in the SIMS profile has an atomic weight M equal to 75. The transition depth D, between invading dopant concentrations of 1025m 3 and 1023m 3 in the epitaxial layer, is 0.05 micrometres.Thus a layer deposited by a method in accordance with the invention as described in this Example is epitaxial and exhibits a transition depth D of 5.7% of the measured thickness of the layer despite the deposition of this part of the layer during the first and second temperature periods at a higher temperature than the desired deposition temperature.
At present the rate of cooling from the cleaning temperature to the desired deposition temperature is limited by the thermal inertia of the reactor. It is postulated that a further reduction of the cooling time from the cleaning temperature to the desired deposition temperature would yield a corresponding reduction in the transition depth.
In order to demonstrate the efficacy of a method in accordance with the invention, an attempt was made to deposit an epitaxial layer on a similar silicon substrate, by using the method described in the Example but which omitted the step of cleaning the substrate by the heat pulse. This resulted in there being no measurable deposition of epitaxial silicon.
Further experiments to deposit a silicon epitaxial layer by the decomposition of silane on a surface of a monocrystalline silicon substrate have been made by a method in accordance with the invention. In these experiments various cleaning times between 15 and 90 seconds were used, the period prior to the end of the heat pulse during which silane was introduced was varied up to 15 seconds and the desired deposition temperature was varied between 6500C and 800 C. In all the experiments electron channelling pattern analysis indicated that epitaxial layers had been deposited at substrate temperatures between 6500C and 800 C. The deposition rate at 6500C was found to be 0.15 micrometres per hour which may be too slow for some applications of the method, and the deposition rate was found to increase by approximately 10 times for each 1 000C rise in temperature between 6500C and 800 C. Similar experiments using trichlorsilane showed that epitaxial layers were deposited at substrate temperatures between 8000C and 875"C.
No- correlation was found between either the length of time of substrate cleaning between 15 and 90 seconds or the length of time the silicon carrier gas stream was present during the cleaning, or the desired deposition temperature, or the cleaning temperature. However, if the cleaning step was omitted there was no deposition of an epitaxial silicon layer.
The minimum time of 15 seconds for the cleaning step employed in these experiments was imposed by the power available for the radiant heaters and by the thermal inertia of the reaction chamber, not by any limit to the effectiveness of the cleaning step. Cleaning step times of less than 15 seconds, and a reduction in the time taken for the substrate temperature to fall from the cleaning temperature to the desired deposition temperature may advantageously be employed in a method in accordance with the present invention and may be achieved with a radially heated reactor adapted from a radiantly heated rapid annealing furnace such as that described in GB Patent Application 2136937 (Philips Electronics and Associated Industries Ltd).
There are a number of known means by which the substrate may be heated, including induction heating, resistive heating and radiant heating. Radiant heating is to be preferred in that it can provide the most rapid heating for the substrate as it may be used to heat the substrate directly without the need for a sus ceptor as is required in induction heating, or a heater body as is required in resistive heating.
The method in accordance with the invention is not to be considered limited to the deposition of undoped epitaxial layers on doped substrates as shown in the Figures and described in the Example. A method in accordance with the invention may be used for the deposition of doped epitaxial layers by the introduction into the reaction chamber of an appropriate dopant carrier gas.
Claims (8)
1. A method of depositing an epitaxial silicon layer on a surface of a monocrystalline silicon substrate by chemical vapour deposition at reduced pressure in a reaction chamber, the method including the steps of chemically cleaning the substrate, placing the substrate on a support in the reaction chamber, purging the reaction chamber, reducing the pressure in the reaction chamber, cleaning the substrate surface within the reaction chamber, and depositing the epitaxial layer, characterised in that the step of cleaning the substrate surface includes the step of applying a heat pulse by heating the substrate to a cleaning temperature between 1 0000C and 1 2500C for not more than 90 seconds, and in that during the heat pulse and within a period of 15 seconds prior to the termination of the heat pulse a stream of a silicon carrier gas is introduced into the reaction chamber to commence deposition of the epitaxial layer which deposition continues following the termination of the heat pulse when the substrate temperature is allowed to fall to a desired deposition temperature for depositing the remainder of the layer.
2. A method as claimed in Claim 1, in which the silicon carrier gas is silane and the desired deposition temperature at which the remainder of the epitaxial silicon layer is deposited is a temperature between 6500C and 800 C.
3. A method as claimed in Claim 1, in which the silicon carrier gas is trichlorsilane and the desired deposition temperature at which the remainder of the epitaxial silicon layer is diposited is a temperature between 8000C and 850 C.
4. A method as claimed in any preceding claim, in which the substrate is heated to the cleaning temperature by a radiant heat source.
5. A method as claimed in any preceding claim, in which the substrate is preheated within the reaction chamber to an elevated temperature before the step of cleaning the substrate surface within the reaction chamber.
6. A method as claimed in Claim 5, in which the substrate is preheated to the desired deposition temperature.
7. A method as claimed in Claim 5 or
Claim 6, in which the substrate is preheated by the radiant heat source used to heat the substrate to the cleaning temperature.
8. A method of depositing an epitaxial silicon layer on a monocrystalline silicon substrate as herein described with reference to the Example and Figs. 1 and 2.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8522195A GB2179930A (en) | 1985-09-06 | 1985-09-06 | A method of depositing an epitaxial silicon layer |
| DE8686201493T DE3684539D1 (en) | 1985-09-06 | 1986-09-01 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE. |
| EP19860201493 EP0214690B1 (en) | 1985-09-06 | 1986-09-01 | A method of manufacturing a semiconductor device |
| US06/904,090 US5011789A (en) | 1985-09-06 | 1986-09-04 | Method of manufacturing a semiconductor device |
| JP61208086A JPH0736387B2 (en) | 1985-09-06 | 1986-09-05 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8522195A GB2179930A (en) | 1985-09-06 | 1985-09-06 | A method of depositing an epitaxial silicon layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8522195D0 GB8522195D0 (en) | 1985-10-09 |
| GB2179930A true GB2179930A (en) | 1987-03-18 |
Family
ID=10584843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8522195A Withdrawn GB2179930A (en) | 1985-09-06 | 1985-09-06 | A method of depositing an epitaxial silicon layer |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2179930A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB837205A (en) * | 1955-07-29 | 1960-06-09 | Wacker Chemie Gmbh | Process for the manufacture of very pure silicon |
| GB1062968A (en) * | 1963-08-22 | 1967-03-22 | Texas Instruments Inc | Process for epitaxial crystal growth |
| GB1071412A (en) * | 1963-02-14 | 1967-06-07 | Texas Instruments Ltd | Improvements in or relating to epitaxial deposition of silicon |
| GB1117359A (en) * | 1965-07-22 | 1968-06-19 | Ass Elect Ind | Improvements relating to semiconductor elements |
| GB1234179A (en) * | 1969-02-27 | 1971-06-03 | ||
| GB1243890A (en) * | 1968-08-14 | 1971-08-25 | Siemens Ag | Improvements in or relating to the epitaxial deposition of inorganic material on a surface of a silicon crystal |
| GB1338403A (en) * | 1969-11-06 | 1973-11-21 | Union Carbide Corp | Production of silicon from dichlosilane |
| GB1532649A (en) * | 1974-12-26 | 1978-11-15 | Monsanto Co | Production of polycrystalline silicon |
-
1985
- 1985-09-06 GB GB8522195A patent/GB2179930A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB837205A (en) * | 1955-07-29 | 1960-06-09 | Wacker Chemie Gmbh | Process for the manufacture of very pure silicon |
| GB1071412A (en) * | 1963-02-14 | 1967-06-07 | Texas Instruments Ltd | Improvements in or relating to epitaxial deposition of silicon |
| GB1062968A (en) * | 1963-08-22 | 1967-03-22 | Texas Instruments Inc | Process for epitaxial crystal growth |
| GB1117359A (en) * | 1965-07-22 | 1968-06-19 | Ass Elect Ind | Improvements relating to semiconductor elements |
| GB1243890A (en) * | 1968-08-14 | 1971-08-25 | Siemens Ag | Improvements in or relating to the epitaxial deposition of inorganic material on a surface of a silicon crystal |
| GB1234179A (en) * | 1969-02-27 | 1971-06-03 | ||
| GB1338403A (en) * | 1969-11-06 | 1973-11-21 | Union Carbide Corp | Production of silicon from dichlosilane |
| GB1532649A (en) * | 1974-12-26 | 1978-11-15 | Monsanto Co | Production of polycrystalline silicon |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8522195D0 (en) | 1985-10-09 |
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|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |