GB2170627A

GB2170627A - Improvements in and relating to the design of multiplier circuits

Info

Publication number: GB2170627A
Application number: GB08602553A
Authority: GB
Inventors: Robin Bransbury
Original assignee: Individual
Current assignee: Individual
Priority date: 1985-02-04
Filing date: 1986-02-03
Publication date: 1986-08-06
Also published as: GB8602553D0; GB8502801D0

Abstract

A multiplier circuit comprising an input stage (A1, Q1, Q2) creating an electrical output signal (at B) representing the log of an electrical input signal (Vin) and an output stage (Q3, Q4) creating an electrical signal (Vout) representing the anti-log of the output signal from the input stage includes matched pairs (Q1, Q3) (R7, R2); (Q2, Q4) (R8, R3) so that any error introduced in the process of creating the log-related output signal of the input stage implies a similar error in the process of creating the anti-log signal of the output stage in a manner to at least reduce, and at best cancel out, the errors. Ports W & Z are driven in one sense, ports X & Y being driven in the opposite sense to change the level of the log signal. The input may be an audio waveform. <IMAGE>

Description

SPECIFICATION Improvements in and relating to the design of multiplier circuits This invention relates to a multiplier circuit and in particular to a trans-conductance multiplier circuit. The invention has considerable utility in the field of the processing of electrical signals derived from audio inputs but can be used whenever an input signal requires to be multiplied with low distortion by a factor less than equal to or greater than unity.

It is known (e.g. from US Patent 3714462) to make a multiplier circuit from an input stage creating the log of an input signal and an output stage creating the antilog of the output from the input stage but heretofore there has been no interrelation between the two stages for the compensation of terrors.

This invention relates to a multiplier circuit of novel topology whereby errors in the process of taking the logarithm of an input signal are imposed on the process of taking the exponent in a manner to at least reduce and at best cancel the errors out.

The invention also embraces circuitry to stabilise the multiplier circuit against temperature changes.

The invention is illustrated, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a first embodiment of transconductance multiplier circuit, Figure 2 shows one form of temperature compensating circuit for use with the circuit of Figure 1, Figure 3 shows a second embodiment of multiplier circuit, and Figures 4 and 5 show modifications which can be made to the circuit of Figure 3.

In Figure 1, Al and A2 are high gain operational amplifiers, the amplifier Al being a noninverting buffer amplifier, and the amplifier A2 an inverting buffer amplifier. I+ is a positive bias current and I- is a negative bias current.

For normal purposes, I+ and I- are provided by suitably valued resistors R4 and R6 from positive and negative supply rails V+ and V-.

Considering firstly the long tailed pair of transistors 01 and Q3; these transistors are a very well matched pair of PNP bipolar transistors. The signal Vin is buffered by the amplifier Al and drives both bases thereof through similar resistors R2 and R7.

The signal Vin is imposed on the point A by the emitter follower action of Q1 and 03 giving a signal there which is almost of the same magnitude as the driving signal at the point B. The signal at the point B is also driving the base of the transistor Ol so there is only a very small differential signal across the base emitter junction which is moving in sympathy with the signal at B, thus turning the transistor Q1 "off" for positive excursions of Vin and "on" for negative excursions.

This differential signal (Vdiff) thus modulates the collector current Ic of the transistor Ol according to the classical relationship for a transistor: q . Vdiff Ic= lo e KT (for collector currents above 1 nA) where q is the charge on an eiectron K is Soltzmann's constant and T is the absolute temperature in degrees Kelvin.

The collector current thus forms a modulated negative feedback path into the non-inverting input of the amplifier Al which is exponential with respect to the magnitude of Vdiff. So the feedback is greater, the larger is the negative signal at Vin.

So the action of the long tailed pair 01/03 is to accomplish a logarithmic function on Vin at the output of the amplifier Al by virtue of the differential voltage across the base emitter junction of the transistor Q1.

Assuming the transistor 03 has been selected to be identical to the transistor 01 and that resistor R7 is a close match to the resistor R2; the differential voltage across the base emitter junction of the transistor 03 will be very similar to that across the transistor 01.

In this way, the collector current of the transistor 03 will be modulated in the same way as the collector current of the transistor 01.

However, it will be operating on the emitterfollowed replica of the signal at B which, as is explained above, is the logarithm of the input signal Vin. Thus the transistor Q3 performs the exponent function of the logarithm of the input signal and thus yields a signal at the output of A2 which is very close indeed to being a linear function of the signal Vin.

By selecting the resistors R2, R5 and R7 to have reasonably low values, in the region of 50 to 500 ohms, the two differential base emitter voltages across the base emitter junctions of the transistors Q1 and 03 will fall almost entirely across the junctions themselves, making the non linear properties of the junctions the dominant effect in the feedback loop and the subsequent exponential loop into the amplifier A2.

Any actual or potential error in the true logarithmic nature of the signal at the point A imposes an extra error on the exponential feedback through the transistor Owl so when the slight error caused by the resistance of the resistors R2 and R5 is passed through the amplifier Al, it gives a similar but opposite error on the signal at point B, cancelling out the error. Thus linearity of the current from the transistor Q3 depends almost entirely on the matching of the resistor R2 to the resistor R7 and the transistor (91 to the transistor Q3.

The same principle of action applies to the second network formed by the transistors 02 and 04, and the resistors R3, R5, R6 and R8.

This network handles the negative excursions in Vin and prevents changes in the operating points of the complementary transistors from affecting the static conditions of the amplifiers Al and A2. The transistors 02 and Q4 require similarly close matching as to that undertaken in the selection of the transistors Q1 and 03.

By adding control ports at W, X, Y and Z, linear offsets to the log/exponent action of the circuit can be obtained. In effect, by driving ports W and Z in the same sense and driving ports X and Y in the same sense but with opposite polarity to the drive to the ports W and Z, the output becomes a function of both the input signal and the magnitude of either or both port drives. It is found that the function produced by operating on the input signal with linear control drives gives an almost perfect fit to logarithmic control. If the multiplier of Figure 1 is used to control an audio waveform, a linear control change gives a change in output which is almost exactly related to the dB's per unit change in drive signal.

The sense of the drive signals is such that when ports W and Z are driven positive while ports X and Y are driven negative, both with respect to ground potential, the circuit increases its amplification. For the reverse case, the opposite is true. Where the matching between the transistor pairs is not perfect, individual ports can be driven with small offsets which gives a first order fit to a perfectly linear transfer characteristic.

The resistor R5 is shown as being a variable component so that the static balance of the upper and lower halves of the circuit can be set up equipotentially above and below ground potential.

For critical operating conditions, 1+ and Ican be made to be proportional to the operating temperature of the transistors 01 to 04, such that when the temperature of these transistors changes by 1"C, the currents l+ and I- drop by 0.33%, preserving a voltage drop across the points A to C of the two base/emitter voltages (Vbe) appropriate to the semiconductor devices used as 0l to 04. A detail of a suitable circuit for temperature stabilisation is shown in Figure 2.

OS and 06 are semiconductor devices with similar geometry to the devices 01 and 03.

07 and 08 are semiconductor devices with similar geometry to the devices 02 and Q4.

With the values shown, the devices Q5 and Q7 act as Vbe multipliers with collector currents of about 2mA. With reasonable matching and thermal linkage between devices 06 and Q8 respectively, the resistors R15 and R16 will have one Vbe dropped across each.

By selecting the resistors R1 5 and R1 6 (between 100 and 500 ohms) the collector currents of the devices Q6 and 08 will provide suitable currents 11 and 12 which will, if the devices Q5 to 08 are in close thermal linkage with the devices 01 to 04, have the required temperature coefficient.

From the foregoing it will be appreciated that by virtue of the circuit topology shown in Figure 1 any error in the process of taking the logarithm of the input signal is imposed on the process of taking the exponent such that the error is cancelled out.

An alternative biassing circuit is shown in Figure 3, consisting of devices 09 and 010 which are PNP and NPN bipolar transistors respectively.

In this embodiment, if transistor Q9 is selected to be a very good match to the transistor pair Ol and 03, the offsets on points W Z are zero, Vin is zero and the inverting input of the amplifier Al is taken to ground, the non-inverting input of amplifier Al becomes a current summing point with its feedback path formed by the transistor 01.

The base of transistor Q9 is at ground potential so its emitter will be one Vbe above ground, as are the emitters of Ol and 03.

The collector currents of transistors 09, Q1 and Q3 will thus divide the part of current l+ which does not flow through resistor R5 according to the exponent of their base emitter voltages. Neglecting the base current through resistors R2 and R7, the transistors Ol and 03 are being driven from a common voltage point (B) and as they are well matched, their collector currents are very similar. The negative feedback round the amplifier Al forces point B to be ground potential so, for the conditions mentioned above, the three devices share the current more or less equally; the better the match, the more equal the collector currents will be.The extra offset provided by the base current through resistors R2 and R7 does have an effect where the hfe of the devices is low and so they should be selected for the highest practical gain possible in the range of collector currents of interest. Compensation for the effect of base current can be provided by taking the base of transistor Q9 to ground via a resistor of the same value as R2 (=R7), so that the offset caused is minimised. This resistor is shown as RB1 in Figure 3. The similar resistor connected to the base of transistor Q10 is shown as RB2.

Where a change in temperature occurs which causes the effective base-emitter voltages of transistors 01, 03 and Q8 to change, close thermal coupling between the devices will cause the collector currents to track each other given that the change in voltage across resistor R4 produced by the small change in Vbe can be neglected in comparison with the value of V+. As V+ is usually a high voltage (+10 to +20 V) this is indeed the case.

The foregoing is also true with appropriate reversal of signs and polarities for the lower half of the circuit which involves the transistors Q2, Q4 and 010.

With the embodiment of the circuit shown in Figure 3, the value of resistor R5 is usually made higher than that used for resistor R5 in Figure 1. A typical value would lie between 500 ohms and 2K ohms total resistance.

As the thermal correction in the arrangement of Figure 3 is effected between the emitters of the transistors, there is no need for thermal correction of the bias currents as shown in Figure 2.

Where the HF gain in amplifier Al is substantial, it has been found that to preserve H.F. stability, it is usually necessary to place some local feedback round the stage as is shown in Figure 4. In Figure 4 the connection of the inverting input directly to ground is replaced by a resistor R17 of fairly low value (100 ohms to 10K) and connecting this input to the output via a network of a fairly high resistor R18 (10K to 1M) with a lead compensation capacitor C1 (and possibly also a resistor R19) in parallel.

Where the thermal offsets have to be very closely controlled, a second set of transistors can be placed- in parallel with transistors 09 and 010 and the current 1+/I- increased to compensate for their collector currents. These extra devices are then used to sense the small changes in temperature between the active devices (Q1 and Q3 and 02 and 04) in the same manner as for Q9 and Q10.

Where the circuit is assembled on thick film, thin film or directly diffused into a silicon wafer, there may be several devices making up Ol to Q4 and 09 and 010 which are arranged in a matrix so that any thermal effect on one part of the array is nullified by its effect on an adjacent device.

Where there is a substantial difference between the HF hfe of the upper and lower halves of the circuit, as is found in integrated versions where the HF hfe of the PNP devices may be one half or less that of the NPN half, extra base drive to the PNP half can be obtained as shown in Figure 5 where resistors R20 and R21 are around 100 ohms to 500 ohms and capacitor C2 has a value between 100 pF and 2000 pF.

The circuits shown in Figures 1 and 3 have a number of significant advantages: 1: Distortion products are very low, in the order of 100 ppm at high frequencies (around 20 KHz) and 20 dS loss.

2: Frequency and pulse response are dictated largely by the performance of the operational amplifiers used.

3: With good thermal coupling between the active devices, thermal offsets cause only offsets at the output rather than distortion products in the output.

Even using small geometry transistors, the signal to noise ratio of the circuit shown in Figure 1 is at least 100 dB in the audio band.

However, by adding the biassing circuit described in my UK Patent Application No.

2156175 where the FET lies across points A and C and the rectifier stage is driven from the input terminal after buffering, the ratio can be improved by some 20 dB, thus giving a VCA with extremely high performance.

Claims

1. A multiplier circuit comprising an input stage creating an electrical output signal representing the log of an electrical input signal and an output stage creating an electrical signal representing the antilog of the output signal from the input stage and means to impose any error introduced in the process of creating the log-related output signal of the input stage on the process of creating the anti-log signal of the output stage in a manner to at least reduce, and at best cancel out the errors.

2. A multiplier circuit as claimed in claim 1, in which the input is fed to an amplifier and error reduction is effected using transistors as inverting elements in the feedback circuit of a non-inverting input of the input amplifier.

3. A multiplier circuit as claimed in claim 1 or claim 2, in which the output stage comprises a pair of transistors, the bases and emitters of which are driven in such a manner as to minimise the inaccuracies of antilog conversion performed by the output stage.

4. A multiplier circuit as claimed in claim 1, in which first and second long-tailed pairs of transistors are respectively used for the log conversion in the input stage and for anti-log conversion in the output stage, the collectors of the first pair being connected to the input of a non-inverting amplifier and the collectors of the second pair being connected to the input of an inverting amplifier.

5. A multiplier circuit as claimed in claim 2, in which the inverting elements in the input stage are linked to the transistors of the output stage by emitter coupling and base drive.

6. A multiplier circuit as claimed in claim 4, in which the emitters of the first pair of transistors are connected to the emitters of the second pair of transistors and means is provided to adjust the relative potentials of the respective connected emitters with respect to ground potential.

7. A multiplier circuit as claimed in any preceding claim, in which means is provided to automatically adjust a thermally sensitive bias current in a manner to reduce the effect of thermal sensitivity of the circuit components.

8. A multiplier circuit as claimed in claim 7 when dependent on claim 4, in which the emitters of the first pair of transistors are connected to the emitters of the second pair of transistors, the transistors in each set of two transistors whose emitters are connected to gether being substantially identical, and in which temperature stabilisation of each set is effected with an additional circuit having a further pair of transistors for each set, the four transistors in each further pair and set being substantially identical and being in close thermal linkage.

9. A multiplier circuit as claimed in claim 7 when dependent on claim 4, in which the emitters of a first pair of substantially identical PNP main circuit transistors are connected together and the emitters of a second pair of substantially identical NPN main circuit transistors are connected together, each connected pair of emitters being connected to the emitter of a supplementary bias transistor substantially identical to those of the respective pair, a resistor being located in the base circuit of each supplementary bias transistor which is substantially identical to the base circuit resistor of each of the transistors in the respective pair of main circuit transistors.

10. A multiplier circuit as claimed in claim 2, in which the gain of the input stage is reduced by local feedback via a feedback loop comprising a parallel connection of a resistor and a capacitor in series with a grounded resistor.

11. A multiplier circuit as claimed in claim 10, in which the capacitor in the feedback loop is in series with a resistor.

12. A multiplier circuit as claimed in claim 4, in which the first pair are PNP transistors and the second pair are NPN transistors and in which the base drive to the PNP transistors of the first pair is adjusted in a manner proportional to the frequency of the input signal so that the difference between the high frequency performance of the NPN and PNP devices is minimised.

13. A multiplier circuit as claimed in claim 12, in which the output of the non-inverting input amplifier is connected to the linked emitters of the first pair by a parallel connection of a capacitor and a resistor and is connected to the linked emitters of the second pair by a resistor.

14. A multiplier circuit substantially as hereinbefore described with reference to, and as illustrated in Figure 1 of the accompanying drawings.

15. A multiplier circuit as claimed in claim 14 when modified as hereinbefore described with reference to Figure 2 of the accompanying drawings.

16. A multiplier circuit substantially as hereinbefore described with reference to, and as illustrated in Figure 3 of the accompanying drawings.

17. A multiplier circuit as claimed in claim 14 or claim 16 when modified by the circuit shown in Figure 4 or the circuit shown in Figure 5.