GB2165013A - Vehicle anti-lock braking control - Google Patents

Abstract

A vehicle anti-lock brake control system includes wheel speed sensors (S1 to S4) which input speed signals to a microprocessor (11) via an interface circuit (10). The microprocessor is programmed to calculate the deceleration (eg 301, 302, 303) of each wheel, compare this with a variable threshold (300, 304) and output a signal to a brake release device (A, B, C) for as long as the deceleration exceeds the threshold. The threshold level is calculated by the microprocessor as a function of the time elapsed since the threshold deceleration is first exceeded. initially the threshold is relatively low, but rises in steps with time elapsed (300). After a predetermined time interval the threshold (304) falls to a new relatively low level which depends on the slip of the wheel and may be a low acceleration. If the slip of the wheel remains higher than a set level following re-application of the brake, a low "fast re-trigger" threshold level is established so as to release the brakes again rapidly if excessive deceleration is again detected or expected acceleration levels are not attained. <IMAGE>

Description

SPECIFICATION Vehicle anti-lock braking control This invention relates to a vehicle anti-lock brake control system of the generally known kind in which the deceleration of a wheel is measured and the brake on that wheel is released if the deceleration exceeds a set threshold.

With such systems there have been many previous attempts to solve the problem of ensuring that the brakes are re-applied as soon as possible after they are released so as to ensure maximum braking efficiency irrespective of the nature of the surface on which the vehicle is running, the condition of the vehicle tyres, the braking effort applied by the driver and other variables. The various approaches to this problem have included setting a fixed delay from the instant when the excessive deceleration is detected and re-engaging the brakes at the end of this delay, sometimes with the refinement that the brakes are overridingly re-applied when a wheel re-acceleration is detected. Although simple, this approach cannot cope with the wide variety of conditions which can exist.It has also been proposed to set a variable delay in accordance with the rate of change of deceleration at the time of detection of the excess deceleration, but, once again this method is not sufficiently reliable in the face of road noise to ensure good efficiency in a wide variety of conditions.

To ensure early detection of the incipient skid condition it is desirable to set the deceleration threshold at a low level, but this increased sensitivity ofthe system exacerbates the problem of brake re-application timing. One proposal to overcome this problem is described in U.S.Patent No. 4,223,957 in which a wheel speed signal is supplied to a first deceleration sensing switch setting a low deceleration threshold for initial brake release and also supplied to a second deceleration sensing switch by a charge storage capacitor. Detection of an incipient skid by the first switch, sets the second switch which is reset following the discharge from the charge storage capacitor of charge it accumulates dependent on the dip in wheel speed.Although this arrangement is an improvement on many of the earlier systems, it still lacks the ability to cope with widely varying conditions.

It is an object of the present invention to provide a vehicle anti-lock brake control system in which brake application timing is effected in a manner which permits high braking efficiency in a wide variety of conditions.

In accordance with the invention there is provided a vehicle anti-lock brake control system comprising wheel speed sensing means for generating a signal dependent on wheel speed, means for operating on said wheel speed signal to generate a signal dependent on the rate of change of wheel speed, means for comparing said rate of change signal with a threshold signal and providing a brake release output signal for as long as said rate of change signal represents a wheel deceleration in excess of a threshold represented by said threshold signal, and means for generating said threshold signal such that if the brake release output signal persists for more than a predetermined time period, the threshold signal is changed from a level representing a relatively high wheel deceleration to a new level representing a relatively low wheel deceleration or even a low acceleration in extreme cases, said new level being dependent on wheel slip (i.e. the difference between wheel speed and a vehicle reference speed derived from a combination of the speed of the wheels of the vehicle).

An example of the invention is shown in the accompanying drawings in which: Figure lisa block diagram showing an example of brake control system featuring the invention; Figure2 is a block diagram of an interface circuit included in Figure 1; Figure 3 is a flow chart showing the overall structure of a main routine of a programme stored in a microprocessor included in Figure 1; Figure 4 is a flow chart showing an interrupt routine of the programme; Figures 5a to 5dare flow charts showing more detail of parts of the main routine; Figures 6to 8 are graphs illustrating operation of the control system in various modes of operation; and Figure 9 shows a modification to Figure 5b.

Referring now to Figure 1 the system includes four wheel speed sensing devices S1,S2. S3 and S4 which are of the well known kind which emit a pulse train at a frequency proportional to wheel speed. These sensing devices are connected to an interface circuit 10 to a microprocessor circuit 11 which, in this example, is a Motorola Microcomputer Type Mc6801. The interface circuit 10 includes an 8-bit counter 21 which counts clock pulses from the microprocessor and a latch 22, 23, 24, 25 for each device S1 to S4 connected to store the count in counter 21 each time a pulse arrives from the associated device S, to S4. The carry-out pulse from the counter (which occurs every tl uS) is applied to the IRQ input of the microprocessor circuit.The interface circuit also includes a latch 26 which indicates whether there has actually been a pulse from any device S1 to S4 since the previous carry-out pulse. The outputs from the latches 22-24 are controlled by the processor 11, via a decoder 27 which receives inputs from Ao A1 and A2 outputs of the processor as well as from an IOS output thereof.

The output of the circuit 11 is applied via an array 12 of power amplifiers to three brake-release solenoids A, B and C which control the release of the brakes at the front left, front right and both rear sides of the vehicle respectively. Afailure detection circuit 13 is connected to the amplifier array 12 and to the circuit 11, but as its function forms no part of the present invention further discussion of this circuit 13 is omitted herefrom.

The microprocessor programme includes a main routine which is shown in outline in Figure 3 and consists simply of an opening step (100) of examining the data collected during the immediately preceding interrupt routine, computing (101 ) the speed of each wheel in turn and storing the speed values derived, and (101a), computing a vehicle speed reference as a function of the wheel speeds, computing (102) the deceleration of each wheel by subtracting the new speed from the previous speed, and then, for each channel, reading to the state flag for that channel and jumping to an appropriate one of the sub-routines shown in Figures 5a, 5b, 5e and 5d.

At the end of these sub-routines the main routine checks (104) whether the data relating to the failsafe circuit is normal. If so, the main routine starts again after a total period of T,.mS. If not the control closes down and provides a warning via the failure detection circuit 13.

The interrupt routine is commenced every tluS and is shown in Figure 4. As shown this routine ascertains (110) for each wheel in turn whether there is any new data in the associated latch 22-25 since the last interrupt routine by checking the appropriate bit output of latch 26. If so the data from the appropriate latch 22-25 is stored (111). If not the interrupt routine either returns to step 110 or exits back to the main routine depending on whether all four latches 22-25 have been read or not (112).

Turning now to Figure 5a a detection sub-routine So is shown therein. In this sub-routine the speed of the wheel in question is subtracted (120) from the vehicle speed reference generated from the four wheel speeds and a decision (121) is made as to whether the slip is greater than 1 mis. If not the programme returns to the main routine, (since any slip which exists is within the tolerance which can be allowed). If so a base deceleration threshold signal is calculated (122) by selecting typically the smaller of 2g or 5g - 0.25gimps of slip, and threshold signal is then generated (123) by adding to this base threshold signal a term proportional to wheel speed.

The actual wheel deceleration signal derived following the immediately previous interrupt routine is then compared (124) with the calculated threshold and, if the actual deceleration does not exceed the threshold deceleration, the programme returns to the main routine. If the threshold decleration is exceeded, the programme sets (125) the flag for that channel to S1 (so that the release pulse sub-route S is entered for this channel in the next main routine cycle Tcyc mS later). The value of the actual deceleration signal is recorded (126), a solenoid timing counter (which counts the main routine cycles for the channel) is started (127) and an appropriate bit is output (128) to energisethe solenoid A, B or C.

Thereafter the programme returns to the main routine.

The release pulse sub-routine S, (Figure 5b) starts with a test (130) of the solenoid timing counter content. If this is not greater than unity the stored deceleration threshold signal is increased (131) by 0.sag and, if thecountisgreaterthan unity2g is added (132) to the deceleration threshold signal. The solenoid timing counter is incremented (133) and the latest actual deceleration signal is compared (134) with the new deceleration threshold signal. If the new threshold is exceeded a test (135) is made to ascertain if the solenoid timing counter content is more than 3. If so the channel flag is set (136) to S3 (so that on the next cycle, the main dump and sub-routine S3 for the channel is entered).The programme then returns to the main routine., If the count is not greater than 3 the programme returns directly to the main routine. If the new threshold is not exceeded, the bit output which energised the solenoid is cleared (137), the channel flag is set to S2 (so that the monitor state sub-routine S2 is entered for that channel in the next cycle), the solenoid timing counter is cleared (139) and an S2 timer is started (140).

When the monitor state sub-routine S2 is entered (Figure 5c) a test (150) is made to determine whether the S2 timer count is equal to one. If so the S2 counter is incremented and, the programme returns to the main routine. If not, a test (151) is made to asertain whether the slip (i.e. vehicle speed- wheel speed) is less than 2.2m/s. If so the channel flag is set (152) to SO (so that the detection sub-routine SO is entered on the next cycle), the S2 timer is cleared (153) and the programme returns to the main routine.If the slip is not less than 2.2m/s then a re-trigger threshold is established (154) which is typically the smaller of 89 or 129-1 .4glmls of slip but may optionally include a term which gives a reduced threshold if an expected recovery acceleration is not achieved. The actual deceleration is then checked against this threshold and if the threshold is exceeded the channel flag is set (156) to S3 (SO that the main dump sub-routine is entered on the next main routine cycle), an output is provided (157) to the appropriate solenoid, the S2 timer is cleared (158), and the solenoid timing counter is started again (159).If the threshold is not exceeded, a fast retriggerthreshold signal is computed (160) as 8g -(1.4gsm/s slip + 0.59 x S2 timer content). The deceleration is then tested (161) against this fast retriggerthreshold and iffound notto exceed the threshold the S2 timer is incremented (162) and the programme returns to the main routine. If the fast retrigger threshold is exceeded the channel flag is set (163) to S1 (so that the release pulse sub-routine S, is entered on the next cycle), the appropriate bit output energises (164) the channel solenoid, the S2 timer is cleared, the solenoid timing counter is started (164) and the programme returns to the main routine.

The main dump sub-routine S3 (Figure 5d) starts by incrementing the solenoid timer count (170) and a solenoid release threshold is then formed (171) as typically 89-1 .4glmls slip. The actual deceleration is compared with this threshold and if the threshold is exceeded the solenoid on signal is maintained (173) and the programme returns to the main channel. If the threshold is not exceeded the channel flag is set (174) to S2 (SO that the monitor state routine is entered on the next cycle), the solenoid is released by clearing (175) the output bit, the solenoid timing counter is cleared (176), the S2 timer is started and the programme returns to the main routine.

Figures 6 to 8 illustrate the operation of the system.

Figure 6 shows the wheel deceleration plotted against time for skids of three different degrees of severity. A stepped line 200 shows how the threshold signal varies with time. This threshold line 200 commences at an initial level 200a determined in the detection routine So (steps 122 and 123). After one main routine cycle (TcycmS) the threshold is increased by 0.5g and after a further 8mS it is increased by 2g (steps 131, 132 of sub-routine S1).

The line 201 represents a shallow skid in which the first 2g step increase takes the threshold above the measured wheel deceleration and therefore allows the brakes to be re-applied after 2 x T,,,. Further step increases of 29 occur after successive Toyc intervals and line 202 represents a somewhat more severe skid in which the deceleration falls below the threshold after two 29 increases have been made.

The brakes are re-applied at the 4XTcyc point. Line 203 shows an even more severe skid in which the deceleration has failed to fall below the threshold after 4XTCyc This condition is the one which causes the sub-routine S3 to be entered on the next cycle.

Figure 7 contains two plots, one showing wheel speed against time and the other deceleration against time. This second plot shows the other deceleration against time. This second plot shows the effect of sub-routines S1 and S3. Line 300 shows, the step-wise increases in the threshold. Curves 301, 302 and 303 show skids of increasing severity. In the case of lines 301 and 302 the deceleration falls below threshold before 4XTcyc has expired, so that subroutine S3 is not entered. Instead sub-routine S2 is entered (its effect being shown in Figure 8). In the case of line 303, however, sub-routine S3 is entered and the threshold signal is then dependent on the degree of slip which is changing with time. The line X-X in Figure 7 shows the threshold in the case of line 303 in the S3 mode.Line 304 shows another even more severe skid (for example on a very poor surface). The line Y-Y shows the S3 threshold for line 304. It will be noted that the deceleration threshold in S3 mode soon becomes negative (i.e. it represents a positive acceleration). Thus on very low friction surfaces brake re-application is delayed until an substantial wheel acceleration is detected.

Referring finally to Figure 8, the effect of subroutine S2 is shown, Figure 8 having two plots respectively showing wheel speed and deceleration as a function of time. The initial detection deceleration threshold is set up in steps 122 and 123 of sub-routine S,, and routine Si (step 134) determines re-application of the brakes. The re-trigger threshold of sub-routine S2 is then introduced to determine when the next brake release is to be effected.The S2 mode continues with the re-trigger threshold falling with time (because of the 0.5g x S2 timer content term) until either the slip falls below 2.2m/s (in which case the channel reverts to the SO mode) or the S3 or S1 modes are entered when deceleration is compared with the re-trigger threshold (step 155) or with the fast re-trigger threshold (step 161).

The system described above provides excellent early detection of deceleration with the brake release pulse thus produced being terminated shortly (i.e.

after, 1,2,3 or 4 T,,,) unless the absolute deceleration level is high. In the latter case, i.e. if the threshold is still exceeded when it reaches its maximum level after 4T,,,, the brake release pulse is maintained and the mode of operation is changed so that there must be clear evidence of wheel recovery before the brakes can be re-applied. The threshold then set depends on slip and generally requires an actual acceleration level to be achieved before brake re-application. On brake re-application a wheel recovery mode is entered in which a low level re-detection threshold is set, which reduces as the measured slip increases and also as time elapses (at constant slip). This increased sensitivity mode is maintained for a fixed time before the normal detection mode is re-entered or until the wheel attains synchronous running.

Thus the system described above overcomes all the disadvantages of the prior art mentioned and can be relied upon to operate satisfactorily in widely varying operating conditions.

Although the description given above is of an embodiment of the invention which, makes use of a microprocessor, it will be appreciated that exactly the same results could be obtained utilizing logic circuits and/or analog circuits to carry out the various threshold signal generation and comparison functions. Such circuits would necessarily be complex and would, of course, be less readily changeable to suit different vehicle type than the microprocessor embodiment described, in which changes can, if necessary, be made in the stored programme to allow the system to be matched to different vehicle types.

All threshold expressions quoted are only typical of values which are used and adjustments of the stored program mayinvolve changes to the terms of each or all these threshold expressions to allow for differences in vehicle parameters.

In the modification shown in Figure 9, the step 132 of Figure 5b is replaced by a step 132a. Here, instead of increasing the threshold by a fixed increment in each cycle, the new threshold is generated by adding to the existing stored threshold a term dependent on the amount by which the measured deceleration exceeds the existing threshold.

Claims (1)

1. CLAIM

   1. A vehicle anti-lock brake control system comprising wheel speed sensing means for generating a signal dependent on wheel speed, means for operating on said wheel speed signal to generate a signal dependent on the rate of change of wheel speed, means for comparing said rate of change signal with a threshold signal and providing a brake release output signal for as long as said rate of change signal represents a wheel deceleration in excess of a threshold represented by said threshold signal, and means for generating said threshold signal such that if the brake release output signal persists for more than a predetermined time period, the threshold signal is changed from a level representing a relatively high wheel deceleration to a new level representing a relatively low wheel deceleration or even a low acceleration in extreme cases, said new level being dependent on wheel slip (i.e. the difference between wheel speed and a vehicle reference speed derived from a combination of the speed of the wheels of the vehicle).