GB2164474A - Circuit testing - Google Patents

Abstract

Signature analysis, as used in circuit testing, includes applying a digital data stream from a node of a circuit to be tested to a feedback shift register (1) for a preset period or window. At the end of this window the register contains a multibit number representative of the logic state of that node. This signature is transferred to another register (11) and the test repeated. The signature in the second register is then transferred ferred to a third register (12) and the new signature placed in the second register. The signatures in the second and third registers are compared by a comparator (13) and when after several signatures have been taken it is indicated that a stable signature has been obtained, that signature is applied to a microprocessor for checking to assess the state of the node under test. The above arrangements are included on a chip, and can be on the same chip as a logic circuit to be monitored. Thus as applied to a digital telephone exchange one or more of the chips from which the exchange is assembled can have such a signature analysis chip portion. <IMAGE>

Description

SPECIFICATION Signature analyser This invention relates to an electrical circuit for use in a digital test device known as a signature analyser.

Signature analysis (SA) is a method of testing a digital equipment,such as a microprocessorbased system, which is absed on data compression. The method involves probing a node of the equipment to be tested from which a digital bit stream embracing period, called a test window, which embraces a number of clock cycles is input to the SA during the time window, which is circuit-controlled. The data thus probed from the test node is then entered into a feedback shift register, e.g. a 16 bit register, in either true or complement form, the feedback connection being in accordance with a preset algorithm. The bit stream from the node under test therefore sets the register to one of its possible states, of which there are (2'6-1) if the register is a 16 bit register.The register setting, which is the signature for the node, is then encoded and displayed in any desired form, e.g. as a four digit hexadecimal form. The resulting display is thus compared with what it should be for a correctly-operating circuit. Any change in the operating conditions of the device under test is reflected in a change in the signature for that node, and hence in the display. Thus a discrepancy shows that a fault is present (and may also identify or help to identify the fault).

An object of the invention is to produce an integrated circuit unit for use in such a signature analyser.

According to the invention there is provided an integrated circuit unit for use in a signature analysis system, which includes a data input via which a digital data stream to be monitored is applied to a feedback shift register for a preset period such that after said application the shift register is set to a condition characteristic of the data stream, a first register to which the bit combination representing said condition is transferred when the shift register has been set, a second register to which the bit combination in the first register is transferred when another operation of the feedback register is to occur, such that when during operation the nominally same digital data stream is received two or more times successively via the data input, the two registers contain two versions of the same bit condition, and a comparator which compares the contents of the two registers after each operation of the feedback shift-register, said comparator generating an output indicating that the bit combinations in the registers represent stable signature for the digital data stream being monitored, whereafter that signature is indicated as required.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a highly schematic block diagram, and Figs. 2, 3 and 4 show how such a chip may be used in an automatic telephone exchange.

The arrangement shown in the block diagram is implemented as a single chip, and it includes a 16 bit signature analysis shift register 1 to which the input data probed from one of a number of test nodes in the device to be tested is applied via a multiplexer 2 and gate 3, the data from each node being supplied via one of a number of latches in the block 4. The multiplexer enables any one of 32, in the example shown, nodes to be tested, this multiplexer is controlled from a control register 5, which is fed a control word from a host microprocessor (not shown) via a microprocessor interface 6.

The shift register 1 has its feedback connections made via respective EXCLUSIVE OR gates in accordance with the following feedback polynomial: 10 D, 0 D9 0 D12 0 D16 There is also on the chip a clock generator 7, which provides the following facilities: (a) generation of the shift register's clock from an incoming free-running clock 8 and start 9 and stop 10 signal inputs which are synchronous with the input data from the node to be tested, (b) resetting the shift register 1 to its "all O's" state after a signature has been taken, via the reset lead shown, (c) providing a clock to enable the resulting signature to be staticized (vide infra).

The clock input, the start signal and the stop signal all come from the device to be tested, via respective multiplexers 8, 9 and 10. These, like the multiplexer 2, are controlled from the register 7. The start and stop signals define the test window for the arrangement. Thus we have input multiplexers to enable any one of 32 data sources to be tested, and either one of two clock sources, two start signals and two stop signals to be used. The contents of the control register 7 then include five bits to control the multiplexer 2, and one each to control the multiplexer 8, 9 and 10.

The associated logic to detect a stable signature includes two sixteen bit registers 11 and 12.

When a signature has been taken, it is transferred from the feedback shift register 1 to the register 11, under control of the outputs of the clock generator on the block 7. When this occurs, the contents of the register 11, which in normal operation represents the previous contents of the register 1, are transferred to the register 12, also under the control of the clock generator. The latter register has two portions, one for most signficant byt (MSB) and the other for less significant byte (LSB).

Thus we have two consecutive versions of the tested node's signature in the registers 11 and 12, and these are compared by a sixteen-bit comparator 13 to check identity. If identity is found, the comparator gives an output to a 3:1 multiplexer 14 over the connection shown via a status register 15. This latter multiplexer can be fed as desired from register 12, or from the status register 15 associated with the comparator 13. When a stable signature has thus been found it is applied via the eight-bit data bus 19 to the host processor (not shown) for assessment to determine the fault (if any). This occurs after the processor has checked from the status register that a stable signature exists. The signature can also be applied to a visual indicator after coding, if desired.

A stable signature counter 17 supplies numbers to indicate how many stable signatures have been produced, its outputs being supplied via the multiplexer 14 to the interface.

The microprocessor interface has the following signals: (i) CS CHIP SELECT, an active low signal which indicates, with a read or write signal that the microprocessor is accessing the signature analysis chip.

(ii) RD READ, an active low signal that indicates, with CHIP SELECT, that the microprocessor is reading a register of the chip.

(iii) WR WRITE, an active low signal that indicates, which chip select, that the microprocessor is writing to a register of the chip.

(iv) A0,A ADDRESS, two active high signals that indicate which register the microprocessor is accessing.

(v) .... . D7 DATA, eight active high bidirectional signals on an eight bit data bus 19 containing the data that the microprocessor is reading or writing.

A chip such as just described is preferably included for signature analysis testing, as part of a self-testing equipment for a digital system. When a test sequence is needed, the microprocessor accesses the chip, and in effect, "tells" it to run through a test sequence in which up to 32 test nodes can be tested. As already indicated two external clocks are assumed to be available, and the word put into the control register 5, etc. from the microprocessor selects which clock is to be used. This word also selects which one of two available start signals, and which one of two available stop signals, is to be used, via the devices 8, 9 and 10. When a stable signature is available it is read out under control of a signal applied to the lead 20, which signal comes from the control block 7.

In some cases where an exceptionally high level of equipment integrity is called for it may be desired to include a test pattern generator on the signature analysis chip to test that chip. The PRDG may be used to stimulate the external logic into generating predetermined data sequences or it may be used in a self-test more to generate signatures internally (thus checking the signal generator register and subsequent logic). This is implemented as a free-running pseudo-random binary sequence generator. This uses a shift register 22 which is at least ten bits long with EXCLUSIVE OR feedback connections to generate a maximal length sequence, i.e. 2n-1 bits where n is the length of the shift register. This shift register is clocked by the clock selected for the analyser's shift register 1.

Associated with the output from the test pattern generator shift register, there are Start and Stop output signals, as shown, used in conjunction with the generator's output to cause the chip to produce signatures. One way to produce such signals is to decode particular states in the pseudo-random sequence, using a decoder 23, and the signals' polarities are so chosen that they may be connected directly to the analyser's inputs, internally if desired.

Another useful facility is to allow the host microprocessor to be able to select whether the clock, start and stop signals are active high or low. This needs an additional control register in the interface 5 for the three bits needed to define these, plus a somewhat more complex interface to allow that additional register to be written into, and to exercise its control functions.

Where the signature analysis chip is actually included in the equipment to be tested, it is useful to be able to place it into a low power mode when it is not being used to take signatures. This would need another bit in the additional control register, plus some extra control circuitry.

In the foregoing description we have referred to the use of the SA chip as an "on board" unit for a logic system. One example of how this is done will now be described with reference to Figs. 2, 3 and 4, which illustrate the application of the chip to a digital electronic telephone exchange.

The telephone exchange to which the SA chip has been applied includes a duplex voice switch 30, which has a capacity of 1000 lines, the actual switch being duplicated in the interest of system security. The subscribers' line circuits are in groups on a number of rack shelves such as 31, and each such shelf is connected via GO and RETURN. This latter multiplexer is connected to the voice switch 30 by further GO and RETURN TDM highways, as shown.

To perform the test sequences involving the use of the SA chip, test signals are applied via test pattern insertion points (TPI) and read out from test pattern extraction (TPE) or test pattern monitor (TPM) points. In Fig. 2, some of the positions of the TPM points are indicated by the asterisks.

Fig. 3 shows how TPI points can be inserted into the highways from the serial-parallel mux 32 to the switch 30, while in Fig. 3 the TPI points are in the input highways to the individual switches of the duplex pair. Fig. 3 also shows TPM points for dealing with test patterns after they have traversed the switch.

The areas considered for testing using an SA chip are quite varied, and four are considered herein: i) Voice Path Test Patterns ii) Time Slot Allocation iii) Tone System Diagnostics iv) Voice Switch Memory Monitoring (1) Voice Path Test Patterns The insertion of test patterns into the voice path at regular time intervals, e.g. at the points indicated at TPI in Fig. 2 allows the voice path to be checked. The correct siting of test pattern monitor (TPM) or test pattern extractor points (TPE) allows fault detection and isolation. The test patterns which reach these points are applied to inputs of an SA chip as shown in Fig. 1, and included on one of the boards of the exchange.

There are three possible sites for test pattern inserters (TPl); i) At the line shelf, as shown in Fig. 1 on the serial buses.

ii) Immediately before the duplex Voice Switch (Fig. 2).

iii) The input arms of both duplex switches (Fig. 3).

Test Site (i) A TPI on the serial PCM buses allows test patterns to be circulated through the entire voice path, in which case general faults are found. Also, by switching the patterns through different switches or portions of switches, it is possible to isolate problems to particular half paths. In this system each connection is set up by two half paths, one from the caller to a centre point and the other from the wanted line to the same centre point. Test pattern monitors (TPM) must be correctly sited or given access to the correct nodes to allow isolation of faults to board level.

The problem with this method is that the 'off-line' voice switch cannot be tested without bringing it 'on-line'. This may be undesirable if the 'off-line' switch may be faulty. However, this method does give a valuable test facility with one TPI fitted to every line shelf.

Test Site (ii) This is similar to the former test site, but the path between the line shelf and the TPI is not tested by the test pattern. However, only one TPI is needed for four of the line shelf TPl's.

Test Site (iii) This is similar to test site (ii) but allows the individual 1K switches to be tested off-line, which is advantageous when diagnostics must be applied to a suspect switch. This needs twice as many TPl's as Test Site (ii), but they may be both part of one unit.

TPI Circuits There are many possible designs for a TPI which depend upon the test site and requirements of the pattern. Such a circuit allows any time slot to be chosen to convey a test pattern, and if it has a memory to supply the pattern then a different test byte may be used in subsequent frames. Also a parity test feature can be used.

Such a circuit if included "on chip" with the SA circuit has output connections to the appropriate points on the network to be tested.

Claims (9)

1. An integrated circuit unit for use in a signature analysis system, which includes a data input via which a digital data stream to be monitored is applied to a feedback shift register for a preset period such that after said application the shift register is set to a condition characteristic of the data stream, a first register to which the bit combination representing said condition is transferred when the shift register has been set, a second register to which the bit combination in the first register is transferred when another operation of the feedback register is to occur, such that when during operation the nominally same digital data stream is received two or more times successively via the data input, the two registers contain two versions of the same bit condition, and a comparator which compares the contents of the two registers after each operation of the feedback shift-register, said comparator generating an output indicating that the bit combinations in the registers represent a stable signature for the digital data stream being monitored, whereafter that signature is indicated as required.

2. An integrated circuit unit as claimed in claim 1, in which said data input is fed from a number of separate input connections via a multiplexer, so that digital data streams may be received from any one of a number of different test points on a circuit to be monitored.

3. An integrated circuit unit as claimed in claim 1 or 2, and which includes a status register associated with the comparator which indicates whether a stable signature has been detected, a control signal being applied thereto when a said stable signature is to be used for test purposes, and gating means responsive to said control signal to read a said stable signature from the second register and to an associated test means.

4. An integrated circuit unit as claimed in claim 3, in which each said first and second register has a capacity of 2n bits, in which said gating means includes a multiplexer associated with the status register and with said second register, and in which when a said control signal is received the status register causes the first n bits of a said signature to be read out of the second register via said multiplexer, followed by the second n bits of that signature.

5. An integrated circuit unit as claimed in claim 4, and which includes a counter associated with said comparator and adapted to indicate how many stable versions of a said signature have been successively generated, and the setting of said counter being read out of the counter via the multiplexer in association with the two portions of the signature.

6. An integrated circuit unit as claimed in claim 1, 2, 3, 4 or 5, and which also includes a test pattern generation unit for generating a test pattern which, when applied to a circuit to be tested, causes the production of one or more of said digital data streams.

7. An integrated circuit unit for use in a signature analysis system, substantially as described with reference to Fig. 1 of the accompanying drawings.

8. A data processing system which includes one or more integrated circuit units one of which includes, in addition to its own data processing circuitry an unit as claimed in claim 1, 2, 3, 4, 5, 6 or 7, together with a microprocessor for testing the signatures and comparing each such signature with a correct signature, the result of such comparison being indicative of the condition of the system.

9. A system as claimed in claim 8, and which is a digital automatic telephone exchange.