GB2156155A - AC circuit controller - Google Patents

Abstract

An a.c. circuit controller utilises a control circuit 12 which produces a pulse train substantially synchronised with a.c. zero crossings when a load L is to be energised. To randomise the direction of zero-crossing at which switch-on occurs and thereby protect a relay RL which has contacts RL1 in parallel with a load controlling semi-conductor switch device Q1 from contact damage caused by relay contact material transfer, an integrator R7, C6 is provided to integrate these pulse and provide a staircase waveform. A comparator A1 detects the level of this staircase waveform and controls firing of Q1 and energisation of the relay RL. In another embodiment (Fig. 2, not shown) the direction of zero crossings sensed by a digital circuit controlling the switch device and the relay is changed at the end of each cycle of operation. <IMAGE>

Description

SPECIFICATION A.C. circuit controller This invention relates to an A.C. circuit controller intended to control, for example, a domestic storage heater.

It has already been proposed (see e.g. US A-3558910) to utilise the parallel combination of a semi conductor switching device such as a triac and a relay contact to control load current. With such an arrangement a control circuit causes the triac to be switched on shortly before the relay contacts close and to be switched off shortly after the contacts open. In this way the benefits of absence of arcing across the relay contacts and minimum power dissipation in the triac (since it is shorted out by the relay contacts most of the time) are obtained.

It has been found, however, that unless the triac switch-on takes place at or near zero crossings in the A.C. waveform, moderate or severe mains-borne interference spikes are created. However, it has also been found that when the conventional triac/relay combination is used in combination with conventional zero voltage techniques, relay contact life suffers. It is an object of the present invention to provide an arrangement in which zero-voltage switching is obtained without the above-mentioned relay contact life penalty.

In accordance with the invention, there is provided an a.c. circuit controller including a semiconductor switch element for connecting a load across an a.c. supply, a relay having contact means in parallel with said switch and a control circuit for triggering said semi-conductor switch element at or shortly after zerocrossings in the a.c. supply waveform to avoid generation of interference spikes and for energising said relay to close said contact means after a predetermined delay, characterised in that the control circuit includes relay protection means to prevent relay contact material transfer by ensuring that relay contact means closures occur substantially equally frequently on opposite polarity half cycles of the a.c.

supply waveform.

Such relay protection means may comprise means for ensuring that the polarity of the a.c. waveform is selected randomly or it may alternatively comprise means for ensuring that the polarity is selected to be alternately positive and negative.

The control circuit may be in the form of a pulse generator which, when energisation of the load is required is caused to produce a train of pulses immediately following each zero crossing in the a.c. supply waveform, integrating means connected to receive the pulse train and generate a staircase waveform, and comparator means for triggering the semiconductor switch when the staircase waveform reaches a predetermined voltage.

The invention thus acts to prevent relay contact damage caused by contact material being transferred from one contact to another as a result of repeated closing with the small forward voltage drop across the semiconductor switch always in the same direction.

In the accompanying drawings Figures 1 and 2 are circuit diagrams of two a.c. circuit controllers for controlling a storage heater in accordance with the ambient, both incorporating examples of the present invention.

Referring firstly to Fig. 1, the controller shown includes a main semiconductor switch in the form of a triac Q, which has its main current flow path in series with the load L across the line and neutral rails 10, 11 of an a.c. mains supply. Normally open contacts RL1 of a relay RL is connected in parallel with the triac, the winding of relay RL being connected in series with another triac Q2 across the supply.

A control circuit is provided for the triacs Q, and Q2 to ensure that triac Q1 is fired immediately following a zero crossing in the supply waveform and the relay contacts close after a delay and that triac Q, ceases to be fired in each supply half cycle after a delay following opening of the relay contacts.

This control circuit includes a zero-voltage switch integrated circuit 1 2 which may be a Plessey integrated circuit type SL441C. The Vcc terminal of this integrated circuit 1 2 is connected to the live rail 10 by a resistor R1, a capacitor C, and a diode D2 in series. A capacitor C3 connects the Vcc pin to the neutral rail 11 and a diode D, has its anode connected to the neutral rail 11 and its cathode connected to the anode of the diode D2.

An internal zener diode included in the integrated circuit 1 2 provides the Vcc terminal thereof with a zener regulated voltage which is supplied to a rail 1 3. The AC INPUT terminal of this integrated circuit is connected by a phase advance network consisting of a resistor R2 in parallel with the series combination of a resistor R3 and a capacitor C2 to the live rail 10. The PULSE DELAY CAPACITOR terminal of circuit 1 2 is connected to rail 11 by a capacitor C4 and a resistor R4 in series and the TIMING COMPONENTS terminal in connected by a resistor R5 to rail 1 3 and by a capacitor C5 to rail 11.The REGULATED OUTPUT terminal of the circuit 1 2 is connected by a thermistor TH 1, a variable resistor VR1 and a preset variable resistor VR2 in series to rail 11 and the CONTROL INPUT terminal is connected to the junction of the thermistor TH 1 with the variable resistor Or 1.

The output terminal is not connected, as is usual with the integrated circuit 12, directly to drive a triac, but is connected instead by a resistor R7 to one side of a capacitor C6, the other side of which is connected to rail 11. A resistor R8 is connected across capacitor C6 and a resistor R9 connects said one side of capacitor C6 to the non-inverting input of a voltage comparator A1. The inverting input of comparator A, is connected to a reference voltage source, namely a pair of diodes D3 D4 in series with a resistor R6 between the rails 13, 11 such that a reference voltage of about 1.4 volts is supplied to the inverting input of comparator A1. A resistor R,o connects the output terminal of comparator A1 to its non-inverting input terminal.

The output terminal of comparator A, is connected to the anode of a diode D5, the cathode of which is connected to one side of a capacitor C7 the other side of which is connected to rail 11. A resistor R" is connected across capacitor C7, said one side of which is connected to the non-inverting input of a voltage comparator A2. The inverting input of comparator A2 is connected to the aforementioned reference voltage source R6, D3,D4.

The output of comparator A2 is connected to the anode of another diode D6 the cathode of which is connected to one side of a capacitor C8, the other side of which is connected to the rail 11. A resistor R,3 is connected across the capacitor C6 and said one side of capacitor C6 is connected to the non-inverting input of yet another voltage comparator A3 the inverting input of which is connected, again, to the reference voltage source R6, D3 D4.

Comparator A3 has its output connected to the cathode of a diode D7 the anode of which is connected by a resistor R,s to the rail 1 3 and by a capacitor C6 to the rail 11. The anode of diode D7 is also connected to the emitter of a unijunction transistor Q3 the bases of which are connected by respective resistors R,6 R,7 to the rails 1 3, 11. The base connected to resistor R,6 is connected by a resistor R,402, to the base of an npn transistor Q5 the collector of which is connected by a resistor R,2 to the output of comparator A2 and the emitter of which is connected to the gate of the triac Q2. The base of u.j.t.Q3, which is connected to resistor R,6, is also coupled by a capacitor C,O to the base of a pnp transistor Q4, the emitter of which is connected to rail 1 3 and the collector of which is connected by a resistor R,g to the gate of the triac Q,. A resistor R,8 connects the base of transistor Q4 to rail 1 3.

The integrated circuit 1 2 includes an internal voltage comparator which compares the voltages at its pins 7 and 8 and circuit provides a train of output pulses delayed relative to zero-crossings in the waveform applied to its pin 2 and of duration determined by resistor R4 and capacitor C4, whenever the voltage at pin 8 is below that at pin 7.

Resistor R5 and capacitor C6 co-operate to impose a voltage ramp on pin 7 so that the length of time in each ramp cycle for which the output pulse train is being produced is variable in accordance with the voltage at pin 8. Since this voltage is dependent on the temperature sensed by thermistor TH 1 and the setting of variable resistor RV1 it will be seen that the pulse train duration is a function of temperature.

Whilst the pulse train referred to is being produced capacitor C6 receives more charge through resistor R7 during pulses, than it loses through resistor Ra in the interval between pulses and a voltage "staircase waveform" is thereby imposed on the capacitor C6. When this voltage rises above the 1.4V reference voltage by the small voltage margin imposed by hysteresis, the output of comparator A, goes high and drives the outputs of comparators A3 and A3 high substantially simultaneously. This enables the u.j.t. Q3 to start operating as a pulse generator whereby transistor Q5 is rendered conductive whenever u.j.t. Q3 is non-conductive and transistor Q4 is rendered conductive each time u.j.t. Q3 becomes conductive.

When the output of comparator A2 goes high the u.j.t. is not conductive and, hence, a firing pulse is immediately delivered to the triac Q2. However, there is an innate delay between current starting to flow in the relay winding RL and the contacts RL1 closing and before this delay has expired, the first pulse is delivered to transistor Q4 to fire the triac Q,.

The phase advance network R2, R3, C2 ensures that the delay between the actual zerocrossing in the supply waveform and the firing of triac Q1 is short so that interference spikes are not generated.

When the pulse train from circuit 1 2 ceases, capacitor C6 discharges through resistor R6 until the voltage on it falls sufficiently below the 1.4V reference voltage for the output of comparator A, to go low. There is then a delay whilst capacitor C7 discharges through resistor R" before the output of comparator A2 goes low. No further firing pulses are supplied thereafter to triac Q2 so that relay RL drops out. After a further delay long enough to ensure that relay drop-out has occurred the output of comparator A3 goes low, such delay being determined by discharge of the capacitor C6 through resistor R,3. This stops the u.j.t. pulse generator and triac Q, ceases to conduct at the next zero crossing.

With the arrangement described above the voltage across the triac 0, at the instant of closing of the contacts of the relay is equally likely to be of either polarity. Thus premature failure of the relay contacts as a result of low voltage contact material transfer is avoided.

Turning now to Fig. 2 the circuit shown therein makes use of CMOS logic elements to ensure that alternate relay closures take place at opposite supply polarities.

The part of the circuit enclosed in dotted lines in Fig. 1 is retained, but is not shown again in Fig. 2. Two points A and B within these dotted lines provide inputs to the circuit of Fig. 2.

Point A receives a 50Hz signal at an appropriate voltage level for directly driving CMOS integrated circuits. Point A is connected to an inverting Schmidt trigger circuit 101 which acts as a zero crossing detector. The output of circuit 101 is connected to one input of a NAND gate 102, the other input of which is connected to the Q output of a J-K flip-flop circuit 103. Another NAND gate 104 has one input connected to point A and its other connected to the Q output of circuit 1 03. The outputs of gates 102, 104 are connected to the inputs of a NAND gate 105.

Point B is at the output terminal of the integrated circuit 1 2 at which there is a train of pulses synchronised with zero crossings whenever it is required for the load to be energised. Point B is connected to the anode of a diode 106 the cathode of which is connected by a resistor 107 to the input of another inverting Schmidt trigger circuit 108, a capacitor 109 and another resistor 110 being connected in parallel between this input and ground. The output of circuit 108 is connected by a capacitor 111 to the anode of a diode 11 2, the cathode of which is connected by a resistor 11 3 to ground. Another capacitor 11 4 connects the input of circuit 108 to the anode of a diode 11 5 which has its cathode connected to the cathode of diode 112.Two resistors 116,117 connect the anodes of respective ones of the diodes 11 2, 115 to ground.

Resistor 107 and capacitor 109 effectively integrate the pulse train at terminal B and the remainder of this part of the circuit acts to provide a positive going pulse at the beginning and end of each such pulse train.

The cathodes of diodes 112, 11 5 are connected to the S input of a J-K flip-flop 118 which has its J, K and C terminals connected to the supply voltage rail 1 20. The 0 output of this circuit 11 8 is connected to one input of a NAND gate 121, the other input of which is connected to the output of gate 1 05. The output of gate 121 is connected to the CK input of a decade counter 122, which has its CE (count enable) terminal grounded. The QO output of counter 1 22 is connected to the C input of circuit 103, which has its R and S terminals grounded and its J and K terminals connected to supply rail 1 20 so that it changes its output state each time its C input goes high.The Q, and Q5 outputs of counter 1 22 are connected to the inputs of a NOR gate 123, the output of which is connected to the input of an inverter 1 24 which has its output connected to one side of a capacitor 1 25. The other side of capacitor 1 25 is connected to the cathode of a diode 1 26 which has its anode grounded and is also connected by a resistor 1 27 to ground.This other side of capacitor 1 25 is connected to the R terminal of circuit 11 8 and gate 1 23 and inverter 1 24 operate to provide a positive going reset pulse to circuit 11 8 whenever either the Ol or Q5 output of counter 1 22 goes high.

Outputs Q2 and Q7 of counter 1 22 are connected to the inputs of a NOR gate 1 30.

Output Q3 is connected to the input of an inverter 131. Outputs Q4 and Qg are connected to two inputs of a NOR gate 1 32 and output Q8 is connected to one input of a NOR gate 1 33. The R (reset) input of counter 1 22 is connected to an initialising circuit comprising an inverting Schmidt trigger circuit 1 34 having its input connected to the junction of two resistors 1 35, 1 36 in series between rail 1 20 and ground, a capacitor 1 37 being connected in parallel with resistor 1 36. Gates 1 32 and 1 33 both have inputs from the output of circuit 1 34.

Gates 1 30 and 1 32 drive a flip-flop circuit made up of two NAND gates 140 and 141 cross-connected as shown. Gate 1 30 has its output connected to an input of gate 140 and gate 1 32 has its output connected to an input of gate 141. Another flip-flop circuit made up of two NAND gates 142, 143 is driven by inverter 131 and gate 133, inverter 131 having its output connected to an input of gate 142.

Gates 1 40 and 1 42 have their outputs connected to inputs of respective ones of two NAND gates 144, 145. An oscillator 146 has its output connected to the other inputs of these gates 144, 145. Gate 144 has its output connected to the input of an inverter 147, the output of which is connected to the cathode of a diode 148 the anode of which is connected by a resistor 149 to rail 120. The anode of the diode 1 48 is also connected to the anode of a diode 1 50 which has its cathode connected to the base of an npn transistor 1 51. The collector of the transistor 151 is connected by a resistor 152 to rail 1 20 and its emitter is connected to the gate of the triac TQ, like that in Fig. 1.Triac TQ, is triggered by a train of pulses from the oscillator 1 46 whenever the output of gate 144 is low.

Similarly the other triac TO2 which controls the relay RL is triggered whenever the output of gate 1 45 is low. The oscillator 146 has an operating frequency high enough to ensure that radio frequency interference is substantially eliminated (i.e. to ensure that there is a pulse sufficiently soon after each zero crossing to prevent a significant switch on transient).

At power up the Schmidt trigger circuit 1 34 produces a high output while capacitor 1 37 is charging and this resets counter 1 22 and the two flip-flop circuits 140, 141 and 142, 143.

After this high output disappears the QO output of counter 1 22 goes high and clocks the J-K flip-flop circuit 103. Initially the output of gate 1 23 is high so that JK flip-flop 118 powers up with its 0 output high so that gate 1 21 is enabled and the next mains zero crossing in the sense appropriate to the state to which JK flip-flop 103 has been set will clock the counter 1 22 so that its Q1 output goes high driving gate 1 23 output low and thereby causing inverter 124 to go high, thereby applying a reset pulse to JK flip-flop 118.The 0 output of JK flip-flop 118 thus goes low, blocking gate 1 21 and stopping the counter 1 22 in readiness for the first train of output pulses from integrated circuit 12. Neither triac has been fired at this stage.

When this first pulse train arrives, JK flipflop 11 8 is set, causing its Q output to go high and thereby enabling gate 121. The next appropriate mains zero crossing clocks counter 1 22 so that its Q2 output goes high which causes flip-flop 140, 141 to change state and enable gate 144. Triac TQ, is thus fired. The next appropriate mains zero crossing (20 mS later) clocks counter 1 22 again and its Q3 output goes high which causes flip-flop 142, 143 to change state and permit firing of triac TQ2. The next appropriate main zero crossing clocks counter 1 22 again, causing the Q4 output to go high which resets the flip-flop 140, 141 so that triac TQ, turns off.Thus triac TO1 carries the full load for about 25 mS (i.e. 1 mains cycle plus 5mS relay delay) at which time the relay contacts have closed. 1 5 mS later triac TQ1 is turned off leaving the load current to be carried by the relay contacts alone. The next appropriate mains zero crossing clocks counter 1 22 so that its Q5 output goes high, thereby resetting JK flipflop 118 and blocking a gate 121 again.

This condition persists until the pulse train from circuit 1 2 (Fig. 1) ceases at which time JK flip-flop 118 is set again and gate 121 enabled. The next appropriate mains zero crossing clocks counter 122, but nothing happens as the Q6 output is not used. On the next clock pulse the Q7 output goes high so as to change the state of flip-flop 140, 141 again, thereby causing the triac TQ, to turn on again. The following clock pulse causes the Q8 output to go high which resets the flipflop 142,143 and allows triac TQp to turn off de-energising the relay RL. The following clock pulse causes the Q9 output to go high which resets flip-flop 140, 141 thereby allowing triac TO, to turn off. The following clock pulse causes the Oo output to go high again setting JK flip-flop 103 to its initial state and the next clock pulse (which occurs after only 10 mS because clock pulses are now synchronised with zero crossings in the opposite sense) causes gate 121 to be blocked again.

In the next cycle all operations will be synchronised with zero crossing in the opposite sense to those which controlled the previous cycle, so that contact material transfer between the relay contacts is totally prevented.

It will be appreciated that triac TQ1 is conductive for two 40 mS periods in each cycle of operation which may last several seconds. Hence, in the event of a relay failure, triac TQ1 will not be overheated.

Claims (11)

1. An a.c. circuit controller including a semiconductor switch element for connecting a load across an a.c. supply, a relay having contact means in parallel with said switch and a control circuit for triggering said semi-conductor switch element at or shortly after zerocrossings in the a.c. supply waveform to avoid generation of interference spikes and for energising said relay to close said contact means after a predetermined delay, characterised in that the control circuit includes relay protection means to prevent relay contact material transfer by ensuring that relay contact means closures occur substantially equally frequently on opposite polarity half cycles of the a.c.

supply waveform.

2. An a.c. circuit controller as claimed in claim 1 in which said relay protection means ensures that the polarity of the a.c. waveform is selected randomly.

3. An a.c. circuit controller as claimed in claim 2 in which said control circuit comprises a pulse generator which, when energisation of the load is required, is caused to produce a train of pulses immediately following each zero crossing in the a.c. supply waveform, said relay protection means incorporating integrating means connected to receive the pulse train and generate a staircase waveform, and comparator means for triggering the semiconductor switch when the staircase waveform reaches a predetermined voltage.

4. An a.c. circuit controller as claimed in claim 3 in which a second semiconductor switch device is provided for controlling the relay, said first-mentioned semi-conductor switch device and said second semi-conductor switch device being rendered conductive simultaneously under the control of said comparator, the inherent delay in operation of the relay delaying closing of the relay contacts until after load current has been established.

5. An a.c. circuit controller as claimed in claim 4 including delay means for delaying de-energisation of said first-mentioned semiconductor switch means after said second semi-conductor switch means has been deenergised.

6. An a.c. circuit controller as claimed in claim 1 including memory means for storing data relating to the sense of a.c. waveform zero crossing in each cycle of operation of the control circuit and rendering the control circuit sensing to opposite senses of zero crossing in alternate cycles of operation.

7. An a.c. circuit controller as claimed in claim 6 in which said memory means is a flipflop circuit providing outputs controlling a gating circuit to pass signals corresponding to zero crossings in one or other sense according to the state of said flip-flop circuit and means for clocking said flip-flop circuit in each cycle of operation.

8. An a.c. circuit controller as claimed in claim 7 in which said clocking means is a counter which is clocked by the output of said gating circuit under the control of an enabling circuit.

9. An a.c. circuit controller as claimed in claim 8 in which said enabling circuit is connected to the control circuit and operates to produce a pulse at the start and finish of each period during which energisation of the load is required.

1 0. An a.c. circuit controller in which said enabling circuit includes a further flip-flop circuit connected to be set to a count enabling state by each of said start and finish pulses, the counter being connected to reset the further flip-flop at certain count states of the counter to await the next start or finish pulses.

11. An a.c. circuit controller as claimed in claim 10 in which, the counter is connected so that successive clock pulses received from the gating circuit via the count enabling circuit following the start pulse cause (i) the semi conductor switch device to be turned on (ii) the relay to be energised and (iii) the semiconductor device to be turned off again, and successive clock pulses received following the finish pulse cause (i) the semiconductor switch device to be turned on again, (ii) the relay to be de-energised and (iii) the semiconductor switch device to be turned off again.

1 2. An a.c. circuit controller substantially as hereinbefore described with reference to Fig. 1 of the accompanying drawings.

1 3. An a.c. circuit controller substantially as hereinbefore described with reference to Fig. 2 of the accompanying drawings.