GB2154819A - Amplifying circuits - Google Patents

Abstract

An FET amplifier T1, particularly for a radar receiver, has its source and drain path connected through a first resistance R1 to a first supply voltage, the emitter of a bipolar transistor T2 is connected to the drain of the FET, the collector of T2 is connected through a second resistance R2 to a second supply voltage and the collector of T2 is also connected to the gate of the FET T1 by way of a third resistance R3. Circuit means R4, R5 apply a control voltage to the base of the transistor T2 to define the operating point of the FET T1. Instead of the potential divider R4,R5 a suitable circuit supplying a variable or constant control voltage may be used. Resistor R5 or R1 may be replaced by a temperature sensitive resistor (RT, Fig. 2) or (RS, Fig. 3) which compensates for variations in the gain of the FET with temperature. <IMAGE>

Description

SPECIFICATION Amplifier circuits This invention relates to amplifier circuits, and in particular to such circuits using field-effect transistors or FET's.

FET's are often used as amplifying devices, and one particular application relates to lownoise amplifiers for radar receivers. This application presents a particular problem, namely that caused by leakage of energy from the radar transmitter through the duplexer and protection circuits. Such leakage causes a large increase in the signal applied to the gate of the FET which may drive the FETA into forward conduction or reverse breakdown.

Whilst the increase in signal may be brief, the effects may last for a long time, in some cases in excess of the inter-pulse interval of the transmitter. The main effect is gain instability, and hence the FET may be rendered unusable as a front-end low-noise receiver amplifier.

FET's, in common with other semiconductor devices, are also temperature-sensitive, and hence the characteristics of the amplifier may vary with temperature.

It is an object of the invention to provide an FET amplifier circuit in which the above prodlems are avoided.

According to the present invention there is provided an amplifier circuit which includes an FET having its source and drain connected through a first resistance across a first voltage source, an NPN transistor having its emitter connected to the drain of the FET and having its collector connected through a second resistance to a second voltage source, a third resistance connected between the collector of the transistor and the gate of the FET, and circuit means for applying a control voltage to the base of the NPN transistor to define the operating point of the FET.

The invention will now be described with reference to the accompanying drawings, in which Figure 1 is a schematic circuit diagram of an amplifier according to the first embodiment; Figure 2 is a schematic circuit diagram showing a variation of the arrangement of Fig.

1; and Figure 3 is a schematic circuit diagram of a further variation of the circuit of Fig. 1.

Referring now to Fig. 1, the amplifying element of the circuit is an FET T1. This has its source connected to ground and its drain connected to a supply voltage + V1 through an inductor L1 and a resistor R. An NPN transistor T2 has its emitter connected to the junction between inductor L1 and resistor R1, designated X. The collector of transistor T2 is connected through a resistor R2 to a second supply voltage - V2, and also to the gate of the FET through a resistor R3 connected in series with an inductor L2. The base of transistor T2 is connected to a control voltage.In the case illustrated this voltage is produced at point Y, the junction between resistors R4 and R5 connected to form a potential divider between a reference supply voltage VR and ground.

A radio-frequency signal to be amplified is applied to the gate of the FET and the amplified signal is obtained from the drain. The inductors L1 and L2 prevent the radio-frequency signals from being fed back to the supply voltage sources, and decoupling capacitors DC are provided as shown.

In operation, the base of the transistor T1 is held at the voltage point Y. This is arranged such that point X is held at the voltage necessary to define the required operating point for the FET. If the current flowing through the FET falls, then more current will flow through the transistor T2. This will cause the gate of the FET to become less negative, thus increasing the current flowing through the FET.

A similar effect occurs if the FET is subjected to the large "breakthrough" signal referred to above. The drop in current through the FET resulting from the after-effects of the large signal causes the gate voltage of the FET to rise, and this restores the drain current to counteract the effects of the large signal.

As a result the FET becomes usable as a lownoise amplifier in the situation specified.

The voltage applied to the base of transistor T2 need not be supplied from the potential divider shown. A suitable circuit supplying a variable or constant control voltage may be used. One particularly suitable circuit is shown in Fig. 2. In this, one resistance of the potential divider is a temperature-sensitive resistor RT, having a characteristic which compensates for variations in the gain of the FET with temperature.

Fig. 3 shows another means of providing compensation for variations in the gain of the FET, in this case due to temperature variations. In this example the resistor R1 of Fig. 1 is replaced by a temperature-sensitive resistor RS, having the appropriate temperature characteristic.

1. An amplifier circuit through which includes an FET having its source and drain connected through a first resistance across a first voltage source, an NPN transistor having its emitter connected to the drain of the FET and having its collector connected through a second resistance to a second voltage source, a third resistance connected between the collector of the transistor and the gate of the FET, and circuit means for applying a control voltage to the base of the NPN transistor to define the operating point of the FET.

2. An amplifier circuit as claimed in Claim

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. SPECIFICATION Amplifier circuits This invention relates to amplifier circuits, and in particular to such circuits using field-effect transistors or FET's. FET's are often used as amplifying devices, and one particular application relates to lownoise amplifiers for radar receivers. This application presents a particular problem, namely that caused by leakage of energy from the radar transmitter through the duplexer and protection circuits. Such leakage causes a large increase in the signal applied to the gate of the FET which may drive the FETA into forward conduction or reverse breakdown. Whilst the increase in signal may be brief, the effects may last for a long time, in some cases in excess of the inter-pulse interval of the transmitter. The main effect is gain instability, and hence the FET may be rendered unusable as a front-end low-noise receiver amplifier. FET's, in common with other semiconductor devices, are also temperature-sensitive, and hence the characteristics of the amplifier may vary with temperature. It is an object of the invention to provide an FET amplifier circuit in which the above prodlems are avoided. According to the present invention there is provided an amplifier circuit which includes an FET having its source and drain connected through a first resistance across a first voltage source, an NPN transistor having its emitter connected to the drain of the FET and having its collector connected through a second resistance to a second voltage source, a third resistance connected between the collector of the transistor and the gate of the FET, and circuit means for applying a control voltage to the base of the NPN transistor to define the operating point of the FET. The invention will now be described with reference to the accompanying drawings, in which Figure 1 is a schematic circuit diagram of an amplifier according to the first embodiment; Figure 2 is a schematic circuit diagram showing a variation of the arrangement of Fig. 1; and Figure 3 is a schematic circuit diagram of a further variation of the circuit of Fig. 1. Referring now to Fig. 1, the amplifying element of the circuit is an FET T1. This has its source connected to ground and its drain connected to a supply voltage + V1 through an inductor L1 and a resistor R. An NPN transistor T2 has its emitter connected to the junction between inductor L1 and resistor R1, designated X. The collector of transistor T2 is connected through a resistor R2 to a second supply voltage - V2, and also to the gate of the FET through a resistor R3 connected in series with an inductor L2. The base of transistor T2 is connected to a control voltage.In the case illustrated this voltage is produced at point Y, the junction between resistors R4 and R5 connected to form a potential divider between a reference supply voltage VR and ground. A radio-frequency signal to be amplified is applied to the gate of the FET and the amplified signal is obtained from the drain. The inductors L1 and L2 prevent the radio-frequency signals from being fed back to the supply voltage sources, and decoupling capacitors DC are provided as shown. In operation, the base of the transistor T1 is held at the voltage point Y. This is arranged such that point X is held at the voltage necessary to define the required operating point for the FET. If the current flowing through the FET falls, then more current will flow through the transistor T2. This will cause the gate of the FET to become less negative, thus increasing the current flowing through the FET. A similar effect occurs if the FET is subjected to the large "breakthrough" signal referred to above. The drop in current through the FET resulting from the after-effects of the large signal causes the gate voltage of the FET to rise, and this restores the drain current to counteract the effects of the large signal. As a result the FET becomes usable as a lownoise amplifier in the situation specified. The voltage applied to the base of transistor T2 need not be supplied from the potential divider shown. A suitable circuit supplying a variable or constant control voltage may be used. One particularly suitable circuit is shown in Fig. 2. In this, one resistance of the potential divider is a temperature-sensitive resistor RT, having a characteristic which compensates for variations in the gain of the FET with temperature. Fig. 3 shows another means of providing compensation for variations in the gain of the FET, in this case due to temperature variations. In this example the resistor R1 of Fig. 1 is replaced by a temperature-sensitive resistor RS, having the appropriate temperature characteristic. CLAIMS

1. An amplifier circuit through which includes an FET having its source and drain connected through a first resistance across a first voltage source, an NPN transistor having its emitter connected to the drain of the FET and having its collector connected through a second resistance to a second voltage source, a third resistance connected between the collector of the transistor and the gate of the FET, and circuit means for applying a control voltage to the base of the NPN transistor to define the operating point of the FET.

2. An amplifier circuit as claimed in Claim 1 in which the circuit means comprises a potential divider connected across a reference voltage supply.

3. An amplifier circuit as claimed in Claim 2 in which one element of the potential divider comprises a temperature sensitive resistance.

4. An amplifier circuit as claimed in either of Claims 1 or 2 in which the said first resistance is a temperature sensitive resistance.

5. An amplifier circuit as claimed in any one of the preceding claims in which the emitter of the NPN transistor is connected to the drain of the FET by way of an inductance.

6. An amplifying circuit as claimed in any one of Claims 1 to 5 in which the NPN transistor is a bipolar transistor.

7. An amplifying circuit as claimed in any one of Claims 1 to 6 in which a radiofrequency signal to be amplifier is applied to the gate of the FET and the amplified signal is obtained from the drain of the FET.

8. An amplifying circuit substantially as herein described with reference to the accompanying drawings.