GB2149603A - Logic circuits - Google Patents

Abstract

An integrated injection logic circuit of the type comprising a bipolar switching transistor (ST) and having a base-feed/collector load. To improve speed of switching, and to allow dense packing of logic components, a junction field-effect transistor (LJ) is incorporated as load between collector voltage line and the base of the switching transistor (ST). The gate of the junction field-effect transistor (LJ) may be referred to collector voltage (Vcc) (Figure 3). Alternatively, to allow selection of switching speed, the gate may instead be referred to a reference voltage (VR) (Figure 4). A logic array may be assembled from a plurality of circuits as above, and gates may be connected in common to reduce the number of input contacts required. Common connection may be afforded by means of a heavily doped semiconductor track extending across the junction field-effect transistors (LJ). <IMAGE>

Description

SPECIFICATION Logic circuits The present invention relates to Logic circuits and more particularly to those referred to as Integrated Injection Logic (12L) circuits.

This logic type, realised in bipolar integrated circuit technology, has various forms such as substrate fed logic (SFL) and integrated Schottky logic (ISL). The usual objectives of these logic families is to achieve maximum packing density of gates on the integrated circuit chip. One problem, of the basic 12L structure, is that the switching transistor 5T is used in an inverted mode and is fed by a lateral PNP transistor LT (Figure 1). This results in a relatively slow logic gate.

One known modification to the basic structure is the ISL structure (Figure 2), where the switching transistor 5T may include multiple collectors, each usually, but not always, of Schottky barrier type, and where the base of the switching transistor 5T is fed from a resistor LR. The switching transistor 5T may be operated either in the multi-collector inverse mode, or at some loss in packing density, in the normal mode. The chief loss in performance is due to the load resistor LR, which, with the transistor base-emitter and collector-emitter/collectorsubstrate capacitances usually limits the operational speed.

In accordance with the present invention there is provided an integrated injection logic circuit, a circuit of the type comprising a bipolar switching transistor and having a base feed/collector load; wherein there is included a junction field effect transistor (J-FET) to serve as this load, the channel thereof being connected between collector voltage line and the base of the switching transistor.

The gate of this J-FET may be connected to the collector voltage line. Alternatively, to permit modification of switching speed, the J-FET gate may instead be referred to a reference voltage line.

Switch speed is then determined by the reference voltage.

A logic circuit array may also be provided, an array comprised of a plurality of logic circuits constructed as aforesaid, wherein the gates of the junction field effect transistor (J-FET's) are connected in common - eg. by means of a heavily doped semiconductor track or by metallic conductor.

A junction field-effect transistor (J-FET) when incorporated as a base feed/collector load approaches the performance of an ideal current source load. The design can be chosen such that sufficient current is passed through the J-FETto charge/discharge nodal capacitance quickly without the use of excessive current when the switching transistor is ON. Further advantages can be gained from the structure adopted for the J-FET. Since the effect is majority-carrier only, no saturation effects, as in a PNP transistor load occur. Layout area is potentially smaller than that for either a PNP transistor or a resistor for most fabrication processes and, very significantly, a reduction can be achieved in the number of contacts needed per gate, eg. a reduction from three to two in a simple inverter.Furthermore the gate electrodes of a number of devices can be connected together so that a group of gates can be connected together so that a group of gates can have their speed tailored to suit the requirement by means of a single control point. The J-FET feed can be used either with multiple-collector inverted transistors, or, with some loss of packing density, with standard transistors.

The specific advantages A J-FET feed are: improvement in speed of operation, due to the avoidance of PNP transistor load saturation and a reduction of parasitic capacitances achievable by smaller geometry layout; reduction of layout area, partly by simplification of device structure and partly by reduction of the number of essential external contacts (optional); and, an increase in versatility of operation by the inclusion of a high impedance current control node. A number of logic gate cells can be coupled together eg. by a track of n±type silicon connected across the J-FET device gates.

These cells then need only a single end contact. High nodal impedance means that no additional metallisation is needed to ensure uniformity of current between nominally identical gates.

In the drawings accompanying this specification: Figures land 2 are circuit diagrams of known integrated injection logic circuits, namely a conventional bipolar transistor feed circuit and a resistor feed schottky transistor circuit, respectively; and, Figures 3 and 4 are circuit diagrams of junction field-effect transistor base-feed/collector load circuits, each constructed in accordance with this invention, and wherein the gate of the field-effect transistor is referred to collector voltage and to reference voltage, respectively.

Embodiments of the invention will now be described, by way of example only, with reference to Figures 3 and 4 of the drawings.

In Figure 3 a NPN switching transistor 5T is shown.

A P-channel junction field-effect transistor LJ is included in circuit, its P-channel being connected between the base of the switching transistor ST and the collector voltage line Vcc from the previous logic circuit stage. The gate of the junction field-effect transistor Lj is, as shown, also connected to the collectorvoltage line Vcc.

The circuit shown in Figure 4 is of similar configuration except that the gate of the junction field-effect transistor LJ is referred to a reference voltage Vn. The switching transistor ST iS shown having a plurality of collectors. This enables fan-out to a plurality of following circuits.

A logic array may be assembled from a number of circuits constructed as described. The J-FET gates may be connected in common. As the gate impedance is high, it is convenient to do this by means of a heavily doped semiconductor (ie. n+ conductivity) track in the integrating substrate.

It is to be understood that the invention is not limited merely to those embodiments shown. Whilst the use of a P-channel J-FET has been assumed above, because of the simplicity of integration with NPN transistors, similar advantages could be gained using N-channel J-FETs, either with PNP switching transistors in circuit entirely complementary to those shown, or conceivably even with NPN devices with some layout comprises.

Claims (6)

1. An integrated injection logic circuit, a circuit of the type comprising a bipolar switching transistor and having a base feed/collector load; wherein there is included a junction field-effect transistor (J-FET) to serve as this load, the channel thereof being connected between collector voltage line and the base of the switching transistor.

2. A logic circuit, as claimed in claim 1,wherein the gate of the field-effect transistor is connected to the collector voltage line.

3. A logic circuit, as claimed in claim 1, wherein the gate of the field-effect transistor is connected to a reference voltage line.

4. An integrated injection logic circuit constructed, adapted and arranged to operate substantially as described hereinbefore with reference to and as shown in either Figure 3 or Figure 4 of the accompanying drawings.

5. A logic array comprised of a plurality of logic circuits, each as claimed in any one of the preceeding claims, wherein the gates of the junction fieldeffect transistors are connected in common.

6. An array, as claimed in claim 5, wherein the common gate connection is provided by a track of heavily doped semiconductor material.