GB2145903A - Sampled data signal processing apparatus - Google Patents

Abstract

Sampled data signal processing apparatus, such as for digital signal processing in a color television receiver, includes a phase translating device (70) for developing transformed signals ((R-Y), (B-Y)) by rotating them through a predetermined phase angle. The rotation angle is selected so that the modified signals (C1, C2) have more nearly maximum magnitudes so as to more efficiently utilize the dynamic range of the subsequent signal processing circuitry (72,40,42) or to provide reduced quantization step size in output signals (R, G, B). <IMAGE>

Description

SPECIFICATION Sampled data signal processing apparatus The present invention relates to apparatusfor processing sampled data signals.

In apparatus which processes a composite sampled data signal comprising two components, it is desirable thatthe components, when separated, have equal amplitudes. In this way, each component occupies the full dynamic range ofthe sampled data signal processing apparatus. This decreases the quantizing noise associated with each component and increases the signal-to-noise ratio. The present inven tion relates to apparatus which embodies this aim.

The present invention is particularly advantageous when employed in the chrominance signal processing section of a colortelevision (TV) signal processing system, Such systems separate video signals into luminance and chrominance signals. The chrominance signal can be considered a vector quantity having a magnitude and an anglewith respectto a reference angle. The chrominance signal may be projected onto orthogonal axes to develop orthogonal components ofthe chrominance signal. A chrominance sectionfurtherseparatesthe chrominance signals into chrominance components along a set of orthogonal axes, for example, (R-Y) and (B-V) components, along (R-Y) and (B-V) axes. For signals in the NTSC television system used in the United States, the luminance signal magnitude is between zero and 100 IRE units.In forming the colorvideo signal, the magnitude of the (B-V) chrominance component is modified by a factor of 0.493 and the (R-Y) chrominance component is modified by a factor 0.877 in order to restrict maximum signal amplitude overshoots to levels within the desired ranges. Thus, for a saturated blue signal, the maximum (B-V) component vector magnitude of 89 IRE units is modified by the factor 0.493 so that the maximum (B-V) magnitude is approximately 43.9 IRE units. Similarly, for a saturated red signal,the maximum (R-Y) component vector magnitude of 70 IRE units is modified bythefactor 0.877sothatthe maximum (R-Y) magnitude is approximately 61.4 IRE units. These signals can be either positive or negative in polarity.

An NTSC-standard system, however, must restore the (B-V) and (R-Y) components to 89 and 70 IRE units, respectively, in orderto reproduce a displayed picture accurately reproducing saturated blue and saturated red portions of the pictures. Conventionally, this restoration is accomplished as a final processing operation by selecting the relative weighting coefficients provided buy a color signal matrix. The color signal matrix weights and combines the luminance signals and the chrominance component signals to produce red R, green G and blue B drive signals in standardized proportions. These R, G and B drive signals are applied to the kinescopeto produce the picture display.

A problem isthatthe (B-V) component, which has a relatively lesser magnitude (i.e. *43.9 IRE units), must produce the greatest display drive signal (i.e. *89 IRE units) so that noise or errors introduced by such processing will tend to be more noticeableto a viewer than will errors in the (R-Y) component signal. This problem is aggravated where similaror common circuitry is employed to process (R-Y) and (B-V) signals because the dynamic range of such circuitry must be designed to acceptthe largeramplitude (R-Y) signals. As a result, the (B-V) signals do not fully utilize the available dynamic range ofthe processing circuitry.To reduce these problems, it would be desirable to increase the magnitude of the (B-V)componentsignal relative to that of the (R-Y) component signal, and to do so at a relatively early stage in its processing, rather than atthe end thereof.

The above-described problem is aggravated in digital television signal processing circuitry because the quantizing resolution inherent in a digitized signal limits the numbers of different levels of R, G and B drive signals which can ultimately be developed. For example, a system may employ a seven-bit (128 level) analog-to-digital converter (ADC) to digitize an analog video signal range between the tip of the synchronizing signal (-40 IRE units) and maximum white level (+100 IRE units). The resulting quantizing resolution is about 140/127 = 1.10 IRE units per step. The 43.9 IRE unit (B-V) signals correspond to about 39 digital steps and the 61.4 IRE units (R-Y) signals correspond to about 55 digital steps.This illustrates that the magnitude ofthe (B-V) signals is significantly less than that ofthe (R-Y) signals.

The most severe problem arises, however, due to limited quantization in digital signal processing and in reconverting the quantized signals to analog signals.

Consider, for example, a TV digital signal processing system in which the (R-Y) and (B-V) digital signals are limited to six bits (64 levels). Because the digital signals have to reproduce both positive and negative signal excursions, one digital level is the zero level leaving 63 non-zero valued digital levels. Further, because the positive and negative peak magnitudes are symmetrical, only +31 digital levels are usable for signal excursions (i.e. 62 non-zero levels).

Assuming thatthe scaling ofthe (R-Y) digital signals is optimized to fully encompass the available range of digital levels, then equivalently scaled (B-V) digital signals will encompass only [(43.9 IRE units)/(61.4 IRE units)] x (+31) levels = *22.16 digital levels so that only *22 levels are actually utilized. When the chrominance signals are restored to full level as output signals, the (B-V) component signal, for example, will encompass *89 IRE units butwill be constrained to the central *22 levels of the (B-V) digital chrominance signal.Thus, the output quantizing resolution is about 4.05 IRE units per step which is significantly and undesirably large and can cause noticeable color contours in the TV picture. These contours cause the picture to have an artificial appearance.

If the (B-V) component were to be increased to occupythe entire +31-level range,thentheoutput quantizing resolution significantly would improve to 2.87 IRE units per step. But this cannot be done simply by multiplying the (B-V) signal to increase its magni wde range because to do so would merely substitute *22 different ones of the *31 available levels spread overthe entire *31level rangeforthe +22 levels in the center thereof. Thus, some additional processing is required so that more ofthe available digital levels are employed to accurately represent the (B-V) chrominance component.

The chrominance components may be represented along different orthogonal coordinate axes than the (R-Y), (B-V) axes. If a different set of axes are chosen, then the maximum amplitude ofthe components as separated may be more nearly equal than the components represented along the (R-Y), (B-V) axes.

Representing the chrominance components along these axes allows better resolution ofthe component in subsequent processing. It is to the basic problem arising in this specific application that apparatus according to our invention is a solution.

Accordingly, the present invention comprises a phase translation device accepting first and second signals in a predetermined phase relationship to a reference phase, and developing signals transformed by a predetermined phase angle rotation selected to make ones ofthe signals so developed have comparable magnitudes so thatthe dynamic range of subse quent processing apparatus is efficiently utilized.

In one embodiment of the invention, the predeter- mined phase angle is selected to obtain a desired effect in the output signal to reduce the effects of quantizing resolution limitations of the input signals.

In the drawings: FIGURES 1 and 5 are schematic diagrams in block diagram form of digital signal processing apparatus including embodiments of the present invention; FIGURES 2 and 3 are diagrams depicting relationships of signals and parameters associated with the apparatus of FIGURES 1 and 5; and FIGURES 4,6 and 7 are schematic diagrams of particular arrangements useful in the apparatus of FIGURES 1 and 5.

In the drawings, arrows having slash marks represent signal paths for multiple-bit parallel digital signals having the number of bits indicated bythe numeral neartheslash mark.

It is noted that an N-bit digital signal has 2N possible magnitudes or levels. These levels can be organized to correspond to zero and (2N.1) non-zero magnitudes. In the case of a "symmetrical" signal, these magnitudes can be organized to correspond to a central zero value, and (2N-1) magnitudes of one polarity and (2'-1 ) values of an opposite polarity. In the description herein,the exemplary digital chrominance signals are ofthesort having a central zero value, unless specifically stated otherwise.Further, the digital signals herein are considered to be symmetrical about the zero value and so only (2N 1-1) magnitudes of each polarity are actually availablefor use (i.e.for N=8, only 127 positive and 127 negative magnitudes are actually available). Therefore, the ratio factor K used herein can have different values depending upon the organization of the magnitudes represented by the digital signals. Also, the present invention is applic abletoquantized (sampled data) signals in general,of which digital signals are an example.

FIGURE 1 shows a digital signal processing arrangementfor a colo;TV receiver. Analog composite video signals ACV are converted into seven-bit digital video signals DV by analog-to-digital converter (ADC) 10.

ADC 10 samples video signal ACV atfour-timesthe frequency of the colorsubcarrier signal, i.e. 4fsc = 4 x 3.58 Megahertz in the NTSC system, in response to sampling clock signal 4fsc. ADC 10 also receives a "dither" signal fHt2 having an amplitude correspond ing to one-haWf ofthe least significant bit (1/2 LSB) value ofthe digital word for the purpose of increasing the apparent quantizing resolution to approximate that of an eight-bitADC. Signals 4fsc andfHX2 are deveíoped as described below. It is noted that digital signal processing is performed at the rate of the sampling signal 4fscwhich is phase andfrequency locked tothe colorsubcarriersignalfsc, oratasubmultiplethereof.

Seven-bit digital video signals DVare applied to digital comb filter 11 which is arranged to produce eight-bit digital luminance signalsYandeight-bit digital chrominance signals C. Digital luminance signalsVare applied to digital luminance processor 12 which performs operations such-as peaking the digital luminance signals and multiplying the-digital luminance signals to adjust the contrast level:ofthe resulting picture. Processor 12 producesprocessed eight-bit digital luminance signals which-are converted into corresponding analog luminance signals Y' by digital-to-analog converter (DAC) 44.

Seven-bit digital video signals DV are applied to digital deflection processor 14 which developsthe various horizontal and vertical drive signals and synchronizing signals required for signal processing, deflection and picture display functions. In particular, processor 14 develops dither signal fw2 at one-halfthe horizontal line rate, i.e. signal fHX2 is "high" for one horizontal line and is "low" for the next line. Processor 14 develops color key pulse CKP which is "low" (enabling) during each occurrenceofthecolorsuboar- rier reference burst signal which is included in the horizontal blanking intervals of the video signals.

Digital chrominancesignalsCare applied to digital chrominance bandpassfilter 16which,forexample, passes only signals near the colorsuboarrierfrequen- cyfsc. Because this filter includes several accumulators (adders) it produces fourteen-bit output filtered digital chrominance signals and exhibits a peak gain of about sixty-four.

The filtered digital chrominance signals from filter 16 are adjusted to a standardized magnitude by digital automatic chrominance control (ACC) gain block 18 which provides attenuation by afactor Of at least two and truncatesthe digital chrominance signalsto eight bits. The eight-bit output digital signalsfrom ACC gain block18arestandardized in magnitudabya negative feedback loop including burstsamplerand comparator 20. In response to color key pulse CKP, burst sampler 20 samples the color subcarrier reference burst signal portion ofthe digital chrominance signals produced byACC gain block 18. These samples are compared to a reference level, e.g.1toa level representing the desired magnitude of the color subcarrier reference burst signal and the peak digital magnitudes which can be accommodated by the digital chrominance signal processing circuitry. As a result of that comparison, burst sampler and compa rator 20 applies a gain control signal to ACC gain block 18 to set its gain (more specifically, to set its attenuation) to standardize the magnitude ofthe color subcarrier reference burst signal. This attenuation setting is maintainedthereafterto also adjust the magnitude ofthe chrominance signals produced by ACCgain block 18.So asto avoid overrangevalues of the (R-Y) digital signals, which are of larger magnitude than are the (B-V) digital signals, the maximum range ofthe (R-Y) digital signals is standardized at less than theequivalentof +127 digital levels. For purposes of the fotlowing description, this is assumed to be about 85% which is about *108 digital levels.

Digital chroma signal demodulator 22 separates the standardized digital chrominance signals from ACC gain block 18 into quadrature chrominance signal components (R-Y) and (B-V). Because (R-Y) and (B-V) components are simply alternate samples in the sequence of digital chrominance signals, demodula tor22 can beasimpledemultiplexerand may include a low pass filter.

The eight-bit (R-Y) and (B-V) component digital signals of the colorsubcarrier reference burst portion are compared in phasetothecolorsubcarrierclock signal fsc by phase comparator and filter24 in response to color key pulse CKP. Phase comparator and filter 24 develops a signal representative ofthe phase error between the actual phase ofthefsc sampling signal and the desired phase thereof relative to the color subcarrier reference burst signal. Phase comparator and filter 24 also filters this phase error signal and applies itto clock generator 26 which includes a voltage controlled oscillator (VCO) operating at the frequency 4fsc.The frequency ofthe VCO is adjusted thereby to be at exactlyfourtimes the color subcarrierfrequency and in phase locktherewith.

Clock generator 26 further includes a digital divider to divide the sampling signal 4fsc by two to produce clock signal 2fsc and by fourto produce clock signal fsc.

The eight-bit demodulated (R-Y) chrominance component produced by demodulator 22 encompasses onlythe central + 108 levels ofthe possible + 127 levels of an eight-bit signal. The demodulated (B-V) component encompasses (43.9/61.4) x 108 = 77.2 levels of which +77 levels actually are produced. For the reasons setforth previously, it is particularly desirable to increase the number of levels encompassed by the (B-V) component signal. The digital levels encompassed bythe (B-V) component signal correspond to the central *77 levels and zero.

Digital fixed-phase rotation circuit 70 receives the (R-Y) and (B-V) digital chrominance components from demodulator 22 and develops modified digital chrominance components C1 and C2 therefrom. C1 and C2 are in quadrature phase relationship as are (R-Y) and (B-V), and have been rotated through a predetermined phase angle a with respect two (R-Y) and (B-V) in accordancewith the phasetranslation equations C1 =(R-Y)Kcosa(B-Y)Ksin a [1] and C2 = (R-Y)Ksin a + (B-V)Kcos a [2] where K is a gain scaling factor.

Phasors representing chrominance components (R-V), (B-V) and rotated chrominance components C1, C2 are illustrated in FIGURE 2. The selection criteria for the angle a and thescaling factor K are discussed below. It is important to note that the phases of C1 and C2 do not correspond to any conventional chrominance phase angle, such as I, Q or (R-V), (B-V) or U, V (in PAL), although such correspondence is not precluded.

FIGURE 4 is an exemplary embodiment of digital fixed-phase rotation circuit 70 employing read only memories (ROMs). Digital chrominance components (R-Y) and (B-Y) arealternatelyapplied by multiplexer 80to address both of ROMs 82 and 84 in response to clock signal 4fsc. ROM 82 includes 256 seven-bit storage locations each of which stores a digital representation ofthe product of its address, the gain scaling factor K and the sine of angle a. Similarly, ROM 84 includes 256 seven-bit storage locations each of which stores a digital representation of the product of its address, the gain scaling factor K and the cosine of angle a.ROM 82 is enabled to produce output signals when clock signal 2fsc is at a logical '0' level (as indicated bythe circle atthe enable input EN of ROM 82) and ROM 84 is enabled to produce output signals when clock signal 2fsc is at a logical '1' level.

In operation overfour cycles of clock signal 4fsc, ROM 84 processes (R-Y) then (B-Y) address data and then ROM 82 processes (R-Y) then (B-Y) address data so that thefourterms of equations [1] and [2] are applied to the input ofdemultiplexing latches 86 in a predetermined sequence. Demultiplexing latches 86 decode the clock signals 2fsc and 4fse to store in four digital latches the four constituent terms which are thereafter applied to su btractor 88 and to adder 90 to form the modified chrominance component signals C1 and C2 in accordance with equations [1] and [2], respectively.

Referring again to FIGURE 1,digital tint control circuit72 controllablyshiftsthe phase angles of modified chrominance components Cl and C2overa range of zero to about *50 degrees in response to a control signal TINT. Control signal TINT is controllable by a viewer to introduce additional positive or negative phase rotation to shift the tint of the displayed picturemoretowards red colors or more towards green colors in accordance with viewer preference. Thus, chrominance component samples CIT and C2T are each rotated in phase by circuits 70 and 72 over an angle of a + 50 degrees with respectto the (R-Y) and (B-Y) chrominance components.

Digital saturation multiplier and multiplexer 40 mullplexestheC1andC2componentsin response to the clock signal fsc. Multiplier40, for example, employs one digital multiplierwhich is multiplexed to adjust the magnitudes of both the C1Tand C2signals in accordance with control input signalsfor color saturation (SAT) controllable by a viewer in accordance with his or her preference for more or less vivid color. The multiplexed modified C1Tand C2chrnmi- nance components are supplied to a chrominance demultiplexer 42. The two seven-bit signals represent ing chrominance components C1T and C2T modified in response to SAT(14 bits total) are multiplexed sequentially over one cycle oftheclocksignalsfsc which includes four cycles of sampling clock 4fsc, i.e.

l1e Cland C2signals are transmitted sequentially as two groups ofthree bits and two groups of four bits.

This beneficially reduces the number of integrated circuit pins required from twelve to four when multiplexer-multiplier 40 is in one integrated circuit and demultiplexer42 is in another integrated circuit. It isfurther consistent with the data rates ofthe chrominance components which are processed at the 4fsc sampling signal rate through bandpass filter 16 and ACC gain block 18 and are each processed atthe fsc clock signal rate thereafter.

Chrcminance demultiplexer42 receives and demul tiplexes the two groups ofthree bits and thetwo groups offour bits to reform seven-bit C1Tand C2r digital chrominance components in response to clock signal fsc. These demultiplexed C1 T and C2T signals are respectively converted to analog chrominance components Cl' and C2' by digital-to-analog converters (DACS) 46 and 48.

Analog RGB matrix 50 receives analog luminance signals Y' and analog chrominance components C1' and C2' to develop analog color drive signals R, G and B. A conventional RGB matrix as is used with (R-Y), (B-Y) chrominance components will produce color drive signals which will not produce accurate colors in a television picture owing to the phase rotation introduced by circuit 70. Therefore, matrix 50 is modified from a conventional matrix to counteractthe imbalance which would otherwise result owing to the aforementioned phase rotation.

Analog RGB matrix 50 transforms luminance signal Y' and modified chrominance components C1' and C2' into color drive signals R, G and B according to the equations R = Y' + Rr C1' + R2C2' [3l G=V'+G1C1'+G2C2' [4] B = Y' + B, C1' + B2C2' [5] where the values of coefficients R1, R2, G, G2, B1 and B2 are determined by the NTSC system and the phase rotation angle a. It is noted that the values of these coefficients are also affected by the particular phosphors ofthe kinescope upon which pictures are reproduced.For example, with the phosphors employed by RCA Corporation in its kinescopes,the (B-Y) and (R-Y) components are restored to 90 and 104 IRE units, respectively, ratherthan to the 89 and 70 IRE units required for the NTSC standard phosphors.

FIGURE 3, for example, illustratesthevalues of coefficients B1 and B2 as a function of the phase rotation angle a.

Selection of the angle a is made so that the blue signal B has a reduced quantization step size relative tothatwhich it haswhen developed from the (R-Y) and (B-Y) chrominance components. Satisfactory improvement results when the angle a is selected in accordance with various criteria, two exemplary ones of which are described below.

Afirstcriterion isto selectthe angle asuch thatthe matrix coefficients are as small as possible. This entails,forexample, computing the values ofall six coefficients for values of angle a between zero and 360 degrees and examining the resulting data to select the angle resulting in the smallest coefficient. This examination is easily done by determining which of the coefficient pairs R1, R2 or G1, G2 or B1, B2 has the greatest possible value and then determining the smallestvalue for both coefficients of the pair.Forthe system employing RCA Corporation phosphors, this criterion is satisfied when the coefficients B1 and B2 have the same magnitude which occursfor os47 , 137 ,227 or317" as shown by the vertical dashed lines of FIGURE 3. It is noted that these angles occur at a rotation of 47" plus an integral number of 90" increments. It is not important which of the four possible phase rotation angles is employed because all provide equivalent results.

A second criterion is to selectthe angle a such that the maximum magnitudeswhich the chrominance components Cl, C2 can have are substantially equal so that most efficient use ofthe dynamic range is achieved, i.e. when the largest possible numberof digital values thereof are utilized. This critenorr is satisfied when os = 41 ,131 ,221 or31 10 as shown by the vertical long-short dashed lines of FIGURE3.

Again, it is not important which ofthefourangles isselected.

The values of the matrix coefficients and the quantizing resolutionvaluesaresetforth inTABLE I forthe angles a = 41 and a = 47 . Satisfactory values of gain scaling factor K, referred to above in relation to FIGURE 4, are incorporated so thatthe magnitudes of chrominance signals C1, C2 efficiently utilizethe range of digital values acceptable to that portion ofthe apparatus subsequentto phase rotation circuit 70, are also listed in TABLE I.

TABLE I a = 41' e = 470 Coefficient Value IRE Units/ Value IRE Units/ Steo Sten RI 0.873 1.40 0.828 1.31 R2 0.686 1.09 0.787 1.25 Gl -0.227 0.36 -0.202 0.32 G2 -0.288 0.46 -0.316 0.50 B1 -0.850 1.35 -0.971 1.54 B2 1.034 1.66 0.977 1.55 K 1.52 - 1.48 The values of gainscaling factor K in TABLE I provide that about 85% of the available magnitude range is utilized with usual saturation level settings so that about 15% remains to accommodate viewers preferring highly saturated (vividly colored) pictures.

FIGURE 5 shows a signal processing system which is a modification of that of FIGURE 1. FIGURE 5 differs in that digital comb filter 11 is eliminated. Digital luminance processor 12' differs from processor12 of FIGURE 1 in that it includes a luminancefilterto suppress the chrominance signals and to thereby producethedigital luminancesignals Y. Digital chrominance bandpassfilter 16 of FIGURE 5 suppres- ses luminancesignalstotherebyproducethedigital chrominance signals C.

The demodulated (R-Y) component signal pro- duced by digital chrominance component clemodula- tor22 is low-pass filtered by the (R-Y) digital comb filter 28 which produces a filtered (R-Y) signal.The demodulated (B-Y) component signal produced by digital chrominance component demodulator 22 is low-passfiltered bythe (B-Y) digital comb filter 30 which produces a filtered (B-V) signal.

Digital comb filters28 and 30 are, for example, relatively simple comb filters of the sortshown in FIGURE 6. Input signals are appliedto one input of digital adder 62 and to the input of 1 H delay device 60.

Delay device 60 is, for example, a FIFO dynamic random access memory (RAM) which provides a delay equal to the time of one horizontal line (1 H) by cyclically developing 227 addresses in response to the clock signal fsc, in the NTSC system. The delayed signal from delay device 60 is applied to the second input of adder 62 which produces a seven-bit sum signal.

Referring to FIGURES, digital saturation multiplier, tint control and multiplexer 40' is modified from multiplier40 of FIGURE 1 in that it performs phase rotation ofthe chrominance components (R-Y) and (B-V). This phase rotation includes rotation through a fixed angle afortransforming the (R-Y) and (B-V) components into the C1 and C2 chrominance components as described above and includes controllable rotation through an angle ss in accordance with the control signal TINT to accommodate viewer preference. In practice this is most efficiently implemented by adding the equivalent ofthe angle atothe value of tint control signal TINT.Further, it is efficient to aggregate the scaling factors K and SAT so that only one multiplier is required to perform both multiplications.

Tint control is performed by rotating the (R-Y) and (B-V) components, which represent quadraturevec- tors, angularly byan angle( +ss). This requiresthat multiplier40' multiply the (B-V) and (R-Y) digital components by factors SAT cos (a+il) and SATsin (a+j3) and then combinethe products according to known algebraic sum and difference equations.

When the signal magnitudes are modified by a single multiplier, multiplier40'must multiply byfactors K SATcos (a+I3), KSATcos (a+ss), KSATsin (a+ss) P) and K SAT sin (a+ ss). This modification to multiplier40' requires the addition oftwo additional latchesto store the two additional multiplication factors.

The apparatus described herein, particularlyADC 10, processors 12 and 14, filters 16,28 and 30, ACC gain block 18, burst sampler 20, demodulator 22, comparator 24, clock generator 26, multiplier and multiplexer40, demultiplexer42 and DACs 46 and 48, can be ofthe sort included in digital signal processing integrated circuitsfortelevision receivers available from ITT Semiconductors, I ntermetall, Freibu rg, West Germany and described in an ITT Semiconductors brochure entitled VLSlDigital System DIGIT2000, dated August1982. Implementation ofthe present invention in these integrated circuits, which include a memory to store control values, is an easily accomplishedmodification.For example, a fixed phase rotation angle a is incorporated by designating the storedvalue of control signal TINT corresponding to zero degrees oftint control phase rotation as being the value corresponding to predetermined angle a.

Gain scaling by the factor Kis incorporated by modifying the stored value of control signal SAT or of the nominal ACC level, or both, to accountforthe factorKand efficiently utilizethe available magnitude range. The analog RGB matrix of these integrated circuitsisthen modified by changing resistance values and by adding one resistor(forthe B1 coefficient) to provide the matrix coefficients of TABLE I. This is most conveniently accomplished when a = 227 is selected because the signs of the matrix coefficients (but notthe values) are unchanged when the color drive signal output pins are redesignated from R, G, B to B, R, G.

Modifications are contemplated to the present invention within the scope ofthe claims following.

For example, the scaling provided byACC gain block 18 can be aggregated with scaling factors Kand SAT and performed bya single multiplier 40 or40'.

It is further contemplated that analog matrix 50 be replaced by a digital RGB matrix 92 shown in FIGURE 7 receiving digital luminancesignalsVfrom luminance processor 12 and digital chrominance components C1 and C2 from demultiplexer42. Digital RGB matrix 92 employs digital multipliers and addersto operate in accordancewith equations [3]through [5] setforth hereinabove. Digital colorsignalsfromthe digital matrix 92 corresponding to R, G and B signals are appliedtothree digital-to-analog converters (DACS) 94,96,98 which develop the analog color drive signals R, G and B, respectively.

By way of further example, it is contemplated that the present invention be employed in conjunction with chrominance component demodulation systems otherthan the (R-Y), (B-V) system described herein. Thus, the present invention is satisfactorily employed with an I, Q or a U, V demodulation system.

Further, the present invention is also satisfactory in a system in which tint control is provided by modifying the phase ofthe sampling clock4fsc relative to that of the color subcarrier reference burst signal.

It is further contemplated that the objects of the presentinventionwill obtainwherethe(R-V) and (B-V) chrominance components are rotated through different angles.

Claims (15)

1. Signal processing apparatus comprising: a source for providing first and second signals each in predetermined phase relationship to a reference phase; transforming means coupled to said source for developing third and fourth signals from said first and second signals, wherein said third and fourth signals are developed by rotating said first and second signals by predetermined phase angle selected for making the maximum magnitudes of said third and fourth signals more nearly equal than are the maximum magnitudes of said first and second signals.

2. TheapparatusofClaim 1 whereinsaidtransforming means comprises: means for developing signals representative ofthe products of said first and second signals and the sine and cosine of said predetermined phase angle; and meansforcombiningthe predetermined ones of said signals representative of said products to produce said third and fourth signals.

3. TheapparatusofClaim 1 furthercomprising: a combining means coupled to said transforming means for combining said third and fourth signals in predetermined proportions to develop at least one output signal; and control means coupled between said transforming means and said combining means for controllably rotating the phases of said third and fourth signals in accordance with a control signal.

4. TheapparatusofClaim 1 whereinsaidtrans forming means includes: a control terminal for receiving a control signal; and means for controllably rotating the phases of said first and second signals in accordance with said control signal.

5. The apparatus of Claim 1 wherein said first and second signals are digital signals representative of analog signals having said quadrature phase relationship.

6. The apparatus of Claim Sfurthercomprising: digital-to-analog converting means coupled to said transforming means for converting said third and fourth signals to third and fourth analog signals, respectively; and analog matrixing meansforcombining said third and fourth analog signals in predetermined proportions to develop at least one analog output signal.

7. The apparatus of Claim Sfurthercomprising: digital matrixing means coupled to said transform ing meansforcombiningsaidthirdandfourth signals in predetermined proportions to develop first and second digital signals; and digital-to-analog converting meansforconverting said first and second digital signals to a plurality of analog output signals.

8. In a television receiver including meansfor providing color television signals, meansforproviding a sampling signal in predetermined phase phase relationship to a color subcarrier reference signal component of said color television signals, an analog-to-digital converter producing digitized samples of said color television signals in response to said sampling signal, and means for developing first and second digitized chrominance componentsfrom said digitized samples in accordance with said predetermined phase relationship of said sampling signal, chrominance processing apparatus comprising: phase transforming means coupled to said developing means for developing first and second modified digitized chrominance components related to said first and second digitized chrominance components by rotation through a predetermined phase angle; and combining means coupledto said phasetransforming means for combining said first and second modified digitized chrominance components in predetermined proportions to develop a plurality of analog color drive signals.

9. The apparatus of Claim 8 wherein said combining means comprises: digital-to-analog converting means for converting said first and second modified digitized chrominance components to first and second analog signals, respectively; and analog matrixing meansforcombining said first and second analog signals in said predetermined proportions to develop said plurality of said analog color drive signals.

10. The apparatus of Claim 8wherein said com bining means comprises: digital matrixing means for combining said first and second modified digitized chrominance compo nents in said predetermined proportions to develop first and second digital color drive signals; and digital-to-analog converting means for converting said first and second digital color drive signals to said plurality of said analog colordrive signals.

11. The apparatus of Claim 8wherein said phase transforming means comprises: means for developing digital signals representative of the products of said first and second digitized chrominance components and the sine and cosine of said predetermined phase angle; and means for combining predetermined ones of said digital signals representative of said products to produce said first and second modified digitized chrominance components.

12. The apparatus of Claim 8 further comprising tint control means coupled between said phase transforming means and said combining means for controllably rotating the phases of saidfirstand of said first and second modified digitized chrominance components in accordance with a control signal.

13. The apparatus of Claim 8 wherein said phase transforming means includes: a control terminal for receiving a tint control signal; and means for controllably rotating the phases of said first and second modified digitized chrominance components in accordance with said control signal.

14. Signal processing apparatus substantially as hereinbefore described with reference to Fig. 1 or Fig.

5 ofthe accompanying drawings or any ofthe described implementations or alternatives thereof.

15. Television apparatus including signal processing apparatus according to claim 14.