GB2145546A - Magnetic bubble memory system - Google Patents

Abstract

A magnetic bubble memory system has a pair of data buffers (13, 16) between a magnetic bubble memory (9) and a host computer (8). Each of the buffers has a capacity corresponding to one page of the bubble memory. When one of the buffers performs data transfer with the host computer, the other buffer performs data transfer with the bubble memory. A buffer state discriminating/checking circuit (52) checks whether or not the buffers are both full, in a read operation of the bubble memory, or both empty in a write operation of the bubble memory. When the result of the check indicates that the buffers are both full or empty, a control circuit (50) connected to the output of the buffer state discriminating/checking circuit causes the operation of the bubble memory to be temporarily stopped. <IMAGE>

Description

SPECIFICATION Magnetic bubble memory system The present invention relates to a magnetic bubble memory system in which data transfer between a host computer and a magnetic bubble memory is performed through a pair of data buffers.

The magnetic bubble memory is a memory of a shift-register type in which magnetic bubbles are shifted on a propagation path on the bit basis or bit by bit by a rotating field.

Accordingly, writing and reading of data in and from the magnetic bubble memory are preformed serially on the bit basis so that data of a single bit is transferred every rotation cycle of the rotating field.

As is well known, the magnetic bubble memory of this type is generally of a majorminor architecture, wherein the number of pages is equal to the number of bits contained in one minor loop and each page has a storage capacity corresponding to the number of the minor loops.

Fig. 1 is a view showing an arrangement of the magnetic bubble memory of the majorminor architecture mentioned above. In the figure, numerals leo to 1.-1 denote n minor loops for holding and storing magnetic bubbles representative of data information, each minor loop having a capacity of m bits.

Numeral 2 designates a write line used for writing data, and 3 a read line used for reading out data.

In writing data in the minor loops, bubbles are generated by a bubble generator 4 in correspondence with logic "1" and "0" of data. When the bubbles come to the position of a swap gate 5, the latter is driven to transfer the bubbles to the minor loops. The swap gate 5 is connected in common to all the minor loops so that the bubbles present on the write line 2 can be simultaneously transferred to the minor loops. In this manner, data corresponding to the number n of the minor loops are written through a single writein operation. This quantity of data is referred to as a page. Accordingly, it can be said that a single page has a data capacity corresponding to the number of the minor loops. Further, since m bits are contained in each of the monor loops, the magnetic bubble memory has a storage capacity corresponding to m pages.

In a reading operation, when the bubbles belonging to a page requested to be retrieved come to the position of a replicator 6, the replicator 6 is driven so that the bubbles of all the minor loops are transferred to the read-out line 3. In this case, data of n bits are read out for the single page as in the case of the writein operation. The bubbles thus read out are transferred to a bubble detector 7 through which the data are serially outputted starting from the data of the minor loop 10.

On the other hand, data transfer to and from the host computer is generally performed parallel on the eight bit basis. Under the circumstance, a data buffer having a function for converting the serial data to the parallel data and vice versa is usually provided between the host computer and the magnetic bubble memory.

In the hitherto-known magnetic bubble memory system, the capacity of the data buffer is on the order of 1 to 3 bytes, which is remarkably small when compared with a page of data of the magnetic bubble memory, imposing thus a considerable restriction on the time required for the data transfer between the magnetic bubble memory and the host computer. More specifically, when data is to be read out from the magnetic bubble memory, the host computer has to fetch the data of eight bits in parallel every time a set of eight serial data are made ready in the data buffer. Similarly, in the case where data is to be written in the magnetic bubble memory, the host computer has to transfer the 8-bit parallel data to the data buffer every time 8bit serial data are transferred to the magnetic bubble memory from the data buffer.

Japanese Patent Application Laid-Open No.

54-146934 laid open on November 16, 1979 has proposed a system in which a pair of data buffers each having a capacity corresponding to one page of a magnetic bubble memory are provided so that one of the data buffers performs the data transfer with a host computer when the other performs the data transfer with a magnetic bubble memory. According to this system, restriction imposed on the time required for the data transfer as described hereinbefore is certainly obviated.

However, a problematic situation may arise in the case where notwithstanding that after the transfer of data of the first page from the magnetic memory to one of the data buffers, data of the succeeding page is being transferred to the other data buffer, the host computer does not fetch the data from the one data buffer. By turns, data of the third page are next to be transferred to the one data buffer. However, when the data transfer of the third page is forcibly carried out regardless of the jamming situation mentioned above, the data of the first page will then be destroyed before being fetched by the host computer.

Similar situation will arise in the case where data are to be written in the magnetic bubble memory from the host computer. More specifically, when data is to be transferred from one of the data buffers to the magnetic bubble memory in succession to the data transfer of the preceeding page from the other data buffer to the bubble memory, there may arise such a situation in which no data are present to be written in the magnetic bubble memory if the data of the succeeding page have not been transferred to the said one buffer data from the host computer.The occurrence of the problems mentioned above is due to the fact that the operation of the magnetic bubble memory is asynchronous with the operation of the host computer for accessing the data buffers while the operation of the magnetic bubble memory is usually performed in such a manner that the completion of operation for data of one page is immediately followed by the operation for the data of the succeeding page.

An object of the present invention is to provide a magnetic bubble memory system in which the operation of a magnetic bubble memory is temporarily stopped when a state exists in which data transfer can not take place between data buffers and the magnetic bubble memory.

According to the present invention, there is provided a magnetic bubble memory system in which data buffer means including a pair of data buffers each having a capacity corresponding to one page of a magnetic bubble memory is provided between said magnetic bubble memory and a host computer so that one of said data buffers performs data transfer with said host computer when the other data buffer performs data transfer with said magnetic bubble memory, said magnetic bubble memory system comprising: a control circuit for controlling the operation of said magnetic bubble memory, said control circuit generating a first pulse signal associated with the inputting of data of one page to said data buffer means and a second pulse signal associated with the outputting of data of one page from said data buffer means, said control circuit also generating a checking signal prior to initiation of the operation of said magnetic bubble memory for each page of data; discriminating means for receiving said first and second pulse signals from said control circuit to discriminate a first state of said data buffer means in which said data buffers are both full or both empty and a second state of said data buffer means which is other than said first stage; and gate means applied with the output of said discriminating means and said chekcing signal from said control circuit for passing the output of said discriminating means upon application of said checking signal, the output of said gate means being connected to said control circuit so that said control circuit causes initiation of the operation of said magnetic bubble memory for each page to be stopped when the output of said discriminating means indicating said first state of said data buffer means is passed through said gate means and to be executed when the output of said discriminating means indicating said second state of said data buffer means is passed through said gate means.

The above and other objects and features of the present invention will be apparent when reading the following detailed description in conjunction with the accompanying drawings, in which: Fig. 1 is a view showing a general arrangement of a magnetic bubble memory of majorminor architecture; Fig. 2 is a block diagram showing a magnetic bubble memory system according to an embodiment of the present invention; Fig. 3 shows an exemplary circuit configuration of buffer state discriminating/checking circuit shown in Fig. 2; Fig. 4 shows a timing chart for illustrating the operation of the circuit of Fig. 3 when data is read out from a magnetic bubble memory by a host computer; and Fig. 5 shows a timing chart for illustrating the operation of the circuit of Fig. 3 when data is written in the magnetic bubble memory from the host computer.

Referring to Fig. 2 which shows in a block diagram a magnetic bubble memory system according to an embodiment of the invention, numeral 60 denotes a so-called bubble memory controller. The controller 60 includes data buffers 13 and 14 each of which has a capacity corresponding to one page of a magnetic bubble memory 9 and is composed by a RAM and a parallel/serial converter circuit. A selector 15 serves to select either the data buffer 13 or the data buffer 14 which is to be connected for effecting the parallel data transfer with a host computer 8. More specifically, when a switching signal INI applied to the selector 15 is "H", the data buffer 13 is connected to the host computer 8 through a parallel data bus 17, while the data buffer 14 is connected to the host computer 8 through a parallel data bus 18 when the switching signal INI is "L".On the other hand, a selector 16 serves to select the data buffer 13 or the data buffer 14 which is to be connected to the magnetic bubble memory 9 for effecting the serial data transfer with the latter. More specifically, when a switching signal IN2 applied to the selector 16 is "H", the data buffer 13 is connected to the magnetic bubble memory 9 through a serial data bus 19, while the data buffer 14 is connected to the bubble memory 9 through a serial data bus 20 when the switching signal IN2 is "L".

With the arrangement of the magnetic bubble memory system mentioned above, operation will now be described on the assumption that data are read out from the magnetic bubble memory 9 by the host computer 8.

In precedence to the operation, the switching signals INI and IN2 are both reset to the logical state or level "H", whereby the data buffer 13 is selected. When the transfer of data of a first page from the magnetic bubble memory 9 is initiated, the data are temporarily stored in the data buffer 13 through the serial data buses 12 and 19. The data buffer 13 is in the state ready for data transfer to the host computer 8 at a time point when the data transfer of the first page to the data buffer 13 has been completed. Subsequently, the reading of data from the data buffer 13 by the host computer 8 takes place by way of the parallel data paths 17 and 11.

Upon completion of the data transfer of the first page from the magnetic bubble memory 9 to the data buffer 13, the switching signal IN2 is changed over to "L" level. Thus, the magnetic bubble memory 9 and the data buffer 14 are connected to each other through the serial data buses 12 and 20. In this state, the host computer 8 is performing data transfer for the first page with the data buffer 13, while data of the succeeding page are being transferred from the magnetic bubble memory 9 to the data buffer 14. Consequently, the data transfer to the host computer 8 can be carried out independent of the data transfer from the magnetic bubble memory 9.

Upon completion of fetching the first page data by the host computer 8 from the data buffer 13, the switching signal IN1 is set to "L", resulting in that the host computer 8 is connected to the data buffer 14 through the parallel data bases 11 and 18. In this way, by providing a pair of data buffers, one of the data buffer can perform the data transfer with the magnetic bubble memory while the other is performing data transfer with the host computer.

The operation for writing data to the magnetic bubble memory 9 from the host computer 8 is carried out in the utterly similar manner.

Again referring to Fig. 2, the bubble memory controller 60 includes a control circuit 50 for controlling the sequence of operations of the magnetic bubble memory, and an interface register file 51 for performing data communication with the host computer 8. As is well known, when a predetermined command issued by the host computer 8 is set in a command register incorporated in the interfface register file 51, the control circuit 50 causes the magnetic bubble memory 9 to perform the operation based on the command.

The bubble memory controller 60 further includes a buffer state discriminating/checking circuit 52 which is characteristic of the present invention and serves to discriminatively determine the state of the data buffers 13 and 14 on the basis of information concerning the inputting of data of one page to the data buffer 13 or 14 and the outputting of data of one page from the data buffer 13 or 14, to thereby supply to the control circuit 50 at a predetermined check cycle a signal 48 indicative of whether the data transfer between the magnetic bubble memory 9 and the data buffer 13 or 14 is possible or not.

The circuit 52 also generates the switching signals IN1 and 1N2 mentioned hereinbefore.

A signal 41 supplied to the buffer state discriminating/checking circuit 52 is one which is generated each time data of one page has been read out from the bubble memory and inputted to the data buffer 1 3 or 14 in the case of a reading operation of the bubble memory and each time data of one page has been outputted from the data buffer 13 or 14 and transferred to the bubble memory in the case of a writing operation of the bubble memory. The control circuit 50 which control the operation of the bubble memory, can recognize the completion of operation of one page of the bubble memory, thereby generating the signal 41 each time the operation of one page is completed.A signal 42 supplied to the buffer state discriminating/checkig circuit 52 is one which is generated each time data of one page has been outputted from the data buffer 13 or 14 and read by the host computer in the case of the reading operation of the bubble memory and each time data of one page has been inputted from the host computer to the data buffer 13 or 14 at the case of the write operation of the bubble memory. The control circuit 50 includes a counter which is incremented each time the host computer accesses to the data buffer 13 or 14 for data of eight bits and which generates the signal 42 each time the counter reaches a count corresponding to one page.

Fig. 3 shows an example of a concrete circuit configuration of the buffer state discriminating/checking circuit 52. Consideration being made on the assumption that data is to be read out from the magnetic bubble memory 9 by the host computer 8, it is sufficient to check whether or not the data buffers 13 and 14 are both full of data transferred from the bubble memory 9 in order to know whether data transfer to the data buffer 13 or 14 from the bubble memory 9 is permissible or not.

In Fig. 3, numerals 23 and 24 denote flipflops. The flip-flop 23 serves to indicate which of the data buffers 13 and 14 is supplied with data from the bubble memory 9. On the other hand, the flip-flop 24 indicates which of the data buffers 13 and 14 is accessed by the host computer 8. More specifically, the flipflop 23 indicates that the bubble memory 9 accesses the data buffer 13 when the output Q of the flip-flop 23 is "H", while indicating the access to the data buffer 14 when the output Q thereof is "H". On the other hand, the flip-flop 24 indicates that the host computer 8 accesses the data buffer 13 when the output 0 thereof is "H", while indicating the access to the data buffer 14 when the output Q thereof is H".

The state of the flip-flop 23 is switched in response to the above-described clock signal 41 supplied from the control circuit 50 upon every completion of the data transfer of one page to the data buffer from the bubble memory. Accordingly, the data transfers from the bubble memory to the data buffers 13 and 14 are performed alternately on the page basis in response to the signal 41.

The state of the flip-flop 24 is changed over in response to the above-described clock sig nal 42 supplied from the control circuit 50 upon every completion of the fetching of onepage data by the host computer 8 by making access to the data buffer. Accordingly, the data buffers 13 and 14 are alternately selected upon every transfer of one-page data to the host computer 8.

As will be appreciated from the foregoing, the Q output signals of the flip-flops 24 and 23 are made use of, respectively, as the switching signals IN1 and IN2 mentioned hereinbefore.

Numeral 46 denotes a reset signal applied to R-terminals of the flip-flops 23 and 24 from the control circuit 50 prior to the operation of the bubble memory 9. Upon application of to the signal 46, the flip-flops 23 and 24 are reset so that the data buffer 13 is initially designated to be accessed by the buffer memory 9 as well as by the host computer 8.

Flip-flops 21 and 22 serve to indicate whether or not the data buffers 13 and 14 are full of data transfferred from the magnetic bubble memory 9. More specifically, the flipflop 21 indicates the state of the buffer memory 13 while the flip-flop 22 indicates that of the data buffer 14. When the 0 output of the flip-flop 21 is "H", it is indicated that the data buffer 13 is full of data (FULL A), while the Q output of the flip-flop 22 at the level "H" indicates that the data buffer 14 is full (FULL B). The 0 outputs of the flipflops 21 and 22 are applied to the inputs of an AND gate 31 whose output 31' indicates whether or not the data buffers 13 and 14 are both full of data (FULL).

The control circuit 50 for the magnetic bubble memory checks the output 31' of the AND gate 31 immediately before operation of the bubble memory for each of the pages is started. When the output of the AND gate 31 indicates "FULL", initiation of operation of the bubble memory for the succeeding page is stopped. To this end, there is provided an AND gate 32 having inputs supplied, respectively, with the output 31' of the AND gate 31 and a checking signal 47 generated by the control circuit 50 immediately before initiation of operation of the bubble memory on the page basis.The control circuit 50 receives the output 32' of the AND gate 32 through an OR gate 39 for stopping initiation of operation of the bubble memory for the succeeding page when the output 48 of the OR gate 39 is "H" while allowing operation of the bubble memory to be initiated when the output 48 is The OR gate 39 is shown to receive not only the output 32' of the AND gate 32 but also the output 38' of an AND gate 38 which is provided in conjunction with a writing operation of the bubble memory as will be explained in later. A read pulse RD and a write pulse WR are inputted to the AND gates 32 and 38, respectively, so that the OR gate 39 passes onto the output 48 thereof only the output 32' of the AND gate 32 in the read operation of the bubble memory and only the output 38' of the AND gate 38 in the wriging operation of the bubble memory.

Fig. 4 is a timing chart for illustrating the operation of the buffer state discriminating/checking circuit 52 shown in Fig. 3 in the case where data is read out from the magnetic bubble memory by the host computer. In Fig. 4, the ON/OFF operation of the rotating field is shown at (a), and a replicate pulse signal applied to the replicator gate is shown at (b). When a Read Bubble command is set from the host computer 8 into the command register of the interface register file 51, the control circuit 50 generates the reset signal 46 (sec (c) in Fig. 4) at a time instant to for resetting the flip-fflops 23 and 24 of the buffer state discriminating/checking circuit 52, and then causes a rotating field generating coil (not shown) to apply a rotating field to the bubble memory 9 until the designated page is reached.Upon reaching the designated page, the replicator gate is driven to allow data of one page to be read out. The data are detected by the bubble detector driven subsequently and transferred to the data buffer 13. In Fig. 4, (d) represents the pulse signal 41 applied to the buffer state discriminatingjchecking circuit 52 from the control circuit 50 upon every completion of the data transfer of one page to the data buffer 13 or 14 from the bubble memory, (e) represents the pulse signal 42 applied to the buffer state discriminating/checking circuit 52 from the control circuit 50 upon every completion of the data fetch of one page from the data buffer 13 or 14 by the host computer 8, (f) and (g) represent the switching signals IN1 and 1N2 applied to the selectors 15 and 16, respectively, (h) and (i) represent the 0 outputs of the flip-flops 21 and 22 indicating the state of the data buffers 13 and 14, respectively, (j) represents the output 31' of the AND gate 31 indicating whether or not the data buffers 13 and 14 cre both full, (k) represents the checking pulse 47 applied to one of the inputs of the AND gate 32 from the control circuit 50 before initiation of operation of the bubble memory for each page, and (4 represent the output 48 of the OR gate 39. The checking pulse 47 is usually generated at a period of T.

In the case of the exemplary operation illustrated in Fig. 4, operations for reading out data of four pages from the bubble memory 9 are performed continuously. It will however be noted that the output 31' of the AND gate 31 (sec (j) in Fig. 4) checked when the fifth checking pulse 47 ((k) in Fig. 4) is generated at a time instant t1, is at "H" level. In other words, at the time point t, at which operation of the bubble memory for the succeeding page (i.e. the fifth page) is to be initiated, the Q output of the flip-flop 21 indicating the state of the data buffer 13 and the Q output of the flip-flop 22 indicating the state of the data buffer 14 are both "H" (see (h) and (i) in Fig. 4), resulting in that both of the data buffers 13 and 14 are full of data.This means that the data buffer 13 is full of data of the third page with the data buffer 14 being full of data of the fourth page and that the data of the third page placed in the data buffer 13 is not yet read out by the host computer 8. In this state, the "H" output of the AND gate 31 is applied to the control circuit 50 as the output 48 ((4 in fig. 4) of the OR gate 39 through the AND gate 32 and the OR gate 39, the control circuit 50 then stops temporarily the initiation of operation of the bubble memory for the fifth page. As a result, after the time instant t1, the rotating field is turned off and the replicator pulse is inhibited, as is illustrated at (a) and (b) in Fig. 4.

At a time instant t2, the pulse signal 42 ((e) in Fig. 4) indicating that the data of the third page placed in the data buffer 13 have been fetched by the host computer 8 is outputted, resulting in that the output 31' of the AND gate 31 is "L" (see (j) in Fig. 4). When the checking pulse 47 is generated at a time instant t3, the output 48 of the OR gate 39 applied to the control circuit 50 is "L" (see (4 in Fig. 4). Accordingly, the control circuit 50 allows the temporarily stopped operation of the bubble memory for the fifth page to be regained after the time instant t3.

In this way, the magnetic bubble memory system is imparted with the function to stop temporarily the operation of the magnetic bubble memory when the data buffer is found to be in the state in which the data transfer from the magnetic bubble memory to the data buffer can not be carried out. By virtue of this function, there arises no problem even if more or less delay is involved in the reading of data from the data buffer by the host computer.

Next, explanation will be made of the case where data is written from the host computer 8 into the bubble memory 9. In this case, it is sufficient to check whether or not the data buffers 13 and 14 are both empty in order to know whether or not data transfer from the data buffer 13 or 14 to the bubble memory 9 is permissible.

Referring to Fig. 3 again, in the case of the writing operation of the bubble memory, the signal 41 is generated from the control circuit 50 upon every completion of transfer of data of one page from the data buffer 13 or 14 to the bubble memory, and the signal 42 is generated from the control circuit 50 upon every completion of data of one page from the host computer to the data buffer 13 or 14.

Flip-flops 35 and 36 are provided for indicating the states of the data buffers 13 and 14, respectively. When the 0 output of the flipflop 35 is "H", it is indicated that the data buffer 13 is empty (EMPTY A), that is, data to be written in the bubble memory 9 is not transferred into the data buffer 13 from the host computer 8. When the Q output of the flip-flop 36 is "H", it is indicated that the data buffer 14 is empty (EMPTY B). The Q outputs of the flip-flops 35 and 36 are applied to the inputs of an AND gate 37 whose output 37' indicate whether or not the data buffers 35 and 36 are both empty. The AND gate 38 receives the output of the AND gate 37, the checking signal 47 from the control circuit 50 and a write pulse WR from the control circuit 50. The output 38' of the AND gate 38 is passed through the OR gate 39 to the control circuit 50.

Fig. 5 is a timing chart for illustrating the operation of the buffer state discriminating/chekcing circuit 52 of Fig. 3 in the case where data is written in the bubble memory from the host computer. The illustration of Fig. 5 will be readily understood in light of the explanation which has been made in conjunction with Fig. 4.

Briefly speaking, the control circuit 50, when a Write Bubble command is set from the host computer 8 into the command register of the interface register file 51, generates the reset signal 46 (see (c) in Fig. 5) at a time instant to. In the exemplary operation shown in Fig. 5, operations for writing data of three pages in the bubble memory are performed continuously. But, it will be noted that the output 37' of the AND gate 37 (see (j) in Fig.

5) checked when the fourth checking pulse 47 ((k) in Fig. 5) is generated at a time instant t1, is at "H" level. In other words, at the time point t, at which operation of the bubble memory for the fourth page is to be initiated, the Q output of the flip-flop 35 indicating the state of the data buffer 13 and the Q output of the flip-flop 36 indicating the state of the data buffer 14 are both "H" (see (h) and (i) in Fig. 5), resulting in that the data buffers 13 and 14 are both empty. This means that data of the fourth page is not yet transferred to the data buffer 14 from the host computer.In this state, the "H" output of the AND gate 37 is applied to the control circuit 50 as the output 48 of the OR gate 39 ((0 in Fig. 5) through the AND gate 32 and the OR gate 39, the control circuit 50 then stops temporarily the initiation of operation of the bubble memory for the fourth page.

At a time instant t2 is outputted the pulse signal 42 ((e) in Fig. 5) indicating that data of the fourth page has been transferred from the host computer to the data buffer 14. At the same time, the output of the AND gate 37 becomes "L". Then, when the checking pulse 47 is generated at a time instant t3, the output 48 of the OR gate 39 applied to the control circuit 50 is "L" (see (0 in Fig. 5), and hence the control circuit 50 allows the temporarily stopped operation of the bubble memory for the fourth page to be initiated (see (a) and (b) in Fig. 5).

In Fig. 4 or 5, the checking pulses 47 have been shown to be generated at a constant period T. However, the checking pulses 47 may be generated frequently (i.e. at a period much shorter than T) during an interval of time when the operation of the bubble memory is stopped because of the "H" output of the OR gate 39, in order to check frequently the output of the AND gate 31 or 37 so that the temporarily stopped operation of the bubble memory can be started immediately after the output of the AND gate 31 or 37 becomes "L".

Claims (3)

1. A magnetic bubble memory system in which data buffer means including a pair of data buffers each having a capacity corresponding to one page of a magnetic bubble memory is provided between said magnetic bubble memory and a host computer so that one of said data buffers performs data transfer with said host computer when the other data buffer performs data transfer with said magnetic bubble memory, said magnetic bubble memory system comprising:: a control circuit for controlling the operation of said magnetic bubble memory, said control circuit generating a first pulse signal associated with the inputting of data of one page to said data buffer means and a second pulse signal associated with the outputting of data of one page from said data buffer means, said control circuit also generating a checking signal prior to initiation of the operation of said magnetic bubble memory for each page of data; discriminating means for receiving said first and second pulse signals from said control circuit to discriminate a first state of said data buffer means in which said data buffers are both full or both empty and a second state of said data buffer means which is other than said first state; and gate means applied with the output of said discriminating means and said checking signal from said control circuit for passing the output of said discriminating means upon application of said checking signal, the output of said gate means being connected to said control circuit so that said control circuit causes initiation of the operation of said magnetic bubble memory for each page to be stopped when the output of said discriminating means indicating said first state of said data buffer means is passed through said gate means and to be executed when the output of said discriminating means indicating said second state of said data buffer means is passed through said gate means.

2. A magnetic bubble memory system according to claim 1, wherein said first pulse signal is generated every time data corresponding to one page has been inputted in said data buffer means, and said second pulse signal is generated every time data corresponding to one page have been outputted from said buffer means.

3. A magnetic bubble memory system constructed and arranged to operate substantially as herein described with reference to and as illustrated in Figs. 2 to 5 of the accompanying drawings.