GB2144948A - Method and circuit for the TDM-transmission of binary signals - Google Patents

Abstract

A method of TDM-transmission of binary signals in which the first mark-bit of a word is always transmitted as a mark-bit with a first polarity and the word to be transmitted is tested to see whether its number of mark-bits is even or odd. If odd, the first mark-bit following the first space-bit of the word is transmitted with a first polarity and all following mark-bits of the word are transmitted alternating between second and first polarity. A circuit arrangement (Fig. 6) for carrying out the invention comprises a binary shift register (7), a parity generator (8), a clocking circuit (9), a flip-flop (10), AND gates (11, 12, 15, 18), a flip- flop (12), a NAND gate (13) and a decoder (19). <IMAGE>

Description

SPECIFICATION Method and circuit for the TDM-transmis- sion of binary signals The invention relates to a method for the TDM (Time Division Multiplex) transmission of binary signals of the kind in which the signals are transmitted via a transmission channel in succeeding timeslots using a code in which logic bits of a first kind are used as mark-bits and logic bits of a second kind are transmitted as space-bits, and wherein within a word of the information all logic bits of the first kind are transmitted as mark-bits with alternating positive and negative polarity (AM I-Code). It aiso relates to a circuit for the realisation of such a method.

Systems for the transmission of TDM binary information often use a fixed frame structure for organising the time multiplex. A frame is divided into several time slots, e.g. with 8 bits each, whereby these time slots succeed one another immediately. For transmission, these digital information elements or bits must be transformed into a line signal of special kind.

The kind of the line signal (line code) can be chosen in such a way that special features of this signal will be obtained. Such features are e.g. to avoid a DC component during a defined period, to achieve maximum energy at low frequencies compared with the bit rate, a minimum of no energy at frequencies which are higher than the bit rate, and a minimum number of signal changes independent of the information content.

Examples of such codes are: Alternate Mark Inversion (AM I), Biphase Level (Manchester), 4B3T (Ternar). The best features are displayed by the above mentioned AMI-Code. Its advantages are a simple code-forming rule and advantageous energy distribution. If this line code is used for the transmission of information via one channel in succeeding time slots and if the binary words originate in different independent terminals, the required AMI rule cannot be adhered to in some cases. The reason is that the independent terminal A cannot tell if the last bit transmitted by the other station B is a positive or a negative pulse.Therefore, it is possible that the last bit of one time slot and the first bit of the next time slot are both positive or negative pulses which may impair the quality of the transmission channel especially when this transmission channel has a high-pass or a band-pass characteristic.

To solve this problem, the following solutions are known: a) DC-less coding bit-by-bit. In this case each logic 1 is shown as a double-pulse (transition from a positive pulse to a negative pulse) or each logic 1 as well as each logic 0 are shown as double-pulses which are in antiphase. Disadvantages of this solution are the higher quantity for coding and decoding and the shifting of the power density spectrum up to higher frequencies, which causes a higher requirement of bandwidth. Compared with AMI-code the energy maximum is at the double frequency which causes difficulties especially in band-pass transmission channels which are practically used in most cases.

b) By inserting a space bit after each time slot which is not used for transmission of any information, the low frequency part of the transmitted information can be reduced substantially. The disadvantage is that for the same information-bit-rate the transmission-bitrate will increase e.g. in case of 8-bit-words, by one eighth. This will cause trouble if this equipment has to operate in synchronism with other e.g. public networks.

c) By inserting a parity bit after each time slot, which fills up the number of the logic 1 to an even number and, if it is sure that the first logic 1 of a time slot in each case is a positive pulse, then the last pulse of a time slot in each case will be a negative pulse. The disadvantage of this solution is the same as mentioned above since the transmission-bitrate must be also increased.

It is an object of the present invention to avoid the above-mentioned disadvantages of known methods and to alter the AMI-code in such a way that a decoding of the received information is ensured and that the arising low frequency spectrum parts are heavily reduced without inserting a space bit or a parity bit.

According to the invention in its broadest aspect, a method for the TDM transmission of binary signals of the kind referred to is characterised in that the first mark-bit of a word is always transmitted as a mark bit with a first polarity, that the word to be transmitted is tested to see whether its number of mark-bits is even or odd, and if the number of mark-bits is odd, the first mark-bit following the first space-bit of the word is transmitted with a first polarity and all following mark-bits of the word are transmitted alternating between second and first polarity.

With this method, no doubling of pulses and no additional pulses are necessary, so that neither the bandwidth for the transmission nor the transmission rate will be enlarged. Transmission-bit-rate and informationbit-rate are identical. The improvement aimed at is achieved by the fact, that there is always a space of one bit at the minimum between two pulses with the same polarity.

A circuit for realisation of the method according to the invention includes a serial data input channel and an input for a clock signal, a parity generator which is supplied with the data signal, and logic circuits which are supplied with the clock signal, the data signal and the output signal of the parity generator, and is characterised in that the inputs for the data signals and the clock signal are connected to a delay circuit whose delay time is not less than, and preferably the same as, the transmission time of one word of the information, that a clocking circuit which signalises the end of a word and the start of the first bit of the next word, is supplied with the clock signal and whose output signalising the end of a word is connected with the clock input of a D-flip-flop whose information input is connected with the output of he parity generator, that the output of the delay circuit, at which the delayed binary information is available in a serial mode, is connected to the input of a first AND-gate, whose other, and inverting, input is supplied with the clock signal and whose output is connected to the clock input of a JK-flip-flop and to the inverting input of a NAND-gate whose other input is connected to the output of the D-flip-flop and whose output is connected to the inputs J and K of the JKflip-flop and to the inverting input of a second AND-gate whose other input is connected to the output of the first AND-gate and the clock input of the JK-flip-flop and whose output is connected with the reset-input of the D-flipflop, and that the output of the delay circuit and the output of the JK-flip-flop (12) are connected to the inputs of a third AND-gate, whose output sends the logic bits of first kind with positive polarity, and that the output of the delay circuit and the inverted output of the JK-flip-flop are connected to the inputs of a fourth AND-gate, whose output sends the logic bits of first kind with negative polarity.

This circuit arrangement has the advantage that no special synchronising method or adjustment to the transmission rate is necessary.

A known parity generator contains a modulo-2-counter (binary scaler) which is set to zero at the beginning of the word and shows at the end of the word whether the number of logic mark bits is odd or even. In a circuit arrangement according to an embodiment of the invention, the delay circuit is a binary shift register controlled by the clock signal and whose number of steps corresponds to the number of bits of the information word and which has a serial output for sending the delayed data signal as well as parallel outputs which are connected to the parity generator. If all the bits of a word are available at the parallel outputs of the shift register a parity generator can detect the number of the mark bits without counting and if this number is odd it will initiate the altering of the code.

According to another embodiment of the invention, the clocking circuit contains a modulo-N-counter controlled by the clock signal, whereby N is the number of bits of one word of the information, with a binary carry output which is connected to the clock-input of the D-flip-flop, and with parallel data outputs, it contains further on, a decoder which is connected to the parallel data outputs of the modulo-N-counter, and whose output N = 0 is connected to the set-input of the JK-flip-flop.

Controlled by the carry signal at the end of the data word the output-signal of the parity generator is transmitted to the D-flip-flop. If the first information bit is available, the output N = 0 of the decoder sets the JK-flip-flop in the priority status, so that the first mark bit of each word will be transmitted as a mark bit with first polarity.

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows a transmission channel with a number of connected subscribers, Figure 2 a time frame consisting of time slots of a multiplex system which are adjoined to corresponding transmission channels, Figure 3 the principle of coding according to the AMI-Code, Figure 4 the effect of a disadvantageous bit combination at the transition of two succeeding timeslots and the improvement made by the invention, Figure 5 the bearing of the method according to the invention on various different bit configurations and Figure 6 an example of a circuit range.

ment according to the invention.

Fig. 1 shows a transmission channel 1, e.g.

a line, with various subscriber stations 2, 3 and 4 which send their information in their corresponding time slots cyclically. As an example, for digital telephone systems with transmission of voice signals using pulsecode modulation (PCM) with a transmission band width of 3.5 kHz and a sample rate of 8 kHz, the resolution is 8 bits. The bit with the highest order (MSB) states the polarity of the sampled voltage value of the analogue signal and the remaining 7 bits show the momentary absolute value of the voltage. In order to get a good signal-to-noise ratio the quantisation occurs nonlinearly. For TDM-transmission, 32 PCM-channels are joined to a frame, whereby 30 channels (time slot 1 . . 1 5 and 17 . . . 31) are used for voice transmission, one (time slot 0) is used for synchronisation and one (time slot 16) is used for signalling.

Such a frame is shown in simplified form in Fig. 2. Time slot TSO is already mentioned, for synchronisation. Time slots TSN, TSN + 1 and TSN + 2 may be coordinated with stations 2, 3 and 4 according to Fig. 1. Since the sample rate is 8 kHz and each sample value is shown by an 8 bit word, the data rate is 64.000 bit/s. Since the multiplex frame is repeated with a frequency of 8 kHz, the duration of the frame is 1 25 ps as shown in Fig. 2.

Fig. 3 shows the conversion of a binary information to an AMI-coded signal for the transmission path, whereby mark-bits are reproduced alternately as positive and negative pulses, whereas space-bits are reproduced by the value of OV. The bit-duration of an AMIcoded signal is designated in Fig. 3 as + B.

In the upper part of Fig. 4, there is shown the time period at the transition from time slot N to time slot N + 1, and several bits of these time slots are marked. Under the condition that bit 8 of time slot N and bit 1 of time slot N + 1 are both mark-bits, the AMI-Coded signal may take a disadvantageous shape at the transition range of both time slots, e.g. according to Fig. 4a a negative double pulse or according to Fig. 4b a positive double pulse can arise. In this manner an undesirable higher value of the low frequency spectrum is caused. It is intended that the invention will avoid this disadvantage and obtain a signal as shown in Fig. 4c.

By means of different bit sequences of complete words, Fig. 5 shows in which cases and of which kind these alternations are to be made according to the invention. In the examples according to Fig. 5a and Sb, the number of mark-bits is even in both cases and therefore no alternation is necessary. According to Fig. 5c, the word shown contains 3 mark-bits and therefore, beginning with the first mark bit which follows the first space-bit of the word, all mark bits of the word are transmitted with inverted polarity. The worst case which could occur is shown in Fig. 5d.

The word shown starts with seven mark bits and the last bit is a space bit. By means of the counting result of mark bits (number is odd) the intended correction is prepared but it cannot be realised, because the first space bit is the last bit of the word.

Therefore at the transition range between these two time slots, two pulses with the same polarity are separated solely by a space bit; but at least the case shown in Fig. 4 a.. . b will not occur.

In Fig. 6 there is shown a circuit arrangement according to the invention in which the binary information to be transmitted is entered in serial mode in bursts of N bits into the input 5. The clock pulse is supplied to input 6. By means of the positive-going edge of the clock pulse, the information is transferred to the circuit arrangement which forms a line coder. The binary information is shifted into a delay circuit in the form of a shift register 7 having N steps. After N clock edges of the bit clock, the word of the information is available in parallel mode at the outputs B1 . . . BN of the shift register 7 and can be checked for its number of mark bits by a parity generator 8.

If this number is odd, this fact is marked at the output UG of the parity generator 8. If this number is odd, this fact is marked at the output UG of the parity generator 8. The bit clock signal applied to input 6 is also applied to the clocking circuit or modulo-N-counter 9, whose output U is set by a carry-signal after counting of N clock-edges. This pulse-mode carry signal is applied to the clock input of a D-flip-flop 10 whose information input is connected to the output UG of the parity generator 8. As a result, the state of the output of the parity generator 8 is applied to the flipflop 10 whose output Q up to the reset instant indicates that the word of the information has an odd number of mark bits.

After N clock edges, the first information bit B1 appears at the serial mode output SER AUS of the shift register 7. This information bit is binary-interfaced with the bit clock pulse by means of an AND-gate 11, so that at the output of the AND-gate a clock edge appears only in the case where the information bit B1 is a mark bit. The output-signal of the ANDgate 11 causes an oscillating switching of a JK-flip-flop 1 2 if the control inputs J and K are supplied with a logic-1-level. This is the case as long as output Q of flip-flop 10 indicates that the number of marks is even or the foregoing bit has not been the first space bit of the word.The signals of the output SER-AUS of shift register 7 and of the output o of clip-flop 10 are binary-connected by a NAND-gate 1 3. As long as flip-flop 1 2 is oscillating, mark bits coming from the output SER-AUS of the shift register 7 are alternately switched through by means of AND-gates 14 and 15 to the outputs 1 6 and 1 7 of these AND-gates. The output signals of the ANDgates are suitable for the control of a generally known push-pull circuit which provides the positive and negative pulses required for the line transmission. In the case where the number of mark bits of a word is odd, the output Q of the flip-flop 10 indicates the state of logic 1 (mark).In the case where the output SER-AUS of the shift register 7 indicates space bits the output of the NAND-gate 1 3 keeps a logic 0 (space) and prepares the flip-flop 1 2 not to change its status during the next clock-edge. The next mark bit appearing at output SER-AUS of shift register 7 causes a clock edge at the output of AND-gate 11 which is sent to the clock input of flip-flop 1 2.

Because of the logic level transmitted from NAND-gate 1 3 to the inputs J and K, the flipflop 1 2 does not switch over, but generates a pulse at that one of the outputs 1 6 or 1 7 which was activated by the preceding mark bit. The flip-flop 10 is now reset by the logic levels combined by the AND-gate 1 8. As a result, at the output of the NAND-gate 1 3 the level logic 1 remains independent of the information which appears at the output SER-AUS of the shift register 7. Thus the flip-flop 1 2 is caused to switch back and forth at each coming mark bit of the information and therefore to switch through alternatively to the outputs 16 and 17.

Since the first mark bit of the line-coded data stream must always be a positive pulse the flip-flop 1 2 is set in the priority state by means of a signal generated at output N = 0 of a decoder 1 9 which is connected to the parallel outputs of the modulo-N-counter 9 namely during that time in which the first information bit of each word of a time slot is transmitted.

Claims (6)

1. Method for the TDM-transmission of binary signals of the kind in which the signals are transmitted via a transmission channel in succeeding timeslots using a code in which logic bits of a first kind are used as mark-bits and logic bits of a second kind are transmitted as space-bits, and wherein within a word of the information ail logic bits of the first kind are transmitted as mark-bits with alternating positive and negative polarity (AMI -Code), characterised in that the first mark-bit of a word is always transmitted as a mark bit with a first polarity, that the word to be transmitted is tested to see whether its number of markbits is even or odd, and if the number of mark-bits is odd, the first mark-bit following the first space-bit of the word is transmitted with a first polarity and all following mark-bits of the word are transmitted alternating between second and first polarity.

2. Circuit arrangement for realisation of the method in accordance with claim 1, including a serial data input channel and an input for a clock signal, a parity generator which is supplied with the data signal, and logic circuits which are supplied with the clock signal, the data signal and the output signal of the parity generator, characterised in that the inputs (5, 6) for the data signals and the clock signal are connected to a delay circuit (7) whose delay time is not less than, and preferably the same as, the transmission time of one word of the information, that a clocking circuit (9) which signalises the end of a word and the start of the first bit of the next word, is supplied with the clock signal and whose output signalising the end of a word is connected with the clock input of a D-flip-flop (10) whose information input is connected with the output of the parity generator (8), that the output of the delay circuit (7), at which the delayed binary information is available in a serial mode, is connected to the input of a first AND-gate (11), whose other, and inverting, input is supplied with the clock signal and whose output is connected to the clock input of a JK-flip-flop (12) and to the inverting input of a NAND-gate (13) whose other input is connected to the output of the D-flip-flop (10) and whose output is connected to the inputs J and K of the JK-flip-flop (12), and to the inverting input of a second ANDgate (18) whose other input is connected to the output of the first AND-gate (11) and the clock input of the JK-flip-flop (12) and whose output is connected with the reset-input of the D-flip-flop (10), and that the output of the delay circuit (7) and the output of the JK-flipflop (12) are connected to the inputs of a third AND-gate (14), whose output (16) sends the logic bits of first kind with positive polarity, and that the output of the delay circuit (7) and the inverted output of the JK-flip-flop (12) are connected to the inputs of a fourth ANDgate (15), whose output (17) sends the logic bits of first kind with negative polarity.

3. Circuit arrangement in accordance with claim 2, characterised in that the delay circuit is a binary shift register (7) controlled by the clock signal and whose number of steps corresponds to the number of bits of the information word and which has a serial output for sending the delayed data signal as well as parallel outputs which are connected to the parity generator (8).

4. Circuit arrangement in accordance with claim 2 or 3, characterised in that the clocking circuit contains a modulo-N-counter (9) controlled by the clock signal, whereby N is the number of bits of one word of the information, with a binary carry output which is connected to the clock-input of the D-flip-flop (10), and with parallel data outputs, that it contains, further on, a decoder (19) which is connected to the parallel data outputs of the modulo-N-counter, and whose output N = O is connected to the set-input of the JK-flip-flop (12).

5. Method for the TDM-transmission of binary signals substantially as described with reference to the accompanying drawings.

6. A circuit arrangement for the TDMtransmission of binary signals substantially as described with reference to the accompanying drawings.