GB2138606A - Digital Oscillator for Generation of Complex Signals - Google Patents

Abstract

The complex signals are in the form cos (2 pi kfM/fA)+(j) sin (2 pi kfM/fA> at a cycle frequency fA and an oscillator frequency fM. An overflowing integrator forms a signal sequence x(k)=kfM/fA) mod 1, represented in binary form by <IMAGE> from a binary coded frequency ratio fM/fA and a computer converts said signal sequence with the aid of stored sine and cosine tables into the signal sequence cos (2 pi kfM/fA)=cos[(2 pi kfM/fA) mod 2 pi ] = cos [2 pi ((kfM/fA) mod 1)] and sin (2 pi kfM/fA)=sin[(2 pi kfM/fA) mod 2 pi ] = sin [(2 pi ((kfM/fA) mod 1)] the computer comprising a first stage RWI to form, in dependence on a bit value alpha 3 applied to a control input thereof, an output value @(k) according to the instruction <IMAGE> a second stage RWII, or RWII2 to form a complex pair of sine and cosine output values from the value x(k) according to the function <IMAGE> and a third stage RWIII to form, in dependence on bit values alpha 1, alpha 2, and alpha 3 applied to control inputs thereof, a pair of output values sin (2 pi x(k)), cos (2 pi x(k)) from the output values of the second stage in accordance with a stored table.

Description

SPECIFICATION Digital Oscillator for Generation of Complex Signals The present invention relates-to a digital oscillator for generation of complex signals.

Oscillators for this purpose are known from, for example, DE-OS 30 07 907. Oscillators which deliver a complex digital sine/cosine signal are needed particularly for digital receivers operating as quadrature receivers. It is known to store the corresponding sine and cosine values in ROM tables.

However, this requires an enormous storage effort in receivers which have a large band width and high resolution.

It would therefore be desirable to provide a digital oscillator which for a great band width and high frequency resolution is more economic in storage space and computer circuits.

According to the present invention there is provided a digital oscillator for generation of complex signals in the form of cos(2#kfM/fA)+(j)sin(2#kfM/fA) at a cycle frequency fA and an oscillator frequency fM, comprising an overflowing integrator to form a signal sequence x(k)=(kfM/fA)mod 1 represented in binary form by

from a binary coded frequency ratio fM/fA, and a computer to convert said signal sequence with the aid of stored sine and cosine tables into the signal sequences cos(2#kfM/fA)=cos[(2#kfM/fA)mod2#]=cos[2#((kfM/fA)mod 1)] and sin(2#kfM/fA)=sin[(2#kfM/fA)mod2#]=sin[2#((kfM/fA)mod 1)] the computer comprising a first stage to form, in dependence on a bit value #3 applied to a control input thereof, an output value #(k) according to the instruction

a second stage to form a complex pair of sine and cosine output values from the value # (k) according to the function #n(#(k)):=[sin(2##(k)), cos(2##(k))], and a third stage to form, in dependence on bit values #1 #2 and a3 applied to control inputs thereof, a pair of output values sin(2x(k)), cos(27rx(k)) from the output values of the second stage in accordance with the following table::

#1 #2 #3 sin(2#x) cos(2#x) 0 0 0 sin(2##) cos(2##) 0 0 1 cos(2##) sin(2##) 0 1 0 cos(2##) -sin(2##) 0 1 1 sin(2##) -cos(2##) 1 0 0 -sin(2##) -cos(2##) 1 0 1 -cos(2##) -sin(2##) 1 1 0 -cos(2##) sin(2##) 1 1 1 -sin(2##) cos(2##) Embodiments of the present invention will now be more particularly described by way of example with reference to the accompanying drawings, in which:: Fig. 1 is a schematic block diagram of a digital oscillator embodying the invention; Fig. 2 is a table of functions utilised by the oscillator; Fig. 3 is a diagram of one form of a first stage of a computer of an oscillator embodying the invention; Fig. 4 is a diagram of one form of a third stage of a computer of an oscillator embodying the invention; Fig. 5 is a schematic block diagram of a first modification of an oscillator embodying the invention; and Fig. 6 is a schematic block diagram of a second modification of an oscillator embodying the invention.

Referring now to the drawings, there is shown an oscillator which shall deliver value pairs cos(2#kfM/fA), sin(2#kfM/fA) at a data rate of TA=1 00 MegaHertz to a mixer. The mixing frequency fM shall amount to 0SfM < 3t) MegaHertz and the frequency resolution to 10 Hertz.

In the embodiment illustrated in Fig. 1, the oscillator comprises a computer having three stages RWI to RWIII. The number of the bit lines is shown for all connections and the underlined values relate to a second embodiment with RWII, as described further below. The oscillator receives the value fM/fA as a binary number in the form of

transmitted from an operating part. In the illustrated embodiment, N must be equal to 24 in order to cover the resulting value range. A digital arithmetic circuit, provided by an overflowing integrator, forms the value sequence x(k)=((kfM/fA) modulo 1) from the value fM/fA. x(k) represents that part of kfM/fA which is not a whole number and 0 < x(k) < 1 applies.Calculated with the aid of the three computer stages from x(k) represented by

M being equal to 21 in this embodiment, is the value sequence sin(2x(k)), cos(2x(k)), which because of the periodicity of sine and cosine with respect to 2# already corresponds to the desired oscillator signal. The symmetrical properties of sine and cosine are utilised and the computation of sin(2x(k)), cos(2x(k)) is brought back to the value of sin(2##(k)) and cos(2(k)), wherein 0 < x (k) < 1/8. Which function in that case belongs to the individual stages of the computer is evident from the mathematical formulation of the relationships given in the following.The algorithm for the calculation of the value pair sin(2x(k)), cos(27rx(k)) can be described by t" [ (t" [ f,(x(k) mod 2-3, a3) ] , a1, a2, a3 ] , with the functions

follows the table of functions given in Fig. 2. The values 1, a2 and # correspond to the first three bits of the binary representation of

Correspondingly, the bit lines are divided up in Fig. 1 and zz, to a3 are conducted according to the given functions as control inputs to the stages RWI and RWIII, respectively.

A simple construction of the first stage RWI is illustrated in Fig. 3 and comprises a multiplexer MUX1 and a complement former (complement of 2). The multiplexer in dependence on # delivers the value x =x mod 2-3 or the complement of 2 thereof.

Fig. 4 shows a simple construction of the third stage RWIII. It comprises two multiplexers MUX2 and MUX3 and two complement formers in respective data inputs of the multiplexers. According to the table of functions of Fig. 2, the output values of sin(27rx) and cos(2x), respectively, can in dependence on a1, #2 and #3 assume the four values +sin(27), +cos(27).

These values accordingly are respectively present at the data inputs of both multiplexers, derived from the values sin(27rx) and cos(27rx) which are delivered from the second stage RWII.

In the illustrated embodiment, a table solution for the determination of sin(2##) is not provided for the second stage RWII, because a storage effort of 210k-bits would be needed for this.

Two advantageous embodiments of the invention will be described, in which the second stage can be realised with a minimum total effort.

Fig. 5 shows a first embodiment based on a series development for sine and cosine: sin(2##)=sin(2#(#-h+h))#sin(2#(#-h))+cos(2#(#-h))#2#h cos(2##)=cos(2#(#-h+h))#cos(2#(#-h))-sin(2#(#-h))#2#h The error in that case is smaller than or equal to (27rh)2 2 and can be kept sufficiently small by suitable splitting of 7 into (7-h) and h. The values of sin(2#(#-h)) and cos(2#(#-h)) are determined with the aid of two tables of sine-ROM and cosine ROM. Since xh has a substantially shorter binary representation than x, rational ROM sizes can be achieved.Apart from these tables, three multiplications, one complement formation and two additions are still required for the computation: h is multiplied by 2# in a multiplier Ml and the product of 2#h and the output value of each of the ROMs is formed in a multiplier M2 or M3, as the case may be.

Finally, the values corresponding to the afore-mentioned series development are combined in adders ADD 1 and ADD2. The "R" in the multipliers signifies that the output values are rounded off. The splitting, shown in Fig. 5, of

is optimal in the sense of a minimum total effort.

Fig. 6 shows a second embodiment based on the computation of sin(27r # # and cos(27r according to an iterative method for the conversion of polar co-ordinates (r, ) into Cartesian coordinates (x, y). In this method, z=x+jy=r cos#+jr sin# is approximated in steps through the vector zn=xn+jyn. Starting with x0=r and y0=0, the vector zn-1=xn-1+jyn-1 is turned the nth interative step through the angle #n=#arctan 2-" towards z. In which direction it is turned depends on whether the attained difference angle

between zn and z has assumed a positive or negative value.The method is convergent because ###n# arctan 2-n tends towards zero. With the initial values r=1 and =27rx, an approximation results for cos(27rx) and sin(2##=. Mathematically, the nth iterative step can be represented as following: xn+jyn=(xn-1+jyn-1)#ej#n =cos#n#[(xn-1-sign(#n)#tan##n##yn-1) +j(yn-1+sign(#n)#tan##n##xn-1)], wherein sign

Because tan ##n#=2-n, no genuine multiplications, but only shift operations are necessary for the computation of Xn and Yn. Since the number of places is fixed from the start, it can be performed by appropriate wiring. The multiplications by cosy, are already taken care of in the first iterative step.For this, too, a shift operation suffices with permissible error. According to the stated relationship, an addition or subtraction is necessary each time for the computation of Xn' y, and sign(yn) In order to keep the iterative error sufficiently small, 17 iterative steps altogether are envisaged in this embodiment.

In the embodiment according to Fig. 6, the first five iterative steps are replaced by tables SIN ROM and COS-ROM. For this, x is split up into

7-h serves as address for the sine/cosine table. The iteration thus proceeds from X5=k. cos(2#(#-h)) and Y5=k. sln(2E(#-h)).

wherein 17 k= # m=6 17 cos#m= # cos(arctan(2-m)).

m=6 These values are logically interlinked according to the above stated iteration formula in the adders (+) of the following stages. The shift operations corresponding to the multiplication by tan # are indicated by circles in Fig. 6. Taken into consideration before the shift operations is sign (#n) designated by VZ in Fig. 6. In the righthand part of Fig. 6, the value Em/2 is added each time to h, namely the value arctan 2-m + 2# arctan 2-m or 2# is added in accordance with the sign VZ attained in the preceding stage.

Claims (12)

1. A digital oscillator for generation of complex signals in the form of cos(2#kfM/fA)+(j)sin(2#kfM/fA) at a cycle frequency fA and an oscillator frequency fM, comprising an overflowing integrator to form a signal sequence x(k)=(KfM/fA) mod 1.

represented in binary form by

from a binary coded frequency ratio fM/fA, and a computer to convert said signal sequence with the aid of stored sine and cosine tables into the signal sequence cos(2#kfM/fA)=cos[(2#kfM/fA)mod2#]=cos[2#((kfM/fA)mod 1)] and sin(2#kfM/fA)=sin[(2#kfM/fA)mod2#]=sin[2#((kfM/fA)mod 1)], the computer comprising a first stage to form, in dependence on a bit value a3 applied to a control input thereof, an output value #(k) according to the instruction

a second stage to form a complex pair of sine and cosine output values from the value x(k) according to the function #n(#(k))::=[sin(2##(k)), cos(2##(k))], and a third stage to form, in dependence on bit values 1, a2, and a3 applied to control inputs thereof, a pair of output values sin(2nx(k)), cos(2#x(k)) from the output values of the second stage in accordance with the following table::

#1 #2 #3 sin(2#x) cos(2#x) 0 0 0 sin(2##) cos(2##) 0 0 1 cos(2##) sin(2##) 0 1 0 cos(2##) -sin(2##) 0 1 1 sin(2##) -cos(2##) 1 0 0 -sin(2##) -cos(2##) 1 0 1 -cos(2##) -sin(2##) 1 1 0 -cos(2##) sin(2##) 1 1 1 -sin(2##) cos(2##)

2. A digital oscillator as claimed in claim 1, wherein the first stage of the computer comprises a multiplexer with two data inputs, a data output and a control input, means being provided to apply bit values a4 to a, of the binary equation

directly to one of the data inputs and through a complement former to the other one of the data inputs.

3. A digital oscillator as claimed in either claim 1 or claim 2, wherein the third stage of the computer comprises two multiplexers each with four data inputs, one data output and three control inputs, means being provided to apply each of the values of sin(2##) # ) and cos(27r # ) from the second stage directly to a respective one of two of the data inputs of each multiplexer of that stage and through a respective complement former to a respective one of the other two data inputs of each multiplexer of that stage.

4. A digital oscillator as claimed in any one of the preceding claims, comprising means to divide the value #(k) before the second stage of the computer into a value (7-h) and a value h and to cause only the sine and cosine values for (7-h) to be stored in tables in the computer, the second stage being arranged to calculate said output values thereof in accordance with the instruction sin(2##)#sin(2#(#-h))+cos(2#(#-h))#2#h cos(2##)#cos(2#(#-h))-sin(2#(#-h))#2#h.

5. A digital oscillator as claimed in claim 4, comprising sine table storage means and cosine table storage means to each receive the value (7-h) and to deliver the values sin(2#(#-h)) and cos(2(7-h)) respectively, a first multiplier to multiply the value h by 27r, a second and a third multiplier to multiply the product of such multiplication by the value sin(2#(#-h)) and by the value cos(2#(#-h)) respectively, a first adder to add the product of the multiplication by the third multiplier to the value sin(2#(#-h)), and a second adder to add the product of the multiplication by the second multiplier, after complement formation of such product, to the value cos(2(7-h)).

6. A digital oscillator as claimed in claim 1, wherein the second stage is arranged to calculate the values [ sin(27), ), cos(27r # ) by an iterative operation for the recalculation of polar co-ordinates (r, ) into Cartesian co-ordinates (x=r cosy, y=r sin(,), wherein r=1 and =2x.

7. A digital oscillator as claimed in claim 6, wherein the second stage is operable in such a manner that, starting from x0=1 and yO=O, the vector zn-1=xn-1+jyn-1 is turned during the nth iterative step through the angle #n=#arctan 2-n towards the vector z=cos(2##)+jsin(2##), the direction of rotation being chosen in dependence on the sign of the difference angle

8.A digital oscillator as claimed in claim 7, comprising means to divide the value #(k) at input means of the second stage into the values (7-h) and h and the second stage being arranged so that the iteration takes place starting from x5=cos(2(7-h)) and y5=sin(2#(#-h)), sine table storage means and cosine table storage means being provided in the computer to store the sine and cosine values of (7-h).

9. A digital oscillator substantially as hereinbefore described with reference to Figs. 1 and 2 of the accompanying drawings.

10. A digital oscillator substantially as hereinbefore described with reference to Fig. 3 of the accompanying drawings.

11. A digital oscillator substantially as hereinbefore described with reference to Fig. 4 of the accompanying drawings.

12. A digital oscillator substantially as hereinbefore described with reference to Fig. 5 of the accompanying drawings.

1 3. A digital oscillator substantially as hereinbefore described with reference to Fig. 6 of the accompanying drawings.