GB2135123A - Multi-level metallizatien structure for semiconductor device and method of making same - Google Patents
Multi-level metallizatien structure for semiconductor device and method of making same Download PDFInfo
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- GB2135123A GB2135123A GB08402109A GB8402109A GB2135123A GB 2135123 A GB2135123 A GB 2135123A GB 08402109 A GB08402109 A GB 08402109A GB 8402109 A GB8402109 A GB 8402109A GB 2135123 A GB2135123 A GB 2135123A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title description 4
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 45
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 238000001465 metallisation Methods 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 239000011856 silicon-based particle Substances 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 abstract 4
- 229910052751 metal Inorganic materials 0.000 description 38
- 239000002184 metal Substances 0.000 description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910018125 Al-Si Inorganic materials 0.000 description 12
- 229910018520 Al—Si Inorganic materials 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Die Bonding (AREA)
Abstract
A semiconductor device (10) having a multi-level metallization structure wherein the first level (26) is of aluminium containing silicon, and the second level (34) is either aluminium or aluminium containing silicon in an amount less than that contained in the first level (26). The two levels (26, 34), where they contact each other, are sintered together, with some of the silicon from the first level (26) being diffused into the second level (34) so that the second level (34) has a region (34a), adjacent the junction between the two levels (26, 34), which has a higher content of silicon than the remaining portion of the second level (34). When making the device (10), the surface of the first level (26), where it is to be joined with the second level (34), is etched to remove some of the aluminium, but not the silicon, which roughens this surface. The second level (34) is applied on this roughened surface, and the device (10) is heated to sinter the two levels (26, 34) together and diffuse the silicon into the second level (34). <IMAGE>
Description
SPECIFICATION
Multi-level metallization structure for semiconductor device and method of making same
The present invention pertains to a multi-level metallization structure for a semiconductor device, particularly an integrated circuit, and a method of making the same. More particularly, the present invention relates to a multi-level metallization structure which uses aluminum and which provides good ohmic contact between the levels.
In the manufacture of semiconductor integrated circuits, the trend is directed toward increasing the number of components per unit area of the circuit chip in order to reduce the cost per circuit function. This increase is achieved by reducing the size of the components themselves and/or reducing the spacing between the components. However, one of the factors which limits the decrease in size and spacing is the area required by the metal interconnections used to connect the various components in a desired circuit.
One technique for overcoming the metal interconnection problem is to use multi-level metallization systems. Multi-level metallization systems include forming contact openings through the particular insulating layer, which is over the substrate of the device, to some of the components in the substrate. A first metal layer is deposited on the insulating layer and in the contact openings. The first metal layer is defined to form a portion of the overall metal interconnection system. A second layer of insulating material is applied over the defined first metal layer, and openings are formed through the second insulating layer. Some of the openings can go completely through the insulating layers to some of the components in the substrate, and some of the openings merely go through the second insulating layer to the defined first metal layer.A second metal layer is deposited on the second insulating layer and in the contact openings, and is defined to form the remaining portion of the overall interconnection system. Thus, the defined second metal layer is connected to some of the components in the substrate and to the defined first metal layer. Additional metal layers may be used if the circuit is sufficiently complex to require them.
A metal commonly used for the metallization in an integrated circuit, because of its high conductivity, ease of application and relatively low cost, is aluminum or aluminum containing a small amount of silicon.
However, a problem with aluminum is that as soon as it is deposited and exposed to air, a thin layer of aluminum oxide is formed on the surface of the aluminum. Although this aluminum oxide is not a major problem when using aluminum as a single level of metallization, it is a problem for multi-level metallization.
The oxide layer provides an insulating layer between the two metallization layers which creates a high resistance where the two layers contact each other. An attempt to minimize the high contact resistance by increasing the contact area has been made by making the area of the openings in the insulating layer between the metallization layers larger than the line width of the defined metallization layer. Heating the device to about 4000C to break up the aluminum oxide and sinter the two layrs together further reduces the resistance. However, it has been found that this does not completely remove the oxide so that the contact resistance is still higher than if no oxide is present. Furthermore, overetching the dielectric to form the oversize contact opening causes undercutting of the dielectric.Undercut edges cause poor step coverage in subsequently deposited layers.
A A semiconductor device includes a substrate of semiconductor material having a first layer of insulating material on a surface thereof and a first conductive layer on the first insulating layer. A second layer of an insulating material is on the first conductive layer and has an opening therethrough to the first conductive layer. A second conductive layer is on the second insulating layer and extends through the opening therein and contacts the first conductive layer. The first conductive layer is of aluminum containing silicon and the second conductive layer is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer. In making the semiconductor device, the first conductive layer is applied over the first insulating layer, and the second insulating layer is applied over the first conductive layer.The opening is formed through the second insulating layer, and the exposed portion of the first conductive layer is etched with an etchant which removes the aluminum at the exposed surface but leaves exposed the precipitated silicon particles contained in the aluminum-silicon conductive layer. The second conductive layer is then applied, and the device is heated to anneal the second conductive layer to the first conductive layer at their interface in the opening in the second insulating layer.
In the drawing:
Figure 1 is a cross-sectional view of a semiconductor device which incorporates the present invention.
Figures 2 through 5 are cross-sectional views illustrating the various steps of the method of the present invention for making the semiconductor device shown in Figure 1.
Figure 1 shows a semiconductor device, generally designated as 10, which includes the present invention.
The semiconductor device 10 includes a substrate 12 of a single-crystalline semiconductor material, such as silicon, having a major surface 14. Within the substrate 12 and along the surface 14 are various active and passive devices, such as transistors, diodes and resistors, which are to be electrically connected in a desired circuit arrangement. Illustrative of such devices are regions 16 and 18 which may be of different conductivity types from that of the substrate 12 or of the same conductivity type but different resistivity. On the surface 14 of the substrate 12 is a first layer 20 of an insulating material, such as silicon dioxide. The first insulating layer 20 has a pair of openings 22 and 24 therethrough to the regions 16 and 18, respectively. A first conductive layer 26 is on a portion of the first insulating layer 20 and extends into the opening 22 to contact the region 16.The first conductive layer 26 is of aluminum containing silicon, preferably up to about 3 percent of silicon.
A second insulating layer 28 extends over the first conductive layer 26 and the portion of the first insulating layer 20 not covered by the first conductive layer 26. The second insulating layer 28 may be of an inorganic material, such as silicon dioxide or silicon nitride, or an organic material, such as a polyimid. The second insulating layer 28 has two openings 30 and 32 therethrough. The opening 30 extends to the first conductive layer 26, and the opening 32 is in alignment with the opening 24 in the first insulating layer 20 which extends to the region 18. A second conductive layer 34 is over a portion of the second insulating layer 28 and extends into the opening 30 to contact the first conductive layer 26 and through the aligned openings 32 and 24to contact the region 18.The second conductive layer 34 is either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer 26. The conductive layers 25 and 34 are defined to form interconnecting strips to electrically connect the various devices in the substrate 12, such as the regions 16 and 18, together and to termination pads for the semiconductor device 10. As will be explained in detail hereinafter, the second conductive layer 34 has a sintered interface with the first conductive layer 26 and has a region adjacent the interface which contains an amount of silicon greater than that which is contained in the remaining portion of the second conductive layer 34. This provides a low-resistance contact between the two conductive layers 26 and 34.
To make the semiconductor device 10 using the method of the present invention, the regions 16 and 18 are formed in the substrate 12 using standard semiconductor technology, such as by ion implantation or diffusion. The first insulating layer 20 is then formed on the surface 14. If the first insulating layer 20 is of silicon dioxide, it can be grown on the surface 14 by exposing the surface 14 to oxygen or steam at a temperature of between about 800do and 1200 C. The opening 22 is then formed in the first insulating layer 20. This can be achieved by applying a layer of a photoresist over the entire surface of the first insulating layer 20 and patterning it where the opening 22 is to be formed using standard photolithographic techniques.The exposed portion of the first insulating layer 20 is then removed using a suitable etchant, such as buffered hydrofluoric acid for silicon dioxide.
The first conductive layer 26 is then formed. This is achieved by coating a layer of the silicon-containing aluminum over the entire surface of the first insulating layer 20 and in the opening 22 using any standard deposition technique, such as evaporation in a vacuum or sputtering. A patterned layer of photoresist is formed over the portion of the silicon-containing aluminum which is to form the first conductive layer 26, using standard photolithographic techniques. The uncoated portion of the silicon-containing-aluminum layer is then removed using a suitable etching technique, such as plasma etching or wet chemical etching with said solutions such as 20 parts H3PO4to 1 part HNO3 at about 50 C. The photoresist layer is then removed.
As shown in Figure 3, the second insulating layer 28 is then coated over the first conductive layer 26 and the exposed portion of the first insulating layer 20. If the second insulating layer is of an inorganic material, such as silicon dioxide or silicon nitride, it can be applied using a standard chemical vapor deposition technique wherein the device is exposed to a gas containing the elements of the second insulating layer and heated to react the gas to deposit the particular material. If the second insulating layer 28 is of an organic material, such as a polyimid, it can be painted or spun on and then cured. The openings 30 and 32 are then formed through the second insulating layer 28 by providing a layer of photoresist over the surface of the second insulating layer 28 and patterning it where the openings 30 and 32 are to be formed using standard photolithographic techniques.The exposed portions of the second insulating layer 28 are then removed using a suitable etching technique for the particular material used for the second insulating layer 28. The opening 24 in the first insulating layer 20 can then be formed by etching the surface of the first insulating layer 20 exposed at the bottom of the opening 32 in the second insulating layer 28. If the second insulating layer 28 is of the same material as the first insulating layer 24, when the opening 32 is formed the etching technique will automatically also etch through the first insulating layer 20 to form the opening 24. However, if the second insulating layer 24 is of a material different from that of the first insulating layer 20, after the opening 32 is formed an appropriate etching technique is then used to form the opening 24.
The surface of the first conductive layer 26 exposed at the bottom of the opening 30 in the second insulating layer 28 is then subjected to an etchant which will etch aluminum, but does not etch silicon. As shown in Figure 4, this will etch away a portion of the aluminum at the exposed surface, leaving silicon particles 36 projecting from the exposed surface. Preferably, about 1000 Angstroms of the aluminum are removed from the exposed surface to achieve a roughened surface provided by the projecting silicon particles 36. Etchants which have been found suitable for this purpose include mixtures of H3PO4 and HNO3, buffered hydrofluoric acid, dilute hydrofluoric acid, and solutions of H2O, HF, and CuSO4.
The mixture containing CuSO4 has been found to work extremely well since copper is plated onto the silicon particles as they are exposed and, depending on the size and density of the silicon particles, limits the etching of the aluminum. The copper-plated surface is then immersed in HNO3 to remove the copper and to expose a surface having a high density of silicon particles. This etching step removes any aluminum oxide from the exposed surface and also provides a roughened surface.
The second conductive layer 34 is then formed by depositing a layer of aluminum or aluminum containing an amount of silicon less than that contained in the first conductive layer 26, over the entire surface of the second insulating layer 28 and in the openings 30,32 and 24. The metal layer is then defined to form the second conductive layer 34 by applying a photoresist over the metal layer and patterning the photoresist so that it covers only the portion of the metal layer which is to form the second conductive layer 34. The uncovered portion of the metal layer is then removed using a suitable etching technique.
The device 10 is then heated at a temperature of about 400 C to sinter the second conductive layer 34 to the first conductive layer 26. During sintering, the silicon particles 36 of the first conductive layer 26 are dissolved in the second conductive layer, and additional silicon will diffuse from the first conductive layer 26 into the second conductive layer 34 which contains less silicon than that contained in the first conductive layer 26. Aluminum-silicon will find areas where the silicon had previously been located at the interface between the two conductive layers. As shown in Figure 5, this provides a region 34a in the second conductive layer 34, at the interface between the second conductive layer 34 and the first conductive layer 26, which has a content of silicon greater than that contained in the remaining portion of the second conductive layer 34.This sintering of the two conductive layers 26 and 34 provides a good electrical contact between the two layers. Furthermore, the diffusion of the silicon through the interface also breaks up any oxide that was formed on the exposed aluminum, and since the top surface of the first conductive layer 26 contains a high density of silicon particles, the area of aluminum exposed to oxidation is reduced considerably. All of these factors serve to provide a good low-resistance contact, and this low-resistance contact can be achieved with very small area contact regions.
The following Examples are given to further illustrate the present invention and are not to be taken in any way as restricting the invention beyond the scope of the appended claims
Example 1
A group of test pattern devices were made with each device being made by first growing a layer of silicon dioxide on a surface of a single-crystalline-silicon substrate by heating the substrate in steam at a temperature of about 11 00#C. A first metal layer was coated on the silicon dioxide layer by sputtering. The first metal layer was then defined to form forty-five (45) islands of the metal, each island being 32 micrometers by 70 micrometers in size. A layer of silica glass containing 3 percent by weight of phosphorous was deposited over the substrate and the first metal island by a chemical vapor deposition process at atmospheric pressure.Ninety (90) openings, each measuring about 10 micrometers by 10 micrometers, were etched through the phosphorous-silica glass to the first metal island using buffered hydrofluoric acid.
The openings were arranged so that there were two openings to each metal island, with the openings being uniformly spaced across the islands as well as uniformly spaced from island to island. The etching of the openings was carried out long enough to etch the surface of the first metal islands at the bottom of each opening. A second metal layer was then deposited by sputtering over the glass layer and in the openings to contact the first islands. The second metal layer was defined to form a plurality of islands, each 32 micrometers by 70 micrometers in size, with each island extending from an opening to one of the first islands to an opening to an adjacent first island. Thus, the second islands electrically connected the first islands in series, which included the contacts between the second islands and the first islands.The devices were then heated at 4500C for 4 hours to anneal the second islands to the first islands.
All of the devices made used aluminum as the second metal layer to form the second islands. In some of the devices, the second metal layer of aluminum was one micrometer in thickness, and in other devices the second metal layer of aluminum was two micrometers in thickness. In some of the devices, the first metal layer was aluminum. In other devices, the first metal layer was aluminum containing 1 percent of silicon, and in some of the devices the first metal layer was aluminum containing 2 percent of silicon.
For each device, the resistance of the series-connected islands was measured. The measured resistance was divided by 90, the number of contacts between the first and second islands, to determine the average contact resistance at each interface between the first and second islands plus the resistance of the metal line between the contact points. Table 1 shows the average resistance for each of the devices.
TABLE 1
Metal Resistance
(First layer/second layer) (ohms) Al/Al Too high to measure Al-Si (1%)/AI(1W) . 177 Al-Si (1%)/AI(2p) . 136
Al-Si (2%)/Al(1ii) . 168
Al-Si (2%)/AI (2A) .0875
Example Il A A group of test pattern devices was made in the same manner as described in Example 1 except that the openings through the phosphorous-silica glass were about 15 micrometers by 15 micrometers in size. Table 2 shows the average resistance for each of the devices.
TABLE 2
Metal Resistance
(First layer/second layer) (ohms) Al/Al .153 Al-Si (1%)/Al (1# .113 Al-Si (1%)/Al (2W) .092
Al-Si (2%)/AI (liy) .1
Al-Si (2%)/AI (2#) .061
Example Ill A group of test pattern devices was made in the same manner as described in Example I except that the openings through the phosphorous silica glass were about 20 micrometers by 20 micrometers in size. Table 3 shows the average resistance for each of the devices.
TABLE 3
Metal Resistance
(First layer/second layer) (ohms) Al/Al .128 Al-Si (1%)/AI (1W) .1 Al-Si (1%)/Al (2cm) .073 Al-Si (2%)/AI (1 > ) .091 Al-Si (2%)/Al (2at) .053
From the above Tables, it can be seen that those devices which used silicon-containing aluminum as the first metal had lower contact resistance than the devices in which both metal layers were aluminum. Also, the higher the silicon content of the first metal layer, the lower the contact resistance. In addition, the thicker the second aluminum layer the lower the contact resistance.
Claims (9)
1. A semiconductor device comprising:
a substrate of semiconductor material having a first layer of insulating material disposed on a surface thereof,
a first conductive layer disposed on the insulating layer,
a second layer of an insulating material disposed on the first conductive layer, said second insulating layer having an opening therethrough to the first conductive layer, and
a second conductive layer disposed on the second insulating layer and extending through said opening and contacting the first conductive layer, wherein
said first conductive layer being aluminum containing silicon and said second conductive layer being either aluminum or aluminum containing silicon in an amount less than that contained in the first conductive layer.
2. A semiconductor device in accordance with Claim 1 wherein said first conductive layer contains up to 3 percent of silicon, and wherein the second conductive layer contains in its region adjacent the interface with the first conductive layer an amount of silicon greater than that contained in the remaining portion of the second conductive layer.
3. A semiconductor device in accordance with Claim 2 wherein the first conductive layer and the second conductive layer are sintered together at their interface.
4. A method of forming a multi-level metallization structure on a substrate comprising the steps of:
forming a first metallization layer of aluminum containing silicon over a surface of a substrate,
forming a layer of an insulating material over the first metallization layer,
forming an opening through the insulating layer to the first metallization layer,
forming a second metallization layer of either aluminum or aluminum containing silicon in an amount less than that contained in the first metallization layer over the insulating layer and in the opening to contact the first metallization layer, and
heating the metallization layers to sinter the two layers together at their junction within the opening in the insulating layer and to diffuse some of the silicon from the first metallization layer into the second metallization layer.
5. The method in accordance with claim 4 wherein, prior to forming the second metallization layer, the surface of the first metallization layer within the opening in the insulating layer is treated to remove some of the aluminum and expose some of the silicon particles at the surface of the first metallization layer.
6. The method in accordance with claim 5 wherin the first metallization layer is treated by subjecting it to an etchant which removes aluminum but not silicon.
7. The method in accordance with claim 4 wherein said first metallization layer contains up to 3 percent of silicon.
8. A method of forming a multi-level metallization structure substantially as described hereinbefore with reference to Figures 2 through 5 of the accompanying drawing.
9. A semiconductor device substantially as described hereinbefore with reference to Figure 1 of the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46564083A | 1983-02-10 | 1983-02-10 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8402109D0 GB8402109D0 (en) | 1984-02-29 |
| GB2135123A true GB2135123A (en) | 1984-08-22 |
| GB2135123B GB2135123B (en) | 1987-05-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08402109A Expired GB2135123B (en) | 1983-02-10 | 1984-01-26 | Multi-level metallization structure for semiconductor device and method of making same |
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| Country | Link |
|---|---|
| JP (1) | JPH0666313B2 (en) |
| KR (1) | KR910008104B1 (en) |
| CA (1) | CA1209281A (en) |
| GB (1) | GB2135123B (en) |
| IT (1) | IT1213136B (en) |
| SE (1) | SE501466C2 (en) |
| YU (1) | YU18284A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0310108A2 (en) * | 1987-10-02 | 1989-04-05 | Kabushiki Kaisha Toshiba | Interconnection structure of a semiconductor device and method of manufacturing the same |
| US5497034A (en) * | 1986-03-31 | 1996-03-05 | Hitachi, Ltd. | IC wiring connecting method and apparatus |
| USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0019883A2 (en) * | 1979-05-24 | 1980-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device comprising a bonding pad |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51112292A (en) * | 1975-03-28 | 1976-10-04 | Hitachi Ltd | Semiconductor device |
-
1984
- 1984-01-26 GB GB08402109A patent/GB2135123B/en not_active Expired
- 1984-01-31 CA CA000446407A patent/CA1209281A/en not_active Expired
- 1984-02-02 YU YU00182/84A patent/YU18284A/en unknown
- 1984-02-06 SE SE8400592A patent/SE501466C2/en unknown
- 1984-02-09 JP JP59024197A patent/JPH0666313B2/en not_active Expired - Lifetime
- 1984-02-09 IT IT8419546A patent/IT1213136B/en active
- 1984-02-10 KR KR1019840000622A patent/KR910008104B1/en active IP Right Grant
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0019883A2 (en) * | 1979-05-24 | 1980-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device comprising a bonding pad |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497034A (en) * | 1986-03-31 | 1996-03-05 | Hitachi, Ltd. | IC wiring connecting method and apparatus |
| EP0310108A2 (en) * | 1987-10-02 | 1989-04-05 | Kabushiki Kaisha Toshiba | Interconnection structure of a semiconductor device and method of manufacturing the same |
| EP0310108A3 (en) * | 1987-10-02 | 1991-02-06 | Kabushiki Kaisha Toshiba | Interconnection structure of a semiconductor device and method of manufacturing the same |
| USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
| USRE38383E1 (en) | 1993-09-15 | 2004-01-13 | Hyundai Electronics Industries Co. Ltd. | Method for forming a via plug in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59205739A (en) | 1984-11-21 |
| CA1209281A (en) | 1986-08-05 |
| IT8419546A0 (en) | 1984-02-09 |
| SE8400592L (en) | 1984-08-11 |
| KR910008104B1 (en) | 1991-10-07 |
| GB2135123B (en) | 1987-05-20 |
| IT1213136B (en) | 1989-12-14 |
| KR840008215A (en) | 1984-12-13 |
| SE8400592D0 (en) | 1984-02-06 |
| YU18284A (en) | 1987-12-31 |
| SE501466C2 (en) | 1995-02-20 |
| JPH0666313B2 (en) | 1994-08-24 |
| GB8402109D0 (en) | 1984-02-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19970126 |