GB2131748A - Silicon etch process - Google Patents
Silicon etch process Download PDFInfo
- Publication number
- GB2131748A GB2131748A GB08235658A GB8235658A GB2131748A GB 2131748 A GB2131748 A GB 2131748A GB 08235658 A GB08235658 A GB 08235658A GB 8235658 A GB8235658 A GB 8235658A GB 2131748 A GB2131748 A GB 2131748A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon
- crystal
- etch
- area
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 29
- 239000010703 silicon Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000013078 crystal Substances 0.000 claims abstract description 25
- 230000005855 radiation Effects 0.000 claims abstract description 8
- 230000004907 flux Effects 0.000 claims abstract description 5
- 239000002245 particle Substances 0.000 claims abstract description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- ONRPGGOGHKMHDT-UHFFFAOYSA-N benzene-1,2-diol;ethane-1,2-diamine Chemical compound NCCN.OC1=CC=CC=C1O ONRPGGOGHKMHDT-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 238000010894 electron beam technology Methods 0.000 abstract description 3
- 238000010884 ion-beam technique Methods 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- BDERNNFJNOPAEC-UHFFFAOYSA-N propan-1-ol Chemical compound CCCO BDERNNFJNOPAEC-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
A silicon etch process wherein an area of silicon crystal surface is passivated by radiation damage and non-planar structure produced by subsequent anisotropic etching. The surface may be passivated by exposure to an energetic particle flux - for example an ion beam from an arsenic, boron, phosphorus, silicon or hydrogen source, or an electron beam. Radiation damage may be used for pattern definition and/or as an etch stop. Ethylenediamine pyrocatechol or aqueous potassium hydroxide anisotropic etchants may be used. The radiation damage may be removed after etching by thermal annealing.
Description
SPECIFICATION
Silicon etch process
Technical Field
This invention concerns a silicon etch process, more particularly an etch process applied to silicon crystal material to produce non-planar structures ~for example mesas or grooves. In this process, an area of the silicon crystal surface is protected and the crystal is exposed to an etchant; the etchant attacks the unprotected area of the silicon surface and removes silicon material to produce a non-planar structure.
Background Art
It is common practice to use an etch resistant mask - for example one of the photoresist material -to protect areas of the silicon surface during the etch process. Great care must be taken to ensure the proper definition, alignment, and registration of this mask. The finer the degree of tolerance on structure dimensions, the more critical is the accuracy of alignment and the more difficult this task.
Anisotropic or preferential etching of different crystal planes in silicon has been exploited widely for micro-engineering of mechanical and electronic structures. (See for example:- Proc
IEEE 70,420 (1982); IEEE Trans on Electron
Devices ED.25, 1185 (1978); and UK Patent
Application No 8125375.) Conventional masking techniques employing etch resistant materials are used to define an etched surface with edges aligned to planes of lower etch rate. By suitable choice of crystal orientation and mask shape, fine geometries of grooves, holes and points can be obtained.
Etches have also been found that are selective to doping level, allowing highly doped layers to be used as etch stops to obtain depth discrimination.
(See J Electrochem Soc 129, 2051, 1982.) Hitherto, the combination of surface masking and etch stop layers have been fundamental to technologies exploiting anisotropic etchants.
Disclosure of the Invention
For crystal specimen examination, it has been common practice to decorate the specimen surface using an etchant. Damage regions of the crystal lattice are in general vulnerable to etch attack, and when a crystal specimen is exposed to an isotropic etchant the damaged regions are etched away in preference to other regions.
Damage is highlighted by etch pitting in the specimen surface. It is surprising, then, as has been found here, that quite the reverse effect is found when damaged silicon is exposed to an anisotropic etchant. Regions of crystal damage actually appear relatively resistant to anisotropic etch attack and crystal damage may thus be used to protect areas of a silicon crystal surface during etch process structure definition.
In accordance with this invention, there is provided a silicon etch process wherein an area of the plane surface of a silicon crystal is exposed to a flux of energetic particle radiation to thereby introduce crystal damage sufficient to passivate said exposed area, the edges of said area lying in planes of relatively low etch rate; and, thereafter, the silicon crystal is exposed to an anisotropic etchant to remove silicon material adjacent to the passivated area.
This process may thus be used for maskless etch, self-aligned, pattern definition. Alternatively, or in conjunction therewith, the damaged region of silicon crystal may be buried, for example by an intermediate step of epitaxial layer deposition, to serve then, as an etch stop during subsequent anisotropic etching. The invention thus facilitates a simple technology that is self-aligned and/or self limiting in the realisation of surface defined patterns as etch structures.
The radiation damage may be produced by means of an ion beam (I-Beam). For example, the said exposed area may be first delineated using a photolithographically patterned photoresist mask or other mask and exposing the crystal surface through this mask to a flux of energetic ions.
These ions may be a dopant species - for example: arsenic (As+); boron (B+); or, phosphorus or orprotons (H+), or may be of silicon itself (Si+).
Alternatively, the radiation damage may be produced by an energetic electron beam (e-Beam).
The exposed area in this case could be defined by electron beam scan control, or again by mask definition.
Suitable anisotropic etchants are solutions of ethylenediamine pyrocatechol, and of potassium hydroxide.
The above process is applicable to VMOS device fabrication. Selecting the [ 1001 plane as crystal surface, and 111 edge directions, the process may be applied to produce V-grooves and/or sloped side mesas.
The process is also applicable to UMOS device fabrication. Selecting the [ 1 10i plane as crystal surface, and 111 edge directions, the process may be applied to produce steep-walled grooves and/or vertical side mesas.
Brief Introduction of the Drawings
In the drawings accompanying this specification:~
Figure 1 is a schematic cross-section in the vertical plane of a vertical channel metal-oxidesemiconductor silicon transistor, illustrating a mesa structure produced using an anisotropic etchant;
Figure 2 is a perspective view of the mesa structure illustrated in the preceding figure; and,
Figures 3 to 6 are schematic cross-sections showing stages in the definition of this mesa structure.
Description of the Embodiments
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings.
There is shown in Figures 1 and 2 a steep walled mesa 1, a structure extending vertically from the [ 110 ] plane surface 3 of a single crystal silicon substrate 5. The upper surface of the mesa 1 has been implanted with arsenic dopant to produce the drain region 7 of the transistor. A dopant species has also been implanted in regions of the substrate 5 each side of the mesa, source implant regions 9. A gate electrode 11 is spaced from the side surfaces of the mesa 1 by a thin insulating layer 13 of oxide. Drain and source electrodes are also provided adjacent to the drain and source regions 7 and 9 (not shown). The sides of the mesa 1 are substantially vertical and the edges of the mesa 1 are aligned in the 111 crystal directions.
The initial steps in the process of fabricating this transistor are illustrated in Figures 3 to 6. In the course of this process a layer 1 5 of photoresist is spun on to the [ 110 ] plane surface of a prepared silicon crystal substrate 5 (Figure 3). The surface pattern of the mesa structure is then defined in the photoresist photographically and soluble photoresist removed, leaving a window 17 in the photoresist mask layer 15, a window having the pattern of the desired mesa surface. The silicon substrate 5 is then exposed to a flux of energetic ions from an arsenic source and the drain implant region 7 is formed (Figure 4). Ion radiation at 80 keV and dose producing a dopant ion density of 1015 ions cm~2 is found sufficient to produce adequate lattice damage to passivate the exposed surface of the silicon substrate 5.The remanent photoresist mask material 15 is then removed and the substrate exposed to an anisotropic etchant (Figure 5). The following etchants have each proved satisfactory:~
(i) Ethylenediamine pyrocatechol etchant:
500 ml Ethylenediamine
80 gm Pyrocatechol
67 ml water
3 gm pyrozine
(ii) Potassium hydroxide solution etchant.~ 250 gm potassium hydroxide
800 ml water
250 ml propan-1-ol
After a period of time the etch process is halted.
The mesa structure Figure 5 is thus obtained. Here the step height of the mesa 1 is determined by the etch time. However in preference to this, the etch may be halted by means of an etch stop incorporated at a predetermined depth beneath the silicon surface. For example, an epitaxial layer, produced by molecular beam epitaxy (MBE) or by chemical vapour deposition (CVD), of the required depth, may be grown on an implanted or ion cleaned surface. The latter treated surface serves as a buried etch stop.
The crystal damage produced during implantation is removed, and the dopant ion species are rendered electrically active, by thermal annealing following subsequent stages of the device fabrication.
Similar satisfactory results have also been obtained using boron, phosphorus, silicon and hydrogen ion sources. In these examples the ion density produced in the silicon was between 1014 and 1015 ions/cm2. Penetration was to a depth of a few thousand Angstroms.
Maskless processing has also been performed employing electron beam lithography. It has been found at 25 keV and using beam currents in excess of 50 nA that patterns can be written directly on to the silicon surface, patterns that cause passivation to anisotropic etching.
Claims (1)
- CLAIMA silicon etch process wherein an area of the plane surface of a silicon crystal is exposed to a flux of energetic particle radiation to thereby introduce crystal damage sufficient to passivate said exposed area, the edges of said area lying in planes of relatively low etch rate; and, thereafter, the silicon crystal is exposed to an anisotropic etchant to remove silicon material adjacent to the passivated area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08235658A GB2131748B (en) | 1982-12-15 | 1982-12-15 | Silicon etch process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08235658A GB2131748B (en) | 1982-12-15 | 1982-12-15 | Silicon etch process |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2131748A true GB2131748A (en) | 1984-06-27 |
GB2131748B GB2131748B (en) | 1986-05-21 |
Family
ID=10534981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08235658A Expired GB2131748B (en) | 1982-12-15 | 1982-12-15 | Silicon etch process |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2131748B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0342391A1 (en) * | 1988-05-20 | 1989-11-23 | Siemens Aktiengesellschaft | Method of producing a photo diode sensitive to blue light |
WO1998040909A2 (en) * | 1997-03-14 | 1998-09-17 | Micron Technology, Inc. | Method of forming etched structures comprising implantation steps |
WO2005067020A2 (en) * | 2003-12-30 | 2005-07-21 | Intel Corporation | A method of varying etch selectivities of a film |
WO2020187763A1 (en) * | 2019-03-19 | 2020-09-24 | Osram Opto Semiconductors Gmbh | Method for structuring a semiconductor surface and semiconductor body comprising a semiconductor surface having at least one structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1544613A (en) * | 1977-03-07 | 1979-04-25 | Ibm | Formation of extremely narrow metallic lines |
-
1982
- 1982-12-15 GB GB08235658A patent/GB2131748B/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1544613A (en) * | 1977-03-07 | 1979-04-25 | Ibm | Formation of extremely narrow metallic lines |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0342391A1 (en) * | 1988-05-20 | 1989-11-23 | Siemens Aktiengesellschaft | Method of producing a photo diode sensitive to blue light |
US4968634A (en) * | 1988-05-20 | 1990-11-06 | Siemens Aktiengesellschaft | Fabrication process for photodiodes responsive to blue light |
WO1998040909A2 (en) * | 1997-03-14 | 1998-09-17 | Micron Technology, Inc. | Method of forming etched structures comprising implantation steps |
WO1998040909A3 (en) * | 1997-03-14 | 1999-06-17 | Micron Technology Inc | Method of forming etched structures comprising implantation steps |
US6261964B1 (en) | 1997-03-14 | 2001-07-17 | Micron Technology, Inc. | Material removal method for forming a structure |
US6309975B1 (en) | 1997-03-14 | 2001-10-30 | Micron Technology, Inc. | Methods of making implanted structures |
US6461967B2 (en) | 1997-03-14 | 2002-10-08 | Micron Technology, Inc. | Material removal method for forming a structure |
US6596642B2 (en) | 1997-03-14 | 2003-07-22 | Micron Technology, Inc. | Material removal method for forming a structure |
US6596648B2 (en) | 1997-03-14 | 2003-07-22 | Micron Technology, Inc. | Material removal method for forming a structure |
US6599840B2 (en) | 1997-03-14 | 2003-07-29 | Micron Technology, Inc. | Material removal method for forming a structure |
WO2005067020A2 (en) * | 2003-12-30 | 2005-07-21 | Intel Corporation | A method of varying etch selectivities of a film |
WO2005067020A3 (en) * | 2003-12-30 | 2005-12-15 | Intel Corp | A method of varying etch selectivities of a film |
US7247578B2 (en) | 2003-12-30 | 2007-07-24 | Intel Corporation | Method of varying etch selectivities of a film |
WO2020187763A1 (en) * | 2019-03-19 | 2020-09-24 | Osram Opto Semiconductors Gmbh | Method for structuring a semiconductor surface and semiconductor body comprising a semiconductor surface having at least one structure |
Also Published As
Publication number | Publication date |
---|---|
GB2131748B (en) | 1986-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4869781A (en) | Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element | |
US4417946A (en) | Method of making mask for structuring surface areas | |
EP0146895B1 (en) | Method of manufacturing semiconductor device | |
US4488351A (en) | Method for manufacturing semiconductor device | |
EP0083783B1 (en) | Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method | |
US6329698B1 (en) | Forming a self-aligned epitaxial base bipolar transistor | |
US3936329A (en) | Integral honeycomb-like support of very thin single crystal slices | |
US4060427A (en) | Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps | |
GB2110876A (en) | Formation of submicron features in semiconductor devices | |
JPH0412615B2 (en) | ||
KR100232711B1 (en) | Manufacturing method of semiconductor device | |
US4187125A (en) | Method for manufacturing semiconductor structures by anisotropic and isotropic etching | |
US4584055A (en) | Method for manufacturing a semiconductor device | |
DE102015102225A1 (en) | Method for processing a layer and method for producing an electronic device | |
GB1592528A (en) | Field-effect transistor and a fabrication process therefor | |
EP0113405A2 (en) | Method for making semiconductor resistors | |
US4948624A (en) | Etch resistant oxide mask formed by low temperature and low energy oxygen implantation | |
GB2131748A (en) | Silicon etch process | |
JPH0133933B2 (en) | ||
Day et al. | Silicon etch process | |
US5763316A (en) | Substrate isolation process to minimize junction leakage | |
EP0111097B1 (en) | Method for making semiconductor devices having a thick field dielectric and a self-aligned channel stopper | |
JPH0396228A (en) | Ion implanting method | |
KR0179098B1 (en) | Method for forming isolation film of semiconductor device | |
JPH0661343A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20001215 |