GB2125592A - Data storage refreshing - Google Patents

Abstract

A data storage arrangement has an address generating circuit for producing a cyclic sequence of addresses indicating which areas of storage are to be refreshed. The address generating circuit comprises a shift register 17 with feedback logic 18, 19, 20, which is more economical to implement on a chip than the usual counter. The arrangement also includes a timing circuit for supplying the clock signal REFR to register 17 when a refresh operation is to be performed, and this also comprises a shift register with feedback logic. <IMAGE>

Description

SPECIFICATION Data storage refreshing This invention relates to data storage. It is known that, in certain types of storage, data is not preserved permanently but tends to decay or deteriorate over a period of time. It is therefore necessary periodically to refresh or regenerate the data.

This normally involves the use of two counters: one for counting clock pulses so as to decide when a refresh operation should be performed, and another for generating a sequence of addresses so as to select successive areas of storage for refreshing.

However, the construction of a counter generally requires a large number of AND gates. This presents problems in the design of systems using uncommitted logic array (ULA) technology, since the number of available AND gates in a ULA chip is limited.

One object of the present invention is to eliminate the need for one or both of these counters.

Summary of the invention According to one aspect of the invention, there is provided a data storage arrangement having means for periodically refreshing the data stored therein, including an address generating circuit for producing a cyclic sequence of addresses indicating which areas of storage are to be refreshed, characterised in that the address generating circuit comprises a shift register with feedback logic.

According to another aspect of the invention, there is provided a data storage arrangement having means for periodically refreshing the data stored therein, including a timing circuit for indicating when a refresh operation should be performed, characterised in that the timing circuit comprises a shift register with feedback logic.

The advantage of the invention is that, in general, a a shift register is more economical than a counter to implement on a ULA chip, in terms of the number of AND gates required.

The use of a shift register with feedback logic is well known for producing a sequence of pseudorandom numbers. However, it has not previously been suggested to use such an arrangement for the purpose of refreshing data storage.

It is generally considered that the maximum sequence length for a feedback shift register having n n stages is 2n -1; see for example U.S. Patent Specification No. 3614400. This is an inconvenient number when the shift register is used for generating addresses, since the number of locations in a data storage arrangement is usually some power of two. Thus, it is desirable to extend the sequence length by one stage from 2n - 1 to 2".

In a preferred form of the invention, the shift register for generating addresses is provided with means for inverting the feedback signal upon detection of a predetermined pattern in the register, thereby producing a pattern in the register which would otherwise be missing from the cycle.

One data storage arrangement in accordance with the invention will now be described by way of example with reference to the accompanying draw Brief description of the drawings Figure 1 is a block diagram of the data storage arrangement.

Figure2 is a circuit diagram of a refresh timer circuit for the data storage arrangement.

Figure 3 is a circuit drawing of a refresh address generator for the data storage arrangement.

Description of an embodiment of the invention Referring to Figure 1, the data storage arrangement comprises a random access memory 10 having 32 individually addressable locations. In practice, of course, the number of locations would normally be much larger.

A refresh address generator 11 produces a sequence of 5-bit addresses which cycles through all 32 possible 5-bit patterns so as to address every location of the memory. As each location is addressed, its contents are read out by a refresh circuit 12 and written back into the same location so as to restore the data to its undecayed state.

The refresh operation is performed periodically at a frequency high enough to ensure that no location is allowed to decay so far that its contents are lost.

The frequency with which the refresh operation is performed is determined by a refresh timer 13 which produces a control signal REFR at predetermined intervals. This signal causes the address generator 11 to step forward to its next state so as to produce the address of the next location to be refreshed, and activates the refresh circuit 12.

Referring to Figure 2, the refresh timer 13 comprises a 5-stage shift register 14. The outputs of the third and fifth stages of the register are combined in an equivalence gate 15 to produce a feedback signal, which is applied to the input of the first stage. A clock signal CLK causes the contents of the register to be shifted one stage to the right, the contents of the fifth stage being discarded.

Thus, for example, of the shift register contains the pattern 01101,the feedback signal is 1 since the third and fifth stages are equal, and hence at the next clock pulse the pattern will change to 10110. The feedback signal will now be 0 since the third and fifth stages are unequal, so that at the next again clock pulse the pattern will change to 01011. It can be shown that starting from the pattern 00000, the shift register will perform a cycle of 31 (i.e. 25 - 1) different patterns. All possible 5-bit patterns occur except 11111.

The contents of the five stages of the register 14 are combined in a NOR gate 16 which thus detects the all-zero state of the register and produces the output signal REFR once every 31 clock pulses.

Referring now to Figure 3, the refresh address generator comprises a 5-stage shift register 17 which is shifted one stage to the right by the REFR signal.

The outputs of the five stages of this register provide the 5-bit refresh address for the memory 10. The register has a feedback circuit for producing the input signal for the first stage.

The feedback circuit could consist of a single equivalence gate as in Figure 2, in which case the address generator would produce a sequence of 31 addresses, omitting 11111. This might be acceptable in some circumstances, but in the present example, it is required to have a sequence length of 32 addresses.

As shown in Figure 3, the feedback circuit comprises a non-equivalence (i.e. exclusive OR) gate 18 connected to the third and fifth stages of the register 17. The output of this gate is fed to one input of an equivalence gate 19, the other input of which receives the output of an AND gate 20. The inputs of the AND gate are connected to the first four stages of the register 17. The output of gate 19 provides the feedback signal.

Normally, the output of the AND gate 20 is zero. In this case, the feedback signal is 1 if the contents of the third and fifth stages are equal, and is O if they are unequal. In other words, when the output of gate 20 is zero, the feedback circuit behaves in the same way as that in Figure 2.

When the AND gate 20 detects the pattern 11110 in the register 17, it produces an output one. This causes the feedback signal to be inverted, making it equal to 1 instead of 0. Thus, at the next clock pulse, the pattern in the shift register changes to 11111. The AND gate 20 is still enabled, and so the feedback signal is again inverted, making if 0 instead of 1.

Hence, at the next again clock pulse, the pattern changes to 01111.

In summary, the feedback circuit 18,19,20 inserts the previously missing pattern 11111 between the patterns 11110 and 01111. The circuit therefore generates a sequence of 32 different addresses, containing all possible 5-bit patterns.

It will be appreciated that the addresses generated in this way are not in true numerical order as in the case of a counter. However, this does not matter for the purpose of refresh address generation: the locations can be addressed in any order, provided they are all addressed at some time in the cycle.

Claims (6)

1. A data storage arrangement having means for periodically refreshing the data stored therein, including an address generating circuit for producing a cyclic sequence of addresses indicating which areas of storage are to be refreshed, characterised in that the address generating circuit comprises a shift register with feedback logic.

2. An arrangement according to Claim 1 wherein the address generating circuit further includes means for inverting the output of the feedback logic upon detection of a predetermined pattern in the shift register, thereby producing a pattern in the register which would otherwise be missing from the cyclic sequence.

3. An arrangement according to Claim 2 wherein the means for inverting the output of the feedback logic includes an AND gate connected to all the stages of the shift register other than the last.

4. A data storage arrangement having means for periodically refreshing the data stored therein, including a timing circuit for indicating when a refresh operation should be performed, characterised in that the timing circuit comprises a shift register with feedback logic.

5. An arrangement according to any preceding Claim wherein the feedback logic comprises a logic circuit arranged to form the equivalence function of the bit values in a predetermined plurality of the stages of the shift register.

6. A data storage arrangement substantially as hereinbefore described with reference to the accom panying drawings.