GB2124414A - Majority decision ULA theta - Google Patents

Abstract

A majority decision logic circuit uses a semiconductor ULA theta , and has four triplicated channels one of which is a clock channel (channel A) while the other three (channels B, C and D) are signal channels. Each channel has triplicated, and nominally identical, inputs and in each channel the circuitry derives from the triplicated inputs a majority vote output, and these majority vote outputs are the circuit's outputs. Each channel also has a majority vote input, either the internally generated majority vote or an external majority vote, and within each channel its majority decision vote is compared with the triplicated inputs. Hence if a fault occurs, the output due to that fault also causes the faulty channel's inputs to be compared with the majority vote to identify which level within the channel is at fault. An output selection circuit enables a faulty channel's outputs to be monitored to given an indication as to which channel and which level is faulty. Alternatively all the channels can be polled so that their fault/no fault states are continuously monitored. <IMAGE>

Description

SPECIFICATION Majority decision ULA This invention relates to a majority decision logic circuit in which triplication is exploited.

According to the invention there is described a majority decision logic circuit, which includes a clock pulse input channel having triplicated inputs on which nominally identical clock pulse trains are received, a first majority decision network associated with said clock pulse inputs and which gives a majority decision output for the clock pulse trains on said inputs, a first comparator which compares the majority decision output with the individual clock pulse inputs and gives an error indication if any discrepancy is detected, a signal input channel having triplicated input on which nominally identical digital signals are received, a second majority decision network associated with said signal channel inputs and which gives a majority decision output for the digital signals on said signal channel inputs, a second comparator which compares the output of the second majority decision network with the individual signal channel inputs and gives an error indication if a discrepancy is detected, and a selection circuit responsive to an error indication produced by a said comparator to give an output indicative of the identity both of the channel on which the error was detected and the input of that channel on which the fault occurred.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which Fig. 2 fits to the right of Fig. 1, Fig. 3 fits to the right of Fig. 2, and Fig. 4 fits to the right of Fig. 3.

The invention is described as implemented by a ULA (Uncommited Logic Array) with a single clock pulse channel and three signal channels, each of these channels using triplication with majority logic techniques. The embodiment to be described is intended for use in an electronic telecommunication exchange, but clearly the invention is not so limited.

The arrangement shown has four identical input channels, one, the A channel, being for the system clock while the other three, the B, C and D channels are signal channels. Each channel has a majority decision input such as AMV for channel A and triplicated inputs such as Al, A2 and A3 for channel A. Only the circuitry of channel A is shown in detail, the other being similar in most respects.

Thus for each of the four input channels the ULA accepts four signals, which are the triplicated inputs and their majority vote. Each channel also derives its own majority vote, and compares this or the externally-supplied vote, as needed, with the triplicated inputs. If a difference is detected an output is "flagged", and a group of four inputs can then be accessed to determine which input of which channel is in error.

The operation of the signal channels B, C and D are identical, each channel having triplicated inputs, such as B1, B2, B3 and their majority vote such as BMV. The triplicated inputs and either the external or the internally derived majority vote are clocked into the comparator section by a fifth signal, the external clock, such as B EXT.CLK. If the comparator detects a fault it inhibits the clock signal, leaving the fault condition in the comparator section, which is then examisd in order to identify the fault.

The operation of channel A differs in that, since it is the system clock channel, it needs no external clock signals, since either of the majority votes (external or internally derived) can be used to perform that function. To make this channel more tolerant to timing variations, as will be seen, the majority vote output is divided by two to produce the clock signal for the various latches, and hence each triplicated input is divided by four before being offered to the comparator section.

The comparator in the A channel is different from those in the other channels in that it only responds to an error when it is repeated.

Two modes of operations are available for monitoring the output from the comparators: (a) an interrupt output flags as soon as a fault condition is detected. The channel at fault and level within that channel may then be determined by addressing an output multiplexer such that the comparator condition of each channel in turn is read out to reveal the fault.

(b) in a so-called poll-mode, the output of each channel,s comparator is examined at regular intervals.

The output addressing may be accessed in two modes, as will be seen later; (i) by fixing an input ALE, which allows output multiplexing information into the chip when in that input is in its high condition which with inputs CEL (Not Chip Enable) and RDL (Not Read) low, causes a continuous output to exist. This enables the condition of a channel identified by a two-bit code input on inputs ADO and AD1 to be indicated.

(ii) under processor control, the code applied to the inputs ADO and AD 1 just mentioned is latched into the chip by a falling edge on input ALE. The condition of the channel thus selected is then read out by driving CEL and RDL low.

After a fault condition and also on switch on, the chip is reset to its normal condition, by application of a pulse on the input CKCHEN.

We now described the various inputs and outputs and the signals which appear, or may appear thereon. In the present case, all the chip's inputs and outputs operate at TTL voltage levels. The signal inputs are at the left-hand side of Fig. 1, and the signal outputs are at the righthand side of Fig. 4.

There are four clock channel inputs, for channel A, each associated with the system clock, whose operating frequency is 4.096 MHz. However, in one version in which the basic clock frequency is 4.096 MHz, the channels B, C and D can work at any bit rate other than that of channel A, up to a maximum of 2.048 MHz. If these, A1, A2and A3 are the triplicated inputs and AMV is the input for their associated majority vote.

As mentioned above, the chip bears three signal channels, B, C and D, and these channels use the clock pulses derived via channel A. In the case of channel B, inputs B 1, B2 and B3 are the riplicated signal streams, and BMV is the associated majority vote input. Signal channels C and D are similar to channel B.

Further, the operations of the signal channels are in general similar to the operations of the clock channel.

The interrupt output INT (Fig. 4) is normally at a low level, but when a fault condition occurs, this output changes to its high level within three cycles of the clock signal on the faulty channel.

This condition is maintained until the chip is reset.

Inputs ADO and AD1 are the address inputs, which are supplied with the information needed to output the state of a desired one of channels A, B, C or D. The relevant patterns are: Channel ADO AD 1 selected 0 O A 1 0 O B 0 1 C 1 1 D The input ALE, which has already been briefly mentioned, allows output multiplex coding information, applied to the ADO and AD1 as just mentioned into the chip. This it does by enabling a set of four latches in Fig. 4 via an inverter INV-1.

One of these latches is enabled under control of the code applied to ADO and AD 1. The "on" outputs of these latches go to the inputs of the output gating units OG 1~OG4 for the four channels. Hence one of these units is enabled and connects its channel outputs to the outputs AD5 AD2 for channels A-D.

The inputs CEL (Not Chip Enable) and RDL (Not Read), control the four-bit tri-state buffer B 1-2-34, Fig. 4, via a set of gates in Fig. 1 and a further buffer inverter B5 in Fig. 4. The tri-state buffer is enabled by a low condition, so CEL and RDL are both driven low when it is required to output information.

We now consider the outputs AD2 to AD5 in more detail. They display the condition of whichever of the channels A to D is selected for read out. Of these ADS conveys the fault flag for the channel selected by the two-bit code on ADO and AD1. The outputs AD5, AD3 and AD2 convey the conditions of levels 1, 2 and 3 respectively for the selected channel. This provides a double checking arrangement. Normally under fault conditions, two of the four outputs will be at 1; if only one output is at 1, then it is likely that there is a fault at the triplicated input. However, this condition also indicates that there is a fault in the chip.

If all four outputs are at 1, in the case of channel B, C or D, then it is likely that the majority vote has failed. Note that failure of the majority vote on channel A is not detected.

The clock check enable input, CKCHEN, is normally held low, but receives a positive pulse of minimum length 100 ns, to reset the fault-holding latches after a fault condition has been investigated, or on start up if a "power on reset" on the test only input is not in use. There are four of these fault-holding latches, one of which is shown for the clock channel at FLA, Fig. 3.

In each of the signal channels this reset is effected directly from the output of the buffer B6 connected to CKCHEN. Note that the reset of FLA in the clock channel is from an AND gate AN 1 connected to the TEST input. This AND gate's second input is from a buffer B7 which itself is reset in response to the signal on the TEST pin.

The test only input pin TEST, is primarily intended for chip testing, and is used to set the circuit to a known and reset state before testing begins. It is held low during normal use. It can also be used as a "power-on reset" if external components are used to hold the input high for a minimum of 150 nS on switch on. When this inputs is onarated. it does not necessarily reset the interrupt output INT (Fig. 4), but this latter is reset by the first clock pulse for channels B, C or D, and the second clock pulse of channel A. As already noted, this reset action is via various other circuit units including B7 and AN 1.

The three triplicated signal inputs of each channel and their majority vote must be clocked into the comparator section by an external clock signal. Thus for signal channel B, the triplicated signal inputs are B1, B2 and B3 and the external majority vote input is BMV. These are gated via a set of gates similar to that shown for channel A whose output B0 and the inputs B1, B2, B3 go to the channel B comparator COMP B in Fig. 3. Here they are gated into the comparator by the application of the external clock signal to gates corresponding to GA1 and GA2 of the A channel's comparator. This external clock signals has a frequency which twice that of the signal inputs, and of a phase such that its falling edge occurs at the same time, +40 ns, that the signal changes occur.

The state of the switch input SW decides whether the circuit is using the externally supplied majority vote or the internally derived majority vote. If this input is taken low, the circuit operates from the external majority vote, and if high it operates from the internal majority vote. This it does via the buffer B8 and gates AN2 and AN3 of the A channel, and corresponding gates of the three signal channels.

The input level on this SW should not change during operation, as if it does errors can occur on the majority vote output, and flags may be incorrectly set.

We now consider the majority vote outputs AMVO, BMVO, CMVO and DMVO. The result of each internal majority vote is fed from a buffer such as B9 for the A channel to a TTL compatible output, AMVO in the case of the A channel, whether the circuit is working from the external or the internal majority vote.

We now consider in more detail the use of the CKCHEN input. After any fault on a triplicated input has been located using the outputs AD2-AD5, the circuit has to be reset. This is done by applying a high pulse to CKCHEN, which immediately resets the comparator latches for channels B, C and D, and presets channel A for resetting. This reset condition in the case of channel B is immediately applied via a connection from buffer B6 to latches in COMP B, COMP C and COMP D which corresponds to latch FLA in COMP A. To complete the reset sequence for each of the signal channels, a negative edge is required on the external clock input for each of these channels. This resets the clock inhibit latches, each of which corresponds to CIA in channel A, and also the feed to the interrupt output.This latter occurs from the outputs of the four latches such as CIA and an AND gate AN4.

To complete the reset sequence for the clock pulse channel A, further clocking of the inputs is needed until a-8 pulse is generated on the majority vote line. This resets the counters shown in the upper portion of Fig. 3, and produces a pulse which, due to an earlier pulse on CKCHEN, is regenerated to reset the comparator latches.

This sequence is needed to ensure that all of the counters are reset at a time determined by the majority vote, so that when the next positive clock edges occur it is certain that all of the counters are properly reset. The pulse which thus resets the comparator latches also resets the bistable FF1 which was preset by the CKCHEN pulse, leaving the circuit in its normal operating state.

On switch on, if the TEST pin is not being used as a power-on reset, it is necessary to apply a pulse to the CKCHEN line to ensure that the circuit is in its correct operating condition. This pulse functions as described above.

We now consider the alternative uses to which the inputs ADO and AD 1 are put. Accessing the circuit unit to determine the channel and level of any fault can be accomplished in one of two ways, dependent on whether or not the output of the circuit unit is interfaced to a microprocessor.

Where the output is interfaced to a microprocessor, it is necessary to ensure that any output can be isolated from the address bus when the chip is not being accessed. This is done by the use of CEL and RDL inputs, and when one or both are high, the chip outputs are put into their high impedance state, and have no effect on the address bus. The normal sequence is first to set the address lines AD0-ADl to identify the wanted channel, and then apply a positive pulse to the ALE line. This latches the address information into the latches L1--L4, Fig. 4. The address but can now be turned to read if CEL and RDL are both driven low. In this case the control from CEL is executed by the gates shown on L1 to L4, and the control fro RDL is executed via B5 on B1 to B4.

In the case of a "non-microprocessor" interface, it is not likely that the outputs will be required to go into their high impedance state, so CEL and RDL can be tied low. The address lines ADO and AD 1 are unlikely to be used to address any other chip, so ALE can also be tied high.

Hence the address information acts directly on the buffers B1--B4, to give the state of the required channel/level at the outputs within 200 ns.

We now consider the operation of the clock channel A. To increase circuit tolerance against system dispersion, each input, Al, A2, A3, is divided by two and by four, using the latches D1 to D6 and their associated circuitry. The clock input to the quadruple latch FLA, which is applied to the input CK thereof, is arranged to clock the latch in the centre of each -1 pulse from the counters, applied to inputs D2, D3 and D4 of FLA, which ensures that the information latched is correct and steady. The outputs from FLA are fed to three EXCLUSIVE OR gates E01-E03, one input of each of which is the majority logic path from Q1 of FLA. Thus if there are no faults, the outputs from the gates E0l-E03, which form the comparator, remain low and operation continues.

If a fault occurs on one level of the channel A, one input to FLA differs from the others, the output of one the gates E0 1 -E03 goes high.

This, via an AND gate AN6 sets the latch CIA to its high state, so that on the next clock edge, which is 1800 out of phase with the clock to FLA, the output of CIA goes low. This holds the output of GA2 high, and prevents further clocking of FLA.

Hence the fault condition is held.

The output from CJA, as well as inhibiting further clock pulse supply to FLA, is also taken via the gate AN4 to the interrupt output, to indicate that a fault condition has occurred. In view of the manner in which the clocking is effected, this indication is given within three cycles of the occurrence of the fault. As already mentioned, the three comparator outputs, plus the OR function thereof, go to the 4x4 multiplexer, B1--B4 to enable the fault level to be identified at outputs AD2-AD5.

When a fault condition has been read, the circuit can be reset to determine whether the fault was "hard" or "transient": in the latter case it will no longer be present when this reset occurs. The reset sequence is initiated, as already mentioned, by a positive pulse on CKCHEN. This sets a D-type latch FF1 in preparation for the master clear signal generated from a divide-by-eight on the majority logic line. This ensures that the reset to the counters does not occur near the clock edges, and it also means that the counters are reset each time a divided-by-eight pulse is generated. This divided-by-eight pulse sets a monostable FF2 where output resets the counters via an AND gate AN7. It also triggers another monostable B7 via a path which was enabled by the setting of FF1 from CKCHEN. The outputs of this monostable reset the fault latch FLA, via a path including AN 1.

The monostables are each produced by using a D-type latch with its output connected via inverters to its reset input. The number of inverters used in this feedback path has to be altered according to the type of array used, but in any case it is long enough to reset the D-latch. In there two examples the feedback path introduces a 40 ns delay.

The operations of the three signal channels B,C,D, which are not shown in detail in the drawings, are much the same as the operation of channel A, except that the signal inputs do not have counters, and the clocking of the fault latches (which correspond to FLA) are for each channel done by an external clock signal.

Resetting of the fault latch is also different, it being done directly from CKCHEN.

As already indicated the four outputs from each channel's fault latch, such as FL4 for channel A, are fed to a multiplex arrangement OG1--OG4 in such a way that depending on the conditions of ADO and AD 1, the outputs from one channel are fed to the tri-state output buffer, enabled by a low signal on both CEL and RDL. The multiplexer can be operated in either one of two modes: (a) by setting ALE high, the latches pass the encoded signals from ADO and AD 1 straight to the multiplexer, and the output reads the channel identified by ADO-AD 1.

(b) When processor-driven, ADO and AD1 are set according to the channel output needed, whereafter ALE is given a positive pulse to latch the encoder information to the multiplexer, the latching being arrangsd to occur on the pulse's falling edge.

General description For each of four input channels the circuit, which is implemented as an ULA, accepts four signals which for each channel are the channel's triplicated inputs and the majority vote. Each channel also derives its own majority vote and compares either this or the externally-supplied vote, as required, with the triplicated inputs. If a difference is detected an output is flagged, and a group of four inputs is then accessed to determine which input or level of which channel is in error.

The operation of signal channels B, C and D is identical. Each channel has triplicated inputs and their majority vote. The triplicated inputs and either the external or internally derived majority vote are clocked into the comparator section by a fifth signal-the external clock. Should a fault be detected by the comparator, it inhibits the clock signal, leaving the fault condition in the comparator section, which can be examined to determine the fault.

Operation of channel A differs in that, since it is the system clock channel it requires no external clock signals as either of the majority votes can be used to perform that function. To make this channel more tolerant to timing variations, the majority vote is divided by two to produce the latch locking signal and, consequently, each triplicated input must be divided by four before being offered to the comparator section.

Two modes of operation can be used to monitor the output from the comparators:~ (1) An interrupt output flags immediately a fault condition arises, the channel and level may then be determined by addressimg the output multiplexer such that the comparator condition of each channel in turn is read out to reveal the fault.

(2) In a poll mode the outputs of the channels' comparators are looked at at regular intervals.

The output addressing may also be accessed in two modes (i) By fixing ALE high and CEL and RDL low a continuous output exists, indicating the state of a channel determined by the code on ADO and ADl.

(ii) When under processor control, the code of ADO and AD 1 is latched into the chip by a falling edge of ALE and then the condition of the channel read out by driving CEL and RDL low.

After a fault condition (and also on switch on) the chip must be reset by application of a CKCHEN pulse.

Claims (4)

Claims

1. A majority decision logic circuit, which includes a clock pulse input channel having triplicated inputs on which nominally identical clock pulse trains are received, a first majority decision network associated with said clock pulse inputs and which gives a majority decision output for the clock pulse trains on said inputs, a first comparator which compares the majority decision output with the individual clock pulse inputs and gives an error indication if any discrepancy is detected, a signal input channel having triplicated inputs on which nominally identical digital signals are received, a second majority decision network associated with said signal channel inputs and which gives a majority decision output for the digital signals on said signal channel inputs, a second comparator which compares the output of the second majority decision network with the individual signal channel inputs and gives an error indication if a discrepancy is detected, and a selection circuit responsive to an error indication produced by a said comparator to give an output indicative of the identity both of the channel on which the error was detected and the input of that channel on which the fault occurred.

2. A logic circuit as claimed in claim 1, and which includes a plurality of signal channels all of which are identical with the first-mentioned signal channel.

3. A logic circuit as claimed in claim 1 or 2, and which has a set of monitoring outputs to which the clock pulse channel or one of said signal channels can be connected by a selection circuit, and means responsive to the detection of a fault to connect the channel on which the fault has been detected to the monitoring outputs so that the latter can be checked to determine which of the inputs of that channel is faulty.

4. A majority decision logic circuit, substantially as described with reference to the accompanying drawings.