GB2120422A - Digital power controller for induction motors - Google Patents

Abstract

Induction motors run at much reduced efficiency below rated load and a microprocessor based system for overcoming this problem is described. A microprocessor 14 keeps a count which varies from a preset number to zero in 60 DEG of the supply voltage waveform and each time zero is reached a selected thyristor, such as 10 or 11, is fired to supply a motor. Phase lag of current behind voltage is determined for each phase using the values of the said count when current and voltage sensors 12 and 21 sense cessation of phase current and phase voltage zero, respectively. The phase lag is compared with a desired reference value, the resultant error signal is filtered and the count adjusted in the microprocessor so that the firing time of the thyristors is varied to correct the phase lag. <IMAGE>

Description

SPECIFICATION Controller for induction motors The present invention relates to a controller for controlling the supply of power to an induction motor.

The power consumption W of a single phase induction motor is W = Vl cos , where V and I are the r.m.s. supply voltage and current drawn, and 4 is the phase lag of the current behind the voltage waveform. At rated load the phase lag and the power factor cos 0 are dependant on the motor. At well below rated load, the power consumption decreases partly because the motor draws reduced current but more importantly because the phase lag 0 increases and reduces the power factor. This reduces the efficiency of the motor because losses from resistive heating and hysteresis are not reduced in proportion to power consumption. Similar effects occur in three phase induction motors.

A controller for induction motors and some of the problems arising in producing such controllers are described in the following patent applications (inventor: P. J. Unsworth):- U.K. Applications Nos. 8129043, 8129044, European Application No. 81304441.9, Japanese Application No. 81/152830 and U.S. Application No. 305735.

According to a first aspect of the present invention there is provided a power controller for an induction motor comprising one or more switching means for connection between an alternating current electrical supply and an induction motor which is to be energised from the supply, there being one switching means for the, or each, phase of the supply, and the or each switching means becoming conductive when a trigger signal is applied to that switching means and remaining conductive until the current supply thereto ceases, current sensing means for generating first signals when the current through the, or at least one of the, switching means ceases, voltage sensing means for generating second signals representative of the phase of at least one of the supply phases, and logical means for digitally calculating, from the first and second signals, the phase lag of current behind voltage of at least one of the phases, comparing the phase lag with a digital reference value to provide a digital error value, and generating firing signals in response to the error value at times in relation to the supply waveform which tend to reduce the conduction period of the switching means when the phase lag increases and vice versa.

According to a second aspect of the present invention there is provided a power controller for an induction motor comprising one or more switching means for connection between an alternating current electrical supply and an induction motor which is to be energised from the supply, there being one switching means for the, or each, phase of the supply, and the or each switching means becoming conductive when a trigger signal is applied to that switching means and remaining conductive until the current supply thereto ceases, current sensing means for generating first signals when the current through the, or at least one of the, switching means ceases, voltage sensing means for generating second signals representative of the phase of at least one of the supply phases, and logical means adapted to generate signals representing a cyclic digital count which is changed at a constant rate until a predetermined value is reached and then reset, to generate firing signals each time the count reaches a predetermined value, to steer each firing signal to at least one of the switching means in accordance with the first and second signals, to determine the phase lag for at least one phase from the first and second signals relating to that phase, and to compare the phase lag determined with a reference value and reduce any difference by adjusting the value of the said count.

Preferably the logical means is a microprocessor and in this way one important advantage of the present invention is obtained: reduction in cost in comparison with power controllers which use a moderate number of integrated circuits and other components.

A further important advantage arises from the second aspect of the invention where the use of the said cyclic count allows an internal interrupt signal in a microprocessor to be generated when the predetermined value, preferably zero, is reached.

Preferably the cyclic count has a period equivalent to 600 of the supply voltage waveform since the 255 states of an eight-bit counter in an eight-bit microprocessor then give sufficient resolution for adjustment of the firing angle. However, the invention may be put into practice using cyclic counts having different periods, for example two cyclic counts each having a period of 1 200 of the supply waveform and having a phase relationship of 600 may be used. A logical interpretation between these counts determines which switching means is to be fired when the predetermined value in each count is reached.

The comparison between the phase lag determined and the reference value may be carried out by subtracting the reference value from the phase lag. The resulting error signal in digital form is then filtered and amplified, to provide phase compensation to stabilise the overall servo feedback loop, before being employed to modify the current value of the cyclic count so adjusting firing angle.

Since the system according to the invention is a feedback system, speed stability problems may be encountered with some induction motors. Digital filtering of the error signal carried out by the logical means very much reduces or removes this problem. Filtering equivalent to a phase lag network up to about 1 to 3 Hertz, and then phase advance from about 8 to 10 Hertz to about 100 to 1 50 Hertz, together with smoothing above about 1 50 Hertz, has been found to be suitable for most induction motors.

The voltage sensing means may comprise means for deriving a rectangular waveform from each phase of the supply, the various rectangular waveforms being in phase with the respective phase voltage.

In the first and second aspects of the present invention the current sensing means may provide a signal representative of the voltage across the, or each, switching means and the logical means may be adapted to advance the firing angle if the voltage measured indicates that the motor controlled is tending to stall or is stationary.

In the first and second aspects of the present invention, the logical means may be adapted to generate secondary firing signals at the same time as the aforementioned firing signals, each secondary firing signal being applied to that switching means which received the last aforementioned firing signal.

It will be apparent from the above and from the specific description of the invention that the invention can be applied to singie phase induction motors or induction motors having other numbers of phases than three.

Certain embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a power controller according to the present invention, Figures 2a to 20 are waveforms used in explaining the operation of the controller of Figure 1, Figure 3 is a more detailed circuit diagram of the controller of Figure 1, Figures 4a and 4b form a flow diagram of a VOLTAGE CROSSING subroutine used by the microprocessor of Figure 1, Figure 5 is a flow diagram of a SAMPLE subroutine, Figure 6 is a FIRING INTERRUPT subroutine, Figure 7 is a FIRING subroutine, Figure 8 is a FIRING ANGLE ADJUSTMENT subroutine, Figures 9a, 9b and 9c illustrate the cyclic count held by the microprocessor and the way in which it is adjusted, and Figure 10 represents the filter characteristic of the digital filter process carried out by the microprocessor on an error signal produced therein.

An overall description will first be given of the operation of one embodiment of the invention with reference to Figure 1.

Pairs of parallel connected thyristors 10 and 11 are connected in series with one phase of a three phase induction motor in any of the ways shown for triacs in Figures 3a to 3d of Application No.

8129044 and the above mentioned foreign applications. Other switching means may be used as an alternative for the thyristors; for example each thyristor pair may be replaced by a triac. A current sensing circuit 1 2 is connected across the thyristors 10 and 11 and has its output connected to a logic circuit 13 3 which is coupled to an eight-bit microprocessor 14. The voltage sensed by the circuit 12 indicates whether current is flowing through either of the thyristors 10 and 11. A firing circuit 1 5 under the control of the microprocessor by way of the logic circuit 13 is connected to fire the thyristors 1 0 and 11.

Inputs 1 6 and 1 7 for the logic circuit 1 3 are from current sensors (not shown in Figure 1) for the two other respective phases and similarly outputs 1 8 and 1 9 are respectively connected to the firing circuits (not shown in Figure 1) of the thyristors for the other phases.

A circuit 21 for sensing the line voltages relative to neutral of the three phases of the supply for the motor receives three inputs 22, one connected to each respective power supply line.

Multiconnection channels 23 and 24 allow the circuits 13 and 21 to communicate with the input and output ports of the microprocessor 1 4 and interrupt connections 20 are also used.

The basis for controlling firing of the six thyristors is a count held in a register in the microprocessor 14. This count is illustrated in Figure 2d as a ramp which varies from a negative number to zero in 60O of the supply voltage waveform. Each time the ramp is counted down to zero a firing signal is sent to one and preferably (as will be explained) two of the three pairs of thyristors. As a result currents flow, in this example, at times indicated in Figure 2f. Phase lag 0 of current behind voltage is determined for each phase from the difference between the count in the ramp register at cessation of current as determined by the current sensing circuits, such as the circuit 12, and at zero crossings in the supply waveform as determined by the circuit 21. The phase lag determined is compared with a reference phase lag in order to give a digital error signal which is digitally filtered and used to adjust the contents of the ramp register so that the timing of the ramp relative to the supply waveform is varied, varying the firing time of the thyristors.

The embodiment of Figure 1 will now be described in more detail in conjunction with Figure 3 and the flow charts of Figures 4a to 8.

The first priority for the microprocessor 1 4 is a subroutine "VOLTAGE CROSSING" (VC) shown in Figure 4a and 4b which is carried out when the supply voltage sensing circuit 21 indicates that one phase of the supply voltage crosses zero relative to neutral. In Figure 3 inverted power supply line voltages are applied to terminals 25 and thence by way of smoothing circuits 26 comprising a series resistor and a parallel capacitor to inverting Schmitt trigger circuits 27. The smoothing circuits remove most spurious transients from the supply waveform and since the parallel capacitors have one terminal connected to ground it is the line voltages relative to neutral which operate the Schmitt trigger circuits when a predetermined voltage relative to zero is reached.An exclusive OR gate 28 is connected at the output of the Schmitt trigger circuits for the phases A and B and another exclusive OR gate 29 is connected to receive as inputs the output of the gate 29 and the output from the Schmitt trigger circuit of phase C. Figures 2a, b and c illustrate the output waveforms of the Schmitt trigger circuits 27 and show rectangular waveforms A, B and C in phase with the supply voltages of phases A, B and C, respectively. When these waveforms are applied to the gates 28 and 29 the output of the gate 29 is the rectangular waveform shown in Figure 2e having transitions from high to low or vice versa every time one of the power supply line voltages crosses zero. The output of the gate 29 is passed to an exclusive OR gate 31 which has another input from the output port 24 of the microprocessor 14.The waveform applied by the microprocessor which is shown in Figure 2g, is a delayed inverted version of that shown in Figure 2e and is separated by the microprocessor to correspond to a variable INV in a way which will be described later. Thus a negative going pulse is generated at each supply phase zero crossing giving an output from the gate 31 as shown in Figure 2h.

When a voltage crossing in the supply waveform occurs, this output from the gate 31 goes low and is applied as an interrupt signal (the VC interrupt) to the microprocessor. The VOLTAGE CROSSING subroutine is then carried out commencing with an operation 33 (Figure 4a) to disable all other interrupts. Then a variable X0 is set to a count R which is the count in the ramp register at the time of the interrupt from the gate 31 (operation 34). The variable X0 and the other variables mentioned in the description are held in separate registers in the microprocessor 14 which, typically, may have over a hundred such registers for allocation.

A variable D accumulates a data value from which the phase lag and supply period may be calculated. It is set initially to the ramp count X(O) in an operation 36 when a VC interrupt occurs but is subsequently adjusted to take account of resetting of the ramp count and adjustments required for calculating the phase lag. Since the previous value of D is required later, the value of D at a VC interrupt is held by a variable DVC in an operation 35 before the operation 36 is carried out.

In order to identify the supply phase which last crossed zero, the bits of the variable ABC(O) are now set in an operation 37 by way of the input port 23 to the respective values of the waveforms A, B and C, e.g. if A and B are high and C is low ABC(O) = 110. An operation 38 sets a three-bit variable VC(O) to the exclusive OR of ABC(O) and ABC(1) where ABC(1) is the stored value of the previous ABC(O). VC(O) then indicates by its value which voltage phase last crossed zero. Examples of the values of variables for two different phase lag and firing conditions are given in Tables 2 and 3 which will be found after the description relating to Figure 10.If a precautionary test 39 indicates that VC(O) = VC(1), where VC(1) is the previous value of VC(O), it is an indication that one supply voltage has crossed zero twice in succession, that is a spurious zero crossing has occurred and the subroutine VOLTAGE CROSSING has already been carried out for this zero crossing. For this reason if the test 39 is "True" then a jump 40 to the end of the subroutine occurs.

In the normal absence of such a spurious zero crossing the signal (INV) shown in Figure 2g is inverted in an operation 41 and applied to one of the inputs of the gate 31. This clears the interrupt pulse at the output of the gate 31, giving the short pulses illustrated in Figure 2h. An operation 42 sets a firing mask variable FM(INV) to the result of an OR operation between the three digit variables VC(O) and VC(1). This mask is used in a FIRING subroutine of Figure 7 which is described later and contains information specifying the phases having the thyristors to be fired next.

Operations 43 and 44 which follow are concerned with setting a three digit variable INS which relates to the "sampie interrupt" routine for detecting cessation of current in one phase. These operations are therefore described later.

Since all actions which must be taken when the supply voltage crosses zero have now been carried out the other interrupts are restored in an operation 46 after a flag VCB is set to one in an operation 45 to indicate that the subroutine must be completed if interrupted.

Some "housekeeping" operations are then carried out in operation 48 where the variables VC(O), VC(1), VC(2) and ABC(1) are set to new values as indicated. Alternatively, the results of repetitive housekeeping operations may be permanently stored to save time in continually recalculating the same logical variables. They are then retrieved as necessary.

In order to ensure that the ramp count of Figure 2d is counted down to zero in 60O of the supply voltage (unless a phase lag correction occurs) a number N, used to reset the ramp register, needs adjustment from time to time as, for example, mains frequency varies. This correction is carried out in operations 50 and 51 where the variable AT is set to the difference between the value of DVC (the value of the ramp count at the time the last voltage interrupt occurred) minus both )((0) and N (in effect the current value ofT). Since any change in frequency is quite likely to be temporary the variable N is corrected by only a proportion k of the error in operation 51. Resetting the ramp counter by N is carried out in a FIRING INTERRUPT subroutine described below.

The busy flag set in operation 43 is now set to zero in operation 53 and then a high frequency filtering subroutine followed by a FIRING ANGLE ADJUSTMENT subroutine, which are also described below, are carried out in operations 54 and 55, bringing to an end the VOLTAGE CROSSING subroutine.

The cessation of current in any thyristor is detected by the current sensing means 12 which is shown in more detail in Figure 3. The terminals 56 and 57 are connected across the parallel thyristors 10 and 11 as shown in Figure 1 so that the voltage across the parallel thyristors is connected by way of a full wave rectifier 58 to an opto-isolator 59. An inverting Schmitt trigger circuit 61 with input connected to the output of the opto-isolator 59 is connected to an inverting OR gate 62. As explained in Application No. 8129044 and the corresponding foreign applications mentioned above, when a thyristor, connected in series with the winding of an induction motor, ceases conduction, the voltage between its anode and cathode falls by an amount which is determined by the back e.m.f. of the motor.

Thus when current ceases the voltage at the output of the opto-isolator 59 falls and this fall is sufficient to cause the Schmitt trigger circuit 61 to change state. In this way the output signal of the OR gate 62 changes from low to high when current ceases and the positive going steps in the waveform shown in Figure 2j are generated. A further input for the gate 62 is provided from the microprocessor 14 as will be described later so that shortly after the gate output goes high it reverts to low, thus clearing the sample interrupt pulse (Figure 2j) at the output of the gate 62.

The other two phases have identical circuits as illustrated in Figure 3 with inverting OR gates 63 and 64 having output waveforms illustrated in Figures 2k and 21, respectively.

The outputs of the gates 62 and 64 are also connected as inputs to an OR gate 65 which forms part of the logic 13 of Figure 1. Thus the gate 65 generates a negative going pulse, as shown in Figure 2i, each time any thyristor ceases conduction.

The output signal from the gate 65 is used as an interrupt for the microprocessor 14 to initiate the SAMPLE subroutine shown in Figure 5.

However the interrupt signal cannot be generated if all the gates 62 to 64 receive a high input from the microprocessor and, in operation, each such input is used to inhibit current sampling from one phase by applying a high input to that one of the gates 62 to 64 associated with that phase. The inhibit signals for the three phases are shown in Figures 2m, 2n and 20 and each correspond to one bit in a three-bit variable INS (Inhibit Sampling), the bits being applied to respective terminals of the output port 24 of the microprocessor. Thus in order to obtain an interrupt signal from the gate 65 one of the inhibit signals applied to the gates 62 to 64 must be removed to allow the output of that gate to go high when current in that phase ceases.This is the function of operations 43 and 44 of Figure 4a, where the existing value of INS is used in an AND operation with the inverse of VC(O) and the result is used in an OR operation with FM(INV) or VC(2) to set the appropriate bit of INS to remove the inhibit signal from one of the gates 62 to 64 shortly after a supply voltage zero crossing occurs. For example shortly after the zero crossing corresponding to the step 1 35 occurs in Figure 2a, the inhibit on current sampling in phase A is removed at a step 136 in Figure 2e.

On receipt of the interrupt from the gate 65, the other interrupts are disabled in an operation 67 and then the variable RS is set to the value of the ramp count R at the time of the sample interrupt in an operation 68.

Current in a phase always ceases within 90 of the last voltage zero crossing in that phase so it is apparent from Figures 2a to 2d that cessation of current may occur during either of two cycles of the ramp count. Operations 70 to 72 resolve this ambiguity by setting a variable CYC to zero or one. In the operation 70 a variable PI is set by carrying out the AND operation between the variables VC(2) and INS. If PI is not equal to 0 sampling has occurred in the previous voltage supply phase and the phase lag 6 is less than 600. CYC is set to zero in the operation 71 but reset to one in the operation 72 if PI is not equal toO, that is (b is between 600 and 1200.

After having received the interrupt from the gate 65, sampling is inhibited in an OR operation 73 between the current value of INS and Vac(1 + CYC), the bracketed quantity being the value of CYC plus 1 so that if CYC = 0 then it is Vac(1) which is combined in an OR operation with INS. INS then has a value which is applied to the gates 62 to 64 inhibiting further current sampling until another supply voltage zero crossing occurs.

An index K (O or 1) indicates which of two firing masks FM(O) or FM(1) is to be loaded in preparation for firing the thyristors. As is explained in the above mentioned patent applications it is necessary to generate the firing pulses in pairs: a pulse to fire the thyristor in the next phase of the sequence of supply phases, known as the primary thyristor, and a pulse to fire another of the thyristors, known as the secondary thyristor, to ensure that, if both other phases have stopped conducting, a return path exists for current from the newly fired phase. The firing mask FM(K) has three bits each corresponding to a parallel connected pair of thyristors for one phase and determines the combination of thyristors to be fired (only one from each parallel pair fires when a pulse is applied since current flow is not in the correct direction for the other thyristor).When any of these bits is a 'one' it indicates that the corresponding pair of thyristors is to fire when the FIRING subroutine is called. K is set in an operation 74 by an exclusive OR operation between CYC and FM(INV) and RTF(K) is set to one in an operation 79. An index J is then set in operations 1 50 to 1 52 to determine the next firing mask FM(J) to be used by the firing interrupt routine. In the operation 1 50 a variable RTF(K) (ready to fire) is tested for equality with one. If the test is "True" J is set toR but if "False" to K.

A flag S(BUSY) is set to one in an operation 75 to indicate that the sample routine is not completed since an operation 76 enables other interrupts and it may be necessary to revert to the SAMPLE subroutine if an interrupt occurs. A flag Zf is checked in an operation 77 to determine whether a stalling override should occur; if so a variable known as "fire on execution of the SAMPLE routine" FOS(K) is set to one. The way in which the flag Zf is set is described later.

The firing of the thyristors indicated by FM(K) may now take place if the variable FOS(K) equals one as indicated by a test 78, and a firing subroutine described below is followed. The variable FOS(K) will have been set to one if either of two exceptionai circumstances occurs: the override flag Zf is set or, as will be explained, on the last occasion when firing should have occurred the thyristor concerned was still conducting. If the test 78 is "false" the flag S(BUSY) is set to zero in an operation 80 whereupon operations 81 and 82 are carried out to calculate the phase lag and the value of the error signal. These calculations are described below.Next a low frequency filtering subroutine, a medium frequency filtering subroutine and a high frequency filtering subroutine (described below) are executed in an operation 83 and then the FIRING ANGLE ADJUSTMENT subroutine is repeated.

When the ramp count reaches zero the appropriate thyristor is fired and for this to occur an interrupt, generated within the microprocessor when the contents of the countdown register reach zero, initiates the FIRING INTERRUPT subroutine shown in Figure 6. Only an operation 84 has to be carried out without interruption and thus it is protected by an operation 85, the protection being lifted by an operation 86. In the operation 84 the count in the internal counter is set to the value of the variable N in order to allow a new cycle of countdown to begin.

To keep the ramp-data variable D up to date, N must be added to D at this stage as indicated in operation 87. If the sample routine has not been completed as indicated by a test 88 on the flag S(BUSY) then the loop 90 including the remainder of the sample routine is followed.

A test 91 is then carried out to determine whether the next thyristor which should fire is ready. If the ready to fire (RTF) variable for the firing mask FM(J) equals 0, then the SAMPLE subroutine has not been followed, that is current is still flowing in the thyristor to be fired and firing must be delayed. The "fire on sample" variable FOS(J) is set to one in an operation 92 and the FIRING subroutine will then be entered from 78 of the SAMPLING subroutine as soon as current ceases. However if RTF(J) is equal to one, as is usually so, the thyristor is ready and the FIRING subroutine of Figure 7 is carried out as indicated at 93.

In the FIRING subroutine (Figure 7) the variable FM is set to FM(J) in order to load the firing mask to the output port of the microprocessor (operation 95). Only three bits are used for firing thyristors and connections corresponding to these bits are made to the output port. As mentioned above, the thyristors are always fired simultaneously in two phases, and the two bits required are set to one in the operation 42 of Figure 4a. Firing two phases ensures that incoming and outgoing current paths are switched on.The primary and secondary thyristors fired are as shown in Table 1 below: TABLE 1 Primary parallel thyristors A B C Secondary parallel thyristors B C A (Supply sequence -A-B-C-A-) Secondary parallel thyristors C A B (Supply sequence-A-C-B-A-) A firing pulse occurs when a variable IF is set to O in an operation 96 removing an inhibit signal (which prevents firing) in the way which will now be described.

The three bits from the output port are applied to AND gates 97, 98 and 99 but a fourth bit, corresponding to the variable IF, is applied to an inverting OR gate 1 00. Two other inputs of this OR gate may be used for inhibiting firing for such purposes as emergency closedown. When IF is set to O as in operation 96 the output of the gate 100 goes high and the gates 97 to 99 are enabled.

In one phase the output of the gate 97 is connected by way of a driver ampiifier 102 to a pulse transformer 103 with secondaries connected to terminals 104 and 1 05 of the parallel connected thyristors. Similar connections are made and shown in the other phases for the output of the gates 98 and 99.

Having fired the appropriate thyristors, the ready to fire variable RTF(J) is set to zero in operation 106 to indicate firing is completed, and in an operation 107 FOS(J) is set to zero and J to5. The variable IF is then set to 1 in an operation 108 applying the inhibit to the gates 97 to 99 by way of the gate 100 so that firing cannot again take place until the FIRING subroutine is entered and operation 96 carried out. In operation 109 the HF filter routine is once more traversed for reasons given later and it is followed by an operation 110 in which the FIRING ANGLE ADJUSTMENT subroutine is carried out.

The adjustment of firing angle will now be described in more detail. As has been mentioned, this adjustment is made by changing the ramp count 140, see Figure 9a, by adding the value of a variable A at a point 141 . In Figure 9a where one cycle of the ramp count is shown, a VC interrupt occurs at the point 142 when the variable D is set to X0 (operation 52), and a firing occurs at the point 143 when the ramp count reaches zero. At this time the ramp count is reset by N (operation 84) and D is updated by the addition of N. The ramp then continues to a point 144 when another VC interrupt occurs.Figure 9b illustrates a situation in which there are no firings between the VC interrupts 142 and 144 because of the adjustment made, and thus no resetting of the ramp count register between interrupts, while Figure 9c shows two firings 143 and 145 between two VC interrupts, again because of the adjustment A.

The phase lag calculation 81 of Figure 5 calculates a variable S which is the sampled phase lag value used in the error signal calculation 82 to calculate the phase lag error variable Ej. The low, medium and high pass filtering operations 54, 83 and 109 use Ej to calculate F, the required firing angle, and then the adjustment A is made by a FIRING ANGLE ADJUSTMENT routine shown in Figure 8, which is based on F.

Dealing now with the phase lag calculation 81, the variable S is set equal to the value of the variable D minus RS (see the operation 68) which is the value of the ramp count at the time current ceases. The variable D keeps count of the time at which the voltage interrupt occurs, any adjustments in phase angle, the variable A, and any resetting of the ramp counter by the value N. Since between one voltage crossing and the next it is possible that the ramp counter may not be reset at all (Figure 9b), may be reset once (Figure 9a) or twice (Figure 9c).

Having calculated S as part of operation 81, N is added to S to compiete the operation if the variable CYC equals 1 indicating that the phase lag occurs in the interval 60 to 1200 relative to the supply waveform.

Derivation of the firing angle adjustment variable A and its use to adjust the ramp counter contents are now described with reference to Figure 8.

The error signal calculation 82 of Figure 5 comprises updating a sample error variable SE by subtracting a reference phase-lag variable SO held in one of the microprocessor registers from the current value of the variable S which indicates phase lag 0. A further error variable Ej is then calculated from the following equation E, = 2/3E + 1/3SE In this way values of SE corresponding to sampling the phase lag successively in the three phases are averaged in forming E,.

The reference phase-lag variable SO which may be set, for example, by switches, or a potential divider coupled to an analog-to-digital converter, or wired links, is set according to the characteristic of the motor controlled.

In order to ensure the stability of an induction motor controlled by the controller, the error signal requires filtering using a characteristic of a "normalised" general type shown in Figure 10 where there is a region 220 between 2 Hertz and 9 Hertz of unity gain preceded by a region 221 where gain falls to one from a value in the range 1 5 to 100. In a region 222 the gain rises to 1 5 at about 130 Hertz but this constant gain is modified at a frequency of about 1 50 Hertz (point 223) where gain starts to fall at a rate of 6 db per octave.

Therefore Ei is subjected to low, medium and high frequency filter routines. The low frequency routine corresponding to the region 121 is implemented by using equations:- YL(1)= AL * YL(O) + (1 -AL)E1 ZL = (1RL)YL(1) + E, * RL YL(O) = YL(1) where * means multiply, YL(O) and YL(1) are the current and previous values of a low frequency filtering variable, ZL represents the output of the low frequency filtering routine, AL = e~To/TL (TL being the time constant of the low-frequency routine and To being the sampling interval of one sixth of a power supply cycle), and RL is a constant which determines the change in gain over the region 221.

For the medium frequency section, the following equations are employed.

YM(1) = AM * YM(O) + -AM)ZL ZM=-(1 - RM)YM(1) + ZL YM(O)=YM(1) where YM(O) and YM(1) are the current and previous values of a medium frequency filtering variable, ZM represents the output of the medium frequency filtering routine, AM = e@to/TM (TM being the time constant of the medium frequency routine), and RM is a constant which determines the change in gain over the region 222.

The equations for the high frequency section are: YH(1)=AH * YH(O) + (1 -AH)ZM YH(O) = YH(1) when YH(O) and YH(1) are the current and previous values of a high frequency filtering variable, and AH = e-Tt/TH (TH being the time constant of the high frequency routine and #1 being one third of To since as is mentioned below the high frequency filtering routine is carried out three times as often as the other filtering routines). The slope starting at the point 223 is provided by the first of these equations.

The new value for the firing angle variable F is then calculated from.

F=G0*E1+G *YH(1) where Go and G are gain constants establishing the overall loop gain to conform with the scale of the vertical axis in Figure 10, and YH is the result of three filtering operations mentioned above carried out on E,. Note that in order to carry out the high frequency filtering subroutine sufficiently often for correct sampling in the resuiting "digital filter", this subroutine is also carried out in operation 54 of Figure 4b and operation 109 of Figure 7.

An alternative method of determining the new firing angle variable F is now given.

The three important regions of Figure 10 are (a) the region 221 -with a characteristic of integral response to an error signal, and falling with increasing frequency; (b) the region 220-of constant gain, (that is with a characteristic of gain proportional to error) and independent of frequency; and (c) the region 222 - with a characteristic of a differential response to error, with gain rising with frequency.

The required response for the regions 221, 220 and 222 may be obtained by combining integral, proportional and derivative error signals to give the firing angle. Thus

where g1'gp and gD are respective gain for the three regions. When sampled at successive 60 time intervals #o' the three terms lead to Ein#o [(Ein-Ein-1)-(Ein-1-Ein-2)] Fn-Fn-1=g1+gp (Ein -EDin-1) + YD#o, #o #o referring to sucessive sampling intervals (n-1) and n. That is: Fn-Fn-1=Ein[g1+gpgD]-Ein-1[gp+2gD]+Ein-2gD This is the required adjustment to the firing angle calculable from the successive error signals Ei.

Typically, g1=gD' and the firing angle adjustment A is A=Fn-Fn-1=k[Ein-Ein-1]+gDEin-2 where K is a gain factor equal to #F #S where #S #F is the sensitivity of motor phase lag S to variations in firing angle F at constant load. K is typically between 1/2 and 1/8.

Following the determination of a new value for F in one of the ways given above, A is set to F - F(old) (that is F, - F,~,), the present and previous values, respectively, of the firing angle variable F, in an operation 111. As a result A may be positive or negative indicating phase advance or retard of the firing angle. The ramp counter is now read in an operation 112 but before the count can be adjusted it must be determined whether adjustment will take the count outside the values 0 to 255 which can be accommodated in the eight-bit ramp counter. Thus a test 113 determines whether adjustment would make the counter contents 9 or less. If so the firing subroutine is entered in an operation 114, firing the next thyristor, and then a return is made to the beginning of the FIRING ANGLE ADJUSTMENT subroutine.If the test 113 indicates that, after adjustment, R would be greater than or equal to 0, then a test 11 5 is carried out to determine whether R plus A would be greater than 255. If not, an operation 11 6 is carried out to reset the contents R of the ramp counter to R plus A and to update the variable D by adding A, completing the FIRING ANGLE ADJUSTMENT subroutine. If the test 11 5 indicates that R plus A is greater than 255 then the maximum possible adjustment to R is made in an operation 117 by setting R equal to 255 and updating A by setting A to 255 minus R. At the same time D is updated to D plus A. Since the full correction of A has not been carried out the variable F(old) is set to its previous value plus A in an operation 11 8.

Operation 77 of the SAMPLE subroutine checks a flag Zf to determine whether an override procedure should be followed if the motor is stalling, the motor is being started, or, when the controller is used to control several motors connected in parallel, whether one of these motors is being started or has stalled. In normal running the voltage across each thyristor is low because either the thyristor is conducting or the difference between the supply voltage and the back e.m.f. generated by the motor is fairly small compared with the supply voltage. However when stalling occurs, or during starting, the back e.m.f. is low or zero and the voltage across the thyristor rises. Phase lag between voltage crossings and current ceasing may increase in these circumstances when the embodiment so far described above would tend to further delay triggering reducing the power to the motor further.This effect is also described in the above mentioned patent applications.

To overcome this problem the voltage across the thyristors is constantly monitored as follows: the current from the opto-isolator 59 is proportional to the voltage across the thyristor pair connected between terminals 56 and 57 and passes by way of a relatively high resistance-value resistor 120 and a relatively low value resistor 12lithe junction of these resistors being connected to an input of an OR gate 123. The voltage across the resistor 120 is limited by a Zener diode 124.

Normally a relatively small current flows from the opto-isolator 59 corresponding to a low voltage across one pair of the thyristors and only a low voltage is generated across the resistor 121, although the voltage across the high-value resistor 120 is sufficient to operate the gate 62 as described above.

However when the motor back e.m.f. is low the current in the resistors 120 and 121 is high although that across the resistor 120 is limited by the Zener diode 124. The voltage across the resistor 121 is then sufficient to form a "high" input for the OR gate 123 so setting the flag Zf. As may be seen from Figure 3, the other two thyristor pairs have similar circuits which also apply inputs to the OR gate 123.

Thus high voltage across any thyristor pair sets the flag ZF.

As has been mentioned in relation to Figure 5, if the flag Zf is set, then in the operation 77 the variable FOS(K) is set to 1 with the result that in the operation 78 the firing subroutine is called and the appropriate thyristor is fired immediately, not when the ramp count reaches zero. In this way firing takes place as soon as possible in each half cycle of the supply waveform and, in effect, maximum voltage is applied for starting or to combat stalling.

For some machines it may be useful to provide an initial subroutine to be run when the machine is started in which the voltage at the input to the OR gate 123, when the back e.m.f. is low, is adjusted by connecting one, or a combination, of resistors 130, 131 and 132 in parallel with the resistor 121 by the microprocessor. This subroutine runs through the possible combinations of the resistors 130 to 132 until a suitable value is found.

Alternatively, to overcome the stalling problem and for starting, one of the respective voltages between motor supply terminals and neutral may be applied directly to the input of the gate 123, when the components 124, 121 and 1 30 to 132 are omitted together with corresponding components for the other phases.

In order to give a better understanding of the operation of the embodiment of the invention specifically described, examples of the values of the variables during operation with a sampling angle of 220 lag (that is the angle at which current cessation occurs) and a firing angle of 900 after voltage crossing are given in Table 2 below.

TABLE 2 Event Phase Angle ABC(0) # VC(0) INV FM(0) FM(1) INS VC(1) VC(2) ABC(1) P1 CYC K RTF(0) RTF(1) J FM (State just before 0 ) 001 1 010 0 011 101 111 010 001 001 001 0 0 1 0 1 101 VC(A) 0 101 0 100 10 110 011 100 010 101 1 S(A) 22 111 010 0 1 1 0 F(B) 30 0 011 VC(C) 60 100 1 001 0 101 110 001 100 100 S(C) 82 111 100 0 0 1 1 F(A) 90 0 110 VC(B) 120 110 0 010 1 011 101 010 001 110 S(B) 144 111 001 0 1 1 0 F(C) 150 0 101 VC(A) 180 010 1 100 0 110 011 100 010 010 S(A) 202 111 010 0 0 1 1 F(B) 270 0 110 VC(B) 300 001 1 010 0 011 101 010 001 001 S(B) 322 111 001 0 0 1 1 F(C) 330 0 101 VC(A) 360 101 0 100 1 110 011 100 010 101 TABLE 3 Event Phase Angle ABC(0) # VC(0) INV FM(0) FM(1) INS VC(1) VC(2) ABC(1) P1 CYC K RTF(0) RTF(1) J FM (State just before 0 ) 001 1 010 0 011 101 101 010 001 001 000 1 1 0 0 1 101 VC(A) 0 101 0 100 1 110 001 100 010 101 S(B) 15 011 000 1 0 1 0 F(B) 45 0 011 VC(C) 60 100 1 001 0 101 010 001 100 100 S(A) 75 110 000 1 1 1 1 F(A) 105 0 110 VC(B) 120 110 0 010 1 011 100 010 001 110 S(C) 135 101 000 1 0 1 0 F(C) 165 0 101 VC(A) 180 010 1 100 0 110 001 100 010 010 S(B) 195 011 000 1 1 1 1 F(B) 225 0 011 VC(C) 240 011 0 001 1 101 010 001 100 011 S(A) 255 110 000 1 0 1 0 F(A) 285 0 110 VC(B) 300 001 1 010 0 011 100 010 001 001 S(C) 315 101 000 1 1 1 1 F(C) 345 0 101 VC(A) 360 101 0 100 1 110 001 100 010 101 In Table 3 the sampling angle is 750 and the firing angle is 105 after zero crossing.The left-hand column of each of Tables 2 and 3 lists a series of events, e.g. VC(A) -- voltage interrupt, phase A; S(A) sampling interrupt, phase (A); and F(B) -- firing pulse to phase B; and the other columns show phase angle and variable values. Variables not changed following an event are left blank.

Many eight-bit microprocessors such as the Z8 or TMS 7020 may be used as the microprocessor 14 and programming will be apparent from the foregoing and the manufacturer's data. Sixteen or possibly 32-bit microprocessors may alternatively be used.

It is often desirable to start an induction motor on reduced supply voltage, that is the motor is given a "soft start". With the embodiment described above an equivalent soft start can be provided by firing the thyristors at a considerable phase lag and progressively reducing the lag until the system shown in the Figures is allowed to take over. Alternatively the reference value of phase lag used in this system may be made large on start-up and progressively reduced.

While certain embodiments of the invention have been specifically described it will be realised that the invention can be put into practice in many other ways. The ramp count which initiates firing may not have a period of 600 relative to the supply waveform; in addition to other periods a different system using two such counts, held in separate registers may be used, each of which extends, for example, for 1 200, there being a phase difference of 600 between the two waveforms. Masking the output of the microprocessor in a way which is determined logically from the polarity of these two ramp counts and the voltage crossings of the supply may then be used to select the correct thyristor for firing.

Clearly firing can be at any predetermined point in the, or one of the, waveforms, not necessarily zero.

Many other forms of switching means other than thyristors may be used, for example triacs or transistor circuits designed to cease conduction when current applied falls to zero and conduct again only after the application of a firing pulse.

Claims (12)

1. A power controller for an induction motor comprising one or more switching means for connection between an alternating current electrical supply and an induction motor which is to be energised from the supply, there being one switching means for the, or each, phase of the supply, and the or each switching means becoming conductive when a trigger signal is applied to that switching means and remaining conductive until the current supply thereto ceases, current sensing means for generating first signals when the current through the, or at least one of the, switching means ceases, voltage sensing means for generating second signals representative of the phase of at least one of the supply phases, and logical means for digitally calculating, from the first and second signals, the phase lag of current behind voltage of at least one of the phases, comparing the phase lag with a digital reference value to provide a digital error value, and generating firing signals in response to the error value at times in relation to the supply waveform which tend to reduce the conduction period of the switching means when the phase lag increases and vice versa.

2. A power controller for an induction motor comprising one or more switching means for connection between an alternating current electrical supply and an induction motor which is to be energised from the supply, there being one switching means for the, or each, phase of the supply, and the or each switching means becoming conductive when a trigger signal is applied to that switching means and remaining conductive until the current supply thereto ceases, current sensing means for generating first signals when the current through the, or at least one of the, switching means ceases, voltage sensing means for generating second signals representative of the phase of at least one of the supply phases, and logical means adapted to generate signals representing a cyclic digital count which is changed at a constant rate until a predetermined value is reached and then reset, to generate firing signals each time the count reaches a predetermined value, to steer each firing signal to at least one of the switching means in accordance with the first and second signals, to determine the phase lag for at least one phase from the first and second signals relating to that phase, and to compare the phase lag determined with a reference value and reduce any difference by adjusting the value of the said count.

3. A power controller according to Claim 2 wherein, in operation, the cyclic count has a period equivalent to 600 of the supply voltage waveform.

4. A power controller according to Claim 2 wherein the logical means is arranged to determine the said phase lag by finding the difference between the value of the said count at each zero crossing of the supply voltage for at least one phase and the value of the count at the next cessation of current in that phase.

5. A power controller according to Claim 2, 3 or 4, wherein the logical means is arranged to compare the reference value and the phase lag by subtracting one from the other to form an error signal

6. A power controller according to Claim 5 wherein the logical means is arranged to so filter the error signal before it is used to adjust the said count that the overall servo feedback loop formed by the power controller and the motor is stable.

7. A power controller according to Claim 6 wherein the filtering imparts phase lag up to 1 to 3 Hertz, phase advance from a frequency in the range 8 to 10 Hertz to one in the range 100 to 1 50 Hertz, and smoothing at least above 150 Hertz.

8. A power controller according to any preceding claim wherein the current sensing means provides a signal representative of the voltage across the, or each, switching means and the logical means is adapted to advance the firing angle if the voltage measured indicates that the motor controlled is tending to stall or is stationary.

9. A power controller according to any preceding claim wherein the logical means is adapted to generate secondary firing signals at the same time as the other said firing signals, each secondary firing signal being applied to that switching means which received the last said other firing signal.

10. A power controller according to any preceding claim wherein the logical means comprises a microprocessor.

11. A power controller for an induction motor substantially as hereinbefore described with reference to Figure 1 and/or 2 of the accompanying drawings.

12. A power controller for an induction motor substantially as hereinbefore described with reference to the accompanying drawings.