GB2120045A - Circuit for interfacing a processor to a line circuit - Google Patents

Abstract

A line switch for a digital telephone switching system which uses distributed processing, has one or more switch modules, 1a, 1b, each coupled to a central office switching system via one or more PCM lines PCMA, PCMB using common channel signalling. Each module comprises groups of line circuits 11, each coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor communicates with the central office switching system and coordinates the operations within the line switch module. A second processor controls clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch. Communication between the processors is via common buses carrying TDM-PCM data and control data. A standardised interface circuit is provided which interfaces each line circuit to the third processor and also to the busing arrangement. <IMAGE>

Description

SPECIFICATION Circuitforinterfacing a processor to a line circuit This invention pertains to telephone switching systems in gerneral, and to an interface circuit for use distributed control digital telephone switching systems in particular.

The ITT 1210 is an advanced digital switching system manufactured in the United States by International Telephone and Telegraph Corporation. The ITT 1210, formerly called DSS-1, is described in a paper by C.G. Svala, "DSS-1, A Digital Local Switching System With Remote Line Switches", National Telecommunications Conference, 1977, pp. 39: 5-1 to 39:5-7. It hasthree basic elements, i.e. line switches, a switching network, and a system control. A line switch interfaces with subscribed lines and one or more PCM lines. A line switch may be co-located with the switching network or may be remote therefrom. The switching network coupled to the line switches by the PCM lines includes digital switching modules called switch groups each including a time-space-time network.The system control which includes a pair of processors with associated program and data memories, directs the operation ofthe switching network and the line switches. Communication of control information between the system control and a line switch is via a common channel superimposed on each PCM line. This common channel approach is described in our British Patent No. 1,595,739.

This invention seeks to improve the control of operation in a system such as that mentioned above.

According to the invention there is provided an interface circuitfor coupling a line circuitto a control processor and to at least one PCM bus, said interface circuit including: (a) a first set ofterminals coupled to said one PCM bus; (b) a second set of terminals coupled to said control processor and including a control terminal, a data terminal and a clockterminal; (c) a third set of terminals coupled to said line circuit and including a pair of PCM terminals coupled to the PCM signal input and output of said line circuit; (d) first means coupled to said second set of terminals for receiving command information at said data terminal and for storing said command informa tion in response to said control terminal having a predetermined state;; (e) second means coupled to said data terminal and responsive to said first means for storing control information received at said data terminal; and (f) third means responsive to said control information stored in said second meansforcoupling said PCM terminals to said first set of terminals.

Embodiments of the invention may be better understood from a reading ofthefollowing detailed description in conjunction with the drawings, in which: Fig. 1 illustrates in block diagram form a digital switching system; Fig. 2 illustrates a line switch comprising two line modules; Fig. 3 illustrates the format of PCM frames; Fig. 4 illustrates an alternate PCM frame format; Fig. 5 illustrates in a general form the distribution of PCM channels within a two line module; Fig. 6 illustrates in a general form the control communication paths; Fig. 7 illustrates the interface logic 6 of Fig. 2 in greater detail; Fig. 8 illustrates the interleaving operation ofthe RX rate converter portion of interface logic 6 of Fig. 7.

Figs. 9a, 9b and 9e iliustrate the RX rate converter 20; Fig. 9d illustrates the line switch controller7; Fig. 10a illustrates the demultiplexing operation of the TX rate converter of Fig. 7.

Fig. 10 illustratestheTX rate converter 21 of Fig. 7 in greater detail; Fig. 11 illustrates a portion of generator 16a of Fig. 7; Fig. 12 illustrates the PLLand control 18 of Fig. 7 in greater detail; Fig. 13 illustrates failure detector 1201 of Fig. 12 in detail; Fig. 14isa block diagram of PLL 1207 of Fig. 12 in detail; Fig. 15 illustrates the phase detector of Fig. 14 in detail; Fig. 16 is a state diagram; Fig. 17 is a portion of Fig. 14shown in detail; Fig. 18 isa blockdigram of a loop filter; Fig. 19 is a loopfiltercircuit; Fig. 19a is the loopfilter circuit of Fig. 14; Fig. 20 is a detailed drawing ofthe PLL 1207 of Fig.

14; Fig. 21 illustrates a portion of the buffer distributor circuit 9 of Fig . 2; Fig. 22 illustrates a portion ofthe buffer distributor circuit 9 of Fig. 2: Fig. 23 illustrates the operation ofthe circuitry of Fig.

9; Figs. 24a and 24b when arranged as shown in Fig. 24 are timing diagrams; Figs. 25a, 25b and 25cwhen arranged as shown in Fig. 25 illustrate a line group; Fig. 26 illustrates a command word format; Figs. 27a and 27b when arranged as shown in Fig. 27 illustrates the per line control interface 44 of Fig. 25 in greater detail; Fig. 28 illustratestheformat of a control word directedto the per line control interface 44; Fig. 29 illustrates the format of a control word directed to a codec; Figs. 30a and 30b when arranged as shown in Fig. 19 show the gain/balance circuit 41 in greater detail; Fig. 31 illustrates the format of a control word transmitted over buses PCMLCA, PCMLCB; Fig. 32 illustrates the control interface 33 in detail; Fig. 33 illustrates the register status during a self-test operation;; Fig. 34 illustrates an automatic gain setting feature; Fig. 35 is a general block diagram of the detailed drawing of Fig. 14; Fig. 26 is a general block diagram of another embodiment; Fig. 37 is a general block diagram of a third embodiment.

GENERAL (Figs. 1 and2) The stored program controlled switching system of Fig. lisa PCM-TDM digital switching system which includes a switching network 3 controlled by a system controller 5. A more detailed description ofthe system controller Sand the switching network 3 is provided in the aforementioned C. G. Svala reference. The system further includes "n" line switches 1 each serving a numberofsubscriber lines 2. Each line switch is coupled to the switching network3 via one or more PCM lines 4. PCM transmission between the line switches 1 and the switching network 3 takes place overthe PCM lines 4. Each PCM line 4 includes, as is well understood, a path for PCM transmission from the switching network 3 to a line switch 1 and a second path for PCM transmission from a line switch 1 to the switching network 3.Each PCM line4carriesframeorganised data or speech at any conventional rate.

Operation ofthe line switches 1 are controlled by the system controller 5. In one illustrative embodiment of the invention, a common channel signalling arrangementsuch as that taught in U.S. Patent4,125,743 issued November 14, 1978 to R. E. Steidl is utilised such that control information between the system controller 5 and the line switches 1 is transmitted over the PCM lines 4. Typical information is sent by a line switch tothe system controller 5 including the following: 1. Report of line seizures which the line switch has detected; and 2. Report of a fault detected in the line switch.

Typical commands sent bythesystem control Stoa line switch includethefollowing: 1. Requestfor assignment of a subscriber line to a channel or release of a line from a channel; 2. Requestforringingtoa line; 3. Requestfor maintenance functions to be performed; and 4. Requestfor partytestto identify the party on the line.

Fig. 2 illustrates one ofthe line switches in greater detail.

Reliability of operation and flexibility in expansion is provided by organising the circuits of each line switch in clusters or"security blocks" of circuits that function as a unit. For anysinglefault, only the group of circuits within the security block containing the fault may be lostto service. Thus, a singlefaultwill not cause a loss of service to the entire line switch. As will be evident to those skilled in the art, the various circuits in the illustrative line switch described herein may be organised without the security block arrangement shown or the size of the various security blocks may be changed.

In accordance with the security block organisation of the line switch, the illustrative line switch is organised as two identical line switch modules. Each line switch module is self contained to the extentthat it can operate as a line switch for a number of subscriber lines.

Afurther aspect of the novel line switch is that distributed processing is advantageously utilised.

Three separate distributed processorfunctions are provided in each line switch module. First, one processor is utilised to com municatewith the system controllerS of Fig. 1 andt3co-ordinatetheoperations within the line switch module. A second processor is provided within a line switch moduleto control clock generation and rate conversion circuits A third processor is provided for a group of line circu ifs to control the operations ofthe line circuits and to gather information from the line circuits.

Afu rther aspect of the line switch architecture isthat an internal busing arrangement is provided wherein both control and PCM data are routedthroughoutthe line switch. With this arrangement, a standardised interface between each processor and the PCM bus may be provided.

In addition to having the capability for establishing connections between subscriber lines connected to the line switch and the swtiching network3, the present line switch has the capability of establishing intra-line switch connections without the switching network 3.

In accordance with the aforementioned security block organisation the line switch 1 is organised as two identical line switch modules 18, b. Each of the line switch modules 1 a, 1 b is self-contained to the extentthat it can operate as a line switch and is connectableto up to 160 subscriber lines or loops. The 160 lines associated with a module are arranged as two clusters of lines. Each cluster is in turn divided into 10 groups of lines, each group includes 8 lines and in the illustrative embodiment each group of 8 lines has its associated line surcuits arranged on one circuit card. It should be noted,that in other embodiments, a group may contain more or less lines and the lines may be arranged in one or more clusters.

Each line switch module 1 a, is coupled to the switching network 3 of Fig.1 1 two PCM lines PCMA, PCMB; bit clock lines CLKA, CLKB; and frame clock lines FSA, FSB. The PCM lines PCMA, PCMB operate at a 1.544 mbs. rate carrying 24voice channels in a frame in the North American network or at a 2.048 mbs. rate carrying 30 voice channels in a frame in European and many foreign networks. Although two PCM lines are shown, the line switch module may be connected to only one PCM line.

The frame clock lines FSA, FSB each provide a 4kHz signal from the switching network3 of Fig. 1' and each isusedto identifywhich incoming bitisacommon channel signalling bit. The common channel signall- ing bits occur in the 193rd bitpositionofeveryother frame. The intermediate 193rd bits are synchronisation bits and are used to determinethe A and B signalling frames.

The bit clock lines CLKA, CLKB: each provide a 1.544 mHz clock.

The interface logic 6 operates to derive various clocking signalsforuse inthe line switch module.

More significantly, interface logic 6 multiplexes and interlaces the PCM channels from the two PCM lines PCMA, PCMB onto bus PCM4 and demultiplexes and separates PCM channelsfrom bus PCM4tothe PCM lines PCMA, PCMB. More specifically, the bus PCM4 operates art a 4.096 mbs. rate. Data transmitted over bus PCM4 is arranged in frames of 512 bits, 480 of which are usedforPCM. If the lines PCMA, PCMB operate at a 1.544 mbs. rate with 24 channels per frame, the channels on the lines PCMA, PCMBwill be interlaced and rate converted to provide 48 channels each 10 bits wide at a 4.096 mbs rate on bus PCM4.If the lines PCMA, PCMB operate at a 2.048 mbs rate with 30 channels per frame, they will be interlaced and rate convertedto provide 60 channels each 8 bits wide at a 4.096mbs. rate on busPCM4.The remaining thirty two bits of each 512 bit frame on PCM4 are used for internal control of the line switch module.

The line switch controller7 receives common channel commands from the system controller 5 of Fig. 1 overthe PCM lines PCMA, PCMB and via the interface logic 6. The line switch controller 7 communicates with and controls the various circuits ofthe line switch module via bus PCM4 by utilising the aforementioned 32 bits.

Buffer and distributor circuits 9 are connected to the bus Pom4 and serve to buffer PCM signals between the bus PCM4 and the line cards 11, ring circuits 13, and other circuits. Two buffer and distributor circuits 9 in each line switch module are provided to partition the PCM buses into segments, i.e. security blocks, which are isolated from each otherto prevent propagation offaults in the line switch and the impact offaults in a group of lines upon all other lines in the line switch. Both buffer and distributor circuits in a line switch module contain identical circuitry for buffering and distributing PCM signals and each is connected to one of two clusters of line circuits. Additionally, the buffer and distributor circuits 9 provide buffering to the PCM buses on the other line switch module ofthe line switch.Thus, each line switch controller 7 has access to all the line circuits in both line switch modules of a line switch and PCM signals may be coupled to all circuits in a line switch. The buffer and distributor circuits 9 includes gating circuits which provide for intra-line switch calls between any two line circuits within the line switch withoutthe need to route the calls through the switching network 3 of Fig. 1. Additionally, one of the buffer and distributors 9 of a line switch module includes circuitryfor deriving various clocking signals from the various clock lines CLKA, CLKB, FSA and FSB.

Each buffer and distributor 9 is coupled to all the line and other circuits in a cluster by two PCM buses PCMLCA, PCMLCB each of which runs at a 4.096mHz rate. Oneofthe PCM buses, e.g. PCMLCA of line switch module 1 a, is derived directly from the bus PCM4 in the same line switch module. The other of the PCM buses, e.g. PCMLCB of line switch module 1b, is derived from the bus PCM4 ofthe other module.

In the North American Network each bus PCMLCA, PCMLCB will have 48 PCM channels at a 4.096mHz rate. Thus each line circuit will have access to 96 PCM channels in the line switch.

As pointed out hereinabove, each group of 8 line circuits is arranged on a single circuit card. Each of group circuits is controlled by a microprocessor which is in turn controlled bythe line switch controller7viathe 32 control bits available during each frame. By providing a mircoprocessor on each line card the work load on the line switch controller 7 is reduced, flexibility of application is obtained, and maintenance functions may be more easily provided.

Ring cards or circuits 13 are provided in the line modules. The ring cards 13 also include microprocessors which reside on the ring cards. The ring cards contain their own ring frequency generator and a ring card is controlled by the line switch controller 7 via the 32 control bits available during each frame.

Timing ofthe ringing is done via the microprocessors which reside on each line card and on each ring card.

Each line module also includes a power converter 12.

PCM BUSES (Figs. 3, 4, Sand 6) Each ofthe PCM buses PCMLCA, PCMLCB and PCM4 in the line switch of Fig. 2 carries information in framesof 125 microsec. in duration. One frame comprises 512 bits. Two alternate arrangements for formatting the 512 bit frame are shown in Figs. 4 and 5 which may be found on the same sheet as Fig. 1. If the line switch isto be used in a 24 channel system,the frames will be arranged as shown in Fig. 3. Fortyeight channels of 10 bits each and 32 additional bits which are utilised as control bits for control of internal line switch functions are provided.By providing 10 bit channels, the line switch may be readily utilised in integrated digital switches proposed for the future wherein each channel will be arranged as shown in Fig. 4. Fig. 4 shows each frame arranged as sixty 8bit channels and 32 control bits. Otherformats may easily be utilised for use in other systems.

Fig. 5 illustrates the distribution of PCM channels in the line switch of Fig.2 when used in a 24 channel system. To further simplify an understanding ofthe PCM channel distribution, only one cluster of line groups 11 and only one buffer and distributor 9 is shown for each line switch module 1 1 b. The format of Fig. 3 is utilised. In each line switch module 1 1 b two 24 channel, 1.544mHz PCM cm lines PCMA, PCMB are connected to the interface logic 6. The interface logic 6 provides rate conversion and interlacing between the PCM lines PCMA, PCMB and the 48 channel,4.096 bus bus PCM4.The buffer and distributor9 of each line module connects bus PCM4 to a 48 channel 4.096mHz bus PCMLCAwithin the same module and via an inter highway bus IH1 or IH2 to a 48 channel, 4.096mHz bus bus PCMLCB in the other module.

Therefore, each line circuit has access to a total of ninety-six 10 bit channels since PCMLCA and PCMLCB are each 48 channel buses. Further,with this configuration each line circuit has access to the two 24 channel PCM lines PCMA, PCMB inthesame module and also to the two 24 channel PCM lines PCMA, PCMB in the other module.

As pointed out hereinabove, the line switches 1 are controlled by the system control 5 of Fig. 1. The line switch controllers, in turn control the operation of the line circuits and other circuits within a line switch.

Turning nowto Fig. 6, the line switch controller7 communicates with the system controller via a common channel signalling arrangement overthe PCM lines PCMA, PCMB as described in the aforementioned patent. If it is assumed that the PCM lines operate at a 1.544mHz rate and one common channel signalling bit is provided in every other frame, then the common signalling channel operates at a 4kbs rate, i.e. bit/2 frames X 1 8000 frames/sec = 4 kbs. The buses PCM4, PCMLCA, PCM LCB are used to transmit 32 bits of control data perframe, each frame being 125 microsec. in duration.ThebusesPCM4, PCMLCA, PCMLCB operate as 256 kbs control data channels, i.e. 32 bits/frame X 8000 frames/sec = 256 kbs.A line switch controller 7 thus provides a common 256 kbs. control channel to each line circuit 11 orothercircuit 10 (which may be the ring circuit 13 or power converter circuit 12 of Fig. 2) via buses PCM4 and PCMLCA in a line switch module and additionally provides via bus IH1 or IH2 the same 256 kbs control data channel to other line switch modules in a line switch. Furthermore, bus IH2 or IHi via bus PCMLCB provides a 256 kbs control channel from the other line switch modules in a line switch to the line circuits of the line switch module shown in Fig. 6.

INTERFACE LOGIC 6 (Fig. 7) The interface logic 6 shown in block diagram form of Fig. 7 provides rate conversion and interlacing/ demultiplexing of data between the two PCM lines PCMA, PCMB and the bus PCM4. Bus PCM4 and other PCM buses in the line switch are clocked at a 4.096 mHz bit rate. These buses must interface to the PCM lines PCMA, PCMB which clock PCM at a 1.544mHz bit rate (or a 2.048mHz bit rate in other applications).

The interface logic6 providesforthe line switch internal clocks to be synchronised to the PCM line clocks CLKA, CLKB atframe boundaries such that no PCM bits are lost during rate conversion. This is accomplished by phase Icc!dng the internal clockto a PCM line clock by means of phase-locked loop (PLL) circuitry.

The rate converter portion of interface logic 6 includes memory elements forthe PCM bit streams.

ThePCMdatafrom bus PCM4arewritten into a memory in the rate converter as the data for PCM lines PCMA, PCMB are read from the memory.

Likewise, PCM data from lines PCMA, PCMB are written into a memory as the data for bus PCM4 is read from the memory.

Each ofthetwo PCM lines PCMA, PCMB is connected to one of two corresponding identical signalling frame and frame clock generator circuits 16a,16b. Each generator 16a, 16b derives an 8khz clock signal on leads 17a, 17b, respectively, from the bit clock signal received via the respective bit clock leads CLKA and CLKB and determines the presence of a signalling frame, and generates a signalling frame signal. The 8kHz clock is applied to a phase-locked loop and control circuit 18 and is supplied to a corresponding phase-locked loop and control circuit 18 in another interface logic 6 via leads 21 a or 21 b.

The phase-locked loop and control circuit 18 gener ates a 4.096mHz clock which is phase-locked to a selected 8kHz clock on leads 17a, 1 7b or on the leads 21 a, 21 bwhich come from an interface logic circuit 6 of another line switch module. Thus, the phase locked loop 18 of a line switch module may be locked to any one of four 8 kHz clocks. The 4.096mHz clock is provided on lead CLK4 and also to a clock generator circuit 19. The generator 19 providesaframingsignal at an 8kHz rate and clock signals at a 4.096mHz rate forthe transmit (TX) and receive (RX) rate converter circuits 20 and 21 respectively.

The PLLand Control Circuit 1 selects which one of thefour8 kHz clocks on lead 17a, l7b2laand2lbisto be used as a master clock of the line switch. The phase-locked loop and control circuit 18 contains failure detection circuitry for all the 8kHz clocks.

When the absence of a clock pulse occurs the failure detectorwill insert a pulse to maintain the oscillation frequency of PLL, and another one of the remaining working 8 kHzclockswill be selected as a master.

Additionally, there is co-operation between the PLL and control circuits 18 in the modules of a line switch such that all will operate to select the same 8kHz derived clock as a master. This assures that the PLL's of all line switch modules are synchronised to the same clock source.

Each PLL further includes self-checkcircuitrysuch that, if a PLL fails, the PLLwill automatically disconnect itselffrom the 4.096mHz line CLK4 and connectthe line CLK4to the output of the PLL in the other line switch module.

RX RA TE CONVERTER (Figs. 7, 8, 9) Rate conversion and interlacing/demultiplexing are provided primarily by the TX rate converter 20 and the RX converter 21. The bus PCM4 includes a transmit path 8a and a receive path 8b. Li kewise, the PCM lines PCMA, PCMB have both transmit and receive paths.

incoming PCM signals from the switching network 3 over lines PCMA, PCMB are applied to the RX rate converter21.The RX rateconverter21 operates asa FIFO type memory. Information received over the PCM lines PCMA, PCMB is stored at the rate of the PCM lines, i.e. 1.544 mHzforthe North American Network or 2.048 mHzforthe other systems. More specificallyforthe North American Network data from PCM line PCMA is clocked into RX rate converter 21 ata 1.544 mbs rate as determined by the 1.544mHz PCM clock line CLKA of PCM line PCMA.Likewise, data from PCM line PCMB is clocked into the RX rate converter 21 as determined byCLKB.The data stored in the RX rate converter 21 is read at a 4.096 mbs rate as determined by the 4.096mHz output of clock generator 19. The 1.544mHz clocks signals received over CLKA, CLKB are not necessarily synchronised.

However, the 4.096 mHz clock signals are phase locked to the clock signals of one ofthe PCM lines connected to a line switch.

Data from thetwo PCM lines PCMA, PCMB is alternately read from the RX rate converter and applied to the receive portion of bus PCM4, i.e. path 8b. Fig. 9a illustrates the interleaving of channels from the PCM lines PCMA, PCMB onto the bus PCM4.

The RX rate converter 20 is shown in greater detail in Fig. 9a, 9b and 9c. Fig. 9A illustrates the intercon nection ofthe circuits of Figs. 9b and 9c. The circuitry of box 951 for PCM line PCMA is duplicated in box 952 for PCM line PCMB and is shown in detail in Fig. 9b.

Fig. 9c shows box 990 in detail.Turning nowto Figs.

9b and 9c,serial PCM data is received from PCM line PCMA. Alternately received bits are stored in buffer flip-flops 902 and 903 by flip-flop 901. After every other bit is stored in the flip-flops 902, 903, the write address counter 904 is advanced by one count and the two bit stored in flip4lops 902,903 are stored in the memory 905. The fiip-flops 902,903 act as a two bit serial to parallel converter and thus form two bit wordsforstoring in the memory 905. Memory 905 is organised as a sixteen 2 bit words and is a random access memory. Memory 905 includes four address bit inputs and read/write input. A read write control circuit comprising flip-flops 907,908 and gates 920, 921 determines whether a read or write operation is to occur.An address selector 909 is used to select either a write address from counter 904 or a read address from counter 910.

When the data stored in flip4lops 902,903 is to be stored in memory 905, the selector 909 selects the counter 904 as the source forthe memory address and flip-flop 908 applies a write signal to the memory 905. When data is to be read from memory 905, selector 909 selects counter 910 as the source for the memory address and flip-flop 908 provides a read control signal to the memory 905. Data read from memory 905 is read as two bitwordswhich are alternately stored in the two bit latches 911,912. The flip-flop 932 and gates 933,934,935,936 and 937 control the loading of data read from memory 905 into the latches 911,912. A selector 913 undercontrol of flip-flop 915 alternately gates the outputs of the latches 911,912 onto the two bit line 914.Tri-state buffergates 916,917 controlled by gates 939,938 alternately connect one ofthe lines 914to the single line 961. The flip-flop 931 is used to select either the outputs from box 951 or 952 to be applied to the line 961. Flip-flop 931 changes its output state once for each voice channel on PCM4.

In effect, latches 911,912; selector 913 and gates 916,917 operate as a parallel to serial converter and flip-flop 931 operates to select either PCMA or PCMB as the source of data on PCM4. The read address counter 910 is driven by signal MCLKwhich as will be described below defines the format of PCM4. Pulses are provided by MCLK which correspond to the PCM voice bits on the bus PCM4.

The gates 938,940,941,942, flip-flop 939 decade counter 943 and 6 bit counter 944 operate to control the tri-state buffer gate 945. Gate 945 is enabled when PCM data from either PCM line PCMA or PCMB is to be transmitted over PCM4. In accordance with the format for PCM4 shown in Fig. 3, gate 945 is enabled forthe 8 PCM sample bit positions of each 10 bit channel and is disabled forthe remaining two bits.

Also, gate 945 is disabled forthe 32 control bit positions in each frame.

TO RATE CONVERTER (Figs. 7, lOa, bandc) The TX rate converter 20 of Fig. 7 mirrors the operation ofthe RX rate converter 21. Specifically, the channels of data on the transmit portion 8a of bus PCM4 are stored in a FIFO memory of the TX rate converter 20. Information is received ata 4.096 mbs rate and stored under control ofthe 4.096mHz clock signals of clock generator 19. Alternate channels of data stored by the TX rate converter are forwarded to the PCM lines PCMA, PCMB at a 1.544 mbs rate as determined by the respective clock signals CLKA, CLKB ofthe PCM lines. This demultiplexing operation is shown in Fig. 10a.

TheTX rate converter 21 of Fig. 7 is shown in detail in Figs. 10band 10c.Thecircuitryin box 1051 forPCM line PCMA is duplicated in box 1052 for PCM line PCMB. Box 1052 is shown in detail in Fig. 10c.

Serial PCM data is received over bus PCM4.

Alternately received PCM sample bits are stored in the two bufferflip-flops 1002,1003. Flip-flop 1004 which is clocked by the signal MCLK selects which of the flip-flops 1002 or 1003 into which a PCM bit is to be stored. The flip4lop 1005, and gates 1006, 1007 are used to synch ronise the operation offlip-flop 1004 each frame. After every other bit is stored in the flip-flops 1002,1003, the two stored bits are written into memory 1008. Memory 1008 is a random access memory organised as 16 words of two bits. Memory write addresses are generated by the counter 1009.

Counter 1009 is a 5 bit binary counter which is clocked at one halfthe rate ofthe MCLK signals byflip-flop 1004. The C output ofthe counter 1009 is used to control gate 1010 and through an inverter 1011 controls ofthe corresponding memory on box 1052 is to be written or read. Decode counter 1012 and gates 1013, l0l4control whether data isto be stored in or read from memory 1008 and also counts the number of bits (10) in each channel on bus PCM4.

When counter 1012 contains a countofO or 1, a memory write operation is inhibited. Address selector 1015 is used to select the address inputto memory 1008. Specifically, the selector 1015 selects output from counter 1009 for memory write address and counter 101 6for a memory read address. Counter 1016 is a 5 bit binary counter and is clocked by the PCM line clock CLKA. When data is read from memory 1008,thetwo bitwordsarealternately stored in the two bit latches 1017, 1018. Flip-flops 1019,1020 and gates 1021, 1022, 1024, 1025 provide control forgating the data into the latches 1017, 1018.

Gate 1023 in combination with the "B" output of counter 1016 provides for alternately selecting the latches 1017,1018 for storing the read data. The selector circuit 1026 under control of flip-flop 1027 alternately gates the contents of latches 1017 and 1018 on line 1028. Tri-state buffer gates 1029 and 1030 controlled by gates 1031,1032, 1033 are alternately enabled to alternatelyconnectthetwo outputsoftheselector 1026to PCM line PCMA.

Latches 1017, 1018, selector 1026 and gates 1029, 1030 operate as a parallel to serial converter.

Theflip-flop 1035 clears the counters 1016 whenev erthe framing bit position during a frame on the PCM line PCMAoccurs.

Tri-state buffer gate 1036 is enabled during the framing bit position to permit common channel signalling orframing information to be gated onto line PCMA.

The above described interlacing and demultiplex ing operations are premised upon the use of 24 channel 1.544 mHz PCM lines PCMA, PCMB and the bus PCM4 having the format of Fig. 4. If however, the PCM lines PCMA, PCMB are 3z channel 2.048mHz lines then the PCM clock lines CLKA, CLKB would operate at 2.048mHz and the format of Fig. 5 would be used for bus PCM4.

PHASE-LOCKED LOOPAND CLOCK CIRCUIT (Figs. 2, 7,11-20) The rate converter requiresthatthe clockfrequency of bus PCM4, i.e. be exactly 512/193 times the clock frequency ofthe PCM lines PCMA, PCMB. The phase difference between the two clocks must be controlled such that it falls within the limits required bythe rate converter hardware.

The maximum phase difference between the inter nal line switch clock and the PCM line clocks that is tolerable to the rate converter is limited only by the amount of memory storage in the rate converter.

However, a largetolerance for phase variation requires a larger amount of memory storage and causes a larger nominal delay in the rate converter.

The rate converter inherently causes 20 mic rosecondsofnominal delay interfacing the 4.096 mHz PCM to 1.544mHz PCM. Additional delay is designed into the rate converterto tolerate the phase variation in the internal line switch clock relative to the PCM line clocks CLKA, CLKB. To design the rate converter for minimum delayrequiresthephasevarianceofthe clocks to be tightly controlled.

The rate converter requires a specific relationship between the two clocks. This relationship is a defined sequence which repeats every frame (125 mic roseconds). Atframe boundaries (Bit 193 ofthe PCM line clocks) the rising edges of both clocks are synchronous when they are in phase. Any deviation is considered a phase error of the line switch clock.

In the illustrative embodiment of Fig. 2 two 4.096 mHz buses PCM4 are driven by the same clock i.e. one bus in each of the line switch modules 1 a, 1 b. Up to four external PCM lines, PCMA, PCMB in both line switch modules,whose phase relative to one another canvary,will interfacetothetwo busesPCM4. Since the 4.096 mHz clock will be phase-locked to an arbitralilychosen PCM line, the rate converter must be capable oftolerating the phase difference relative to other PCM lines. Also, the failure of any one PCM line must not affect service on the other PCM lines. An extension of this philosophy requires that any single failure in the PLL circuitry does not cause the loss of all four PCM lines.In summary, the PLL must have a phase error whose variance is minimised relative to the PCM lines; it must be capable of using any one of the PCM lines as a reference so that a failure of any PCM line does not affect service on the other PCM lines. Two PLL circuits must existthat are indepen dently selectable to ensure that a singlefailure in the PLL does not affectthe PCM clock CLK4.

The signalling frame and frame clock generators 16a, 16b of Fig. 7 includes a dividercircuitto derive an 8kHz signal from the 1.544mHz PCM line clock and the signalling frame clock. The divider circuitfor generator 1 6a is shown in detail in Fig. 11. The circuit includes gate 1101 connected to the line input of an eight bit counter 1102. Decoder gate 1103 is coupled to the eight bit counter provides an output to the "D" input offlip-flop 1104. Flip-flop 1104 has its clock input CLKconnected to CLKA and its Output provides an 8 kHzframing signal FS8A.The outputs FS8Aand FS8B of generators 16a, 16b are provided as inputs to the PLL and PLL control circuit 18 of Fig. 7.

Additionally these FS8A and FS8B outputs are provided to the other line switch module in a line switch. Similarly, FS8A and FS8B outputs from the other line switch module are provided as inputs to the PLL and PLL control circuit 18 of Fig. 7. Thus, the PLL and PLL control circuit has clock inputs derived from each ofthefourPCM lines connected to a line switch, i.e. the signals derived from CLKAandCLKB of line switch module 1 a and those derived from CLKA and CLKB of line switch module lbofFig. 2. Additionally, each ofthe circuits 16a, 1 6b of Fig. 7 generates a signalling frame signal SlGA,SlGB respectively.The signalling frame signals are also supplied to the PLL and PLL control circuit 18 from the circuits 16a, and 16bin both line switch modules.

Turning nowto Fig. 12, the signalling frame signals SIGA and SIGB are coupled to a 1 of 4selector 1205.

Each ofthefour8kHzinputs FS8A, FS8Bare indivudually connected to a failure detector circuit 1201,1202,1203, 1204.A 1 1 of 4 selector 1206 is to select one ofthe clock outputs from the failure detectors 1201,1202, 1203,1204 as the input FS8 to the phase-locked loop 1207. The selector 1206 as well as selector 1205 is controlled by the PLLcontroller 1250. The PLL 1207 is locked to the selected input. If a failure should occur in the PCM line from which the signal FS8 is derived, service to the other PCM lines would be interrupted if there was no capability of change to PCM line to which it is phase-locked. The failure detectors 1201,1202,1203, l204detectfailures in the PCM lines. Fig. 13 illustrates in detail the failure detector 1201.Normally a clock pulse at the 8kHz rate of FS8A arrives on every 125 microsec. If however, the time between two pulses is less than a predetermined interval, i.e. l00microsec.,theonesetshot 1301 will preventthe fast pulse from being propagated. If the time interval between pulses is greater than 100 microseconds, (and less than a second predetermined interval as discussed below) the pulse will be transmitted through gates 1303 and 1307. If the time interval between pulses is greaterthan the second predetermined interval, i.e. 150 mic roseconds,the one shot 1302 will time out, its Q outputwill go low inhibiting gate 1303. Additionally, the PLLcontroller 1280 will maintain a logic low on lead 1308 with the resultthatthe clear inputto one shot 1302 is low.With the clear input low, the output Q is maintained low. Thus, the one shot 1302 is "latched" in the low state. When Q is low,8is high.

Three bit binary counter 1305 is arranged such that when Q is low, a binary4 (ABC = 001) is loaded and when Q goes high,the counter 1305 may begin counting. Counter 1305 has a clock input coupled to the 4.096mHz clock CLK4. When the counter reaches binary count 6 (ABC = 011) a signal is provided atthe output of gate 1307. The output signal will persist through a binarycountof7 (ABC = 111) and will terminate at the next binary count (ABC = 000) i.e. a binary count of 0. When a binary control 0 is reached, the output signal at gage 1307 is terminated, a low is applied to the clear input of counter 1305 causing counter 1305 to "latch-up". Additionally, a signal is provided to the PLL controller 1250 on line 1309 indicating that a failure has occured. Thus, if a pulse is absent for more than 150microsec. a "phantom" pulse is provided and the PLL controller 1250 is informed of the failure. The PLL controller 1250 will select a different one of the PCM lines to use as a reference forthe PLL 1207. The phantom pulse is required to insure that the PLL 1207 does not miss a pulse. It no pulse were to occur, the PLL 1207 would function as though it were an entire frame out of phase and would slow down the 4.096mHz clock CLK4to correctforthis. This would result in the rate converter losing several frame of PCM before frame resynchronisation had occurred. Since the phantom pulse is out of phase with a normal pulse stream, it does cause an aberration in the operation of PLL 1207.

However, the PLL 1207 has a narrow loop bandwidth such that its output will be within the limits of the rate convertertolerance. The aberration in the PLL is less than 100 nanosec. of phase change.

A block diagram ofthe PLL 1207 is shown in Fig. 14.

The PLL 1207 comprises a clock input FS8 to which a voltage controlled oscillator (VCO) 1403 is slaved.

This is accomplished by dividing both the output of theVCO andthe inputclockto getacommon frequency, i.e. 8 kHz. The signalling frame and frame clock generator 1 6a of Fig. 8 divides the incoming 1.544mHzPCM line clock CLKAto obtain an 8 kHz output FS8A which is in this example selected by selector 1206 of Fig. 12 to provide signals on FS8. The divider 1404 of Fig. 14 divides the 4.096mHz output of VCO 1403 to also generate an 8 kHz signal. The phase detector 1401 generates an error currentwhich is integrated bythe loop filter 1402 to control VCO 1403.

When CLK4 is phase-locked to FS8, the frequency of VCO 1403 is exactly 512/193times CLKA.

In orderto minimisethe phasevarianceinthe PLL 1207, a phase detector is provided that gives a phase error near zero under steady state conditions. A simple phase detector that meets this critical requirement is shown in Fig. 15.

This phase detector requires TTL compatible inputs and unlike a quadrature oran exclusive-OR type of phase detector, it is not duty-cycle dependent on the inputs since it is strictly rising-edge sensitive which prevents phase lockfrom occurring on an integer multiple (harmonic) ofthe desired VCO frequency. It similarly rejects subharmonic phase lock.

The outputs (Q1 and 02) of flip-flops 1501, 1502 havethefollowingfourstates: State 1 = Both Q1 and 02 high State2=01 is low, 02 is high State 3 = Q1 is high, Q2 is low State 4 = Both Q1 and Q2 low State 4 is an unstable condition since this causes a set pulse which returns theflip4lop pair to State 1.

State 1 is of the "off" state in that both transistor switches (TR1 and TR2) are turned off in that state.

Fig. 16 shows the state diagram ofthe phase detector.

The phase detector cycles through the state diagram (Fig. 16) starting at State 1 progressing to either State 2 or3, to State 4, and returns to State 1. It makes this cycle once every 125 microseconds staying in State 1 for a large duration ofthe cycle. If f2 lags f1 in phase, the detector cycles through State 2; if f2 leads f1,it cycles through State 3. The time it is in State 2 or 3 is equal to the phase difference between fl and f2.

Thus, the phase detector has a +360 degrees of phase error operating range. If the error exceeds 360 degrees in either direction orf2 is not equal to f1 ,the cycle time is not necessarily 125 microseconds (out of lock condition). However, the phase detector will always cycle through State 2 when f2 is less than fl and through State3 when 2 is greaterthan 1.

Therefore, the phase detectorwill, in all cases, drive the control voltage toward a locked condition.

When in State 2 or 3, TR1 or2 is "on" causing currentto be pumped into or out ofthe loop filter capacitor (C). When fed into an infinintely high impedance, the voltage on the capacitor represents the summation (or integral) of all past phase errors.

This is extremely important, since different VCO's require different control voltages to oscillate at 4.096 mHz. The phase detector will operate at nearly zero phase error under steady state conditions independent of the DC voltage on the control voltage line. TR1 and TR2 need only to be turned on to correct for changes in PLL operating conditions and to replace the small amount of charge lost on the capacitor due to circuitry leakage during each 125 microsecond period. The phase error is independent of the vast majority of the PLL parameters including loop gain, supply voltage, loop filter values, and all VCO characteristics. In comparison, when using phase detectors in which the control line voltage is directly proportional to the phase error, the phase error is much more difficult to control.With such phase detectors any required change in control voltage (due to part variance ortemperaturechange) causes a proportional phase error change.

Phase error between the VCO and its reference is dependent primarily on the propagation delay through the dividers (512 and 193) and the phase detector. The dividers were both designed with this consideration and have on ly o ne fl ip-flop delay from input to output. The -:193 counter is that of Fig. 11 and the . 512 counter is shown in Fig. 17.The phase detector uses two flip-flops that are inherently closely matched since they are in the same integrated circuit package.

The PLL has a measured nominal phase difference between andf2atthe phase detector of 10 nanoseconds (less than 0.03 degrees). The total phase difference between CLK4 and CLKA or CLKB will be larger since there are additional circuit delay tolerances that affectthetotal phase difference. .

These include delay tolerances in the dividers, failure detector circuits, selectors and buffering circuits. The worst case phase difference between CLK4 and CLKA or CLKB is under 200 nanoseconds using LSI-TTL techonology.

The phase/frequency discrimination attributes of the phase detector give the PLL a capture and lock range limited only by the frequency range of the VCO.

Thisallowsgreatflexibility in the design ofthe remaining portions of the PLL.

The design of the loop filter 1402 of Fig. 14 involved several requirements. First, the loop must remain stable under all operating conditions. Secondly, the loop bandwidth must be selected such that the aberration in the 8kHz reference caused by a PCM line failure, does not cause the VCO to shift in frequency excessively. A damping factorgreaterthan .7 is desirable for stability. A damping facter under .7 is underdamped with zero being the limit before oscillations result. For stability analysis, the PLLcan be modelled as shown in Fig. 18, and this uses a PLL with a narrow loop bandwidth which is very stable since it is overdamped.

Two low-pass sections were added to the basic loop filter shown in Fig. 19 in order to reduce the aberration caused by a PCM line failure. In addition, isolation is provided between the VCO and active loop filter circuitry atthe VCO operating frequency of 4.096 mHz. Turning to Fig. 19a which illustrates the loop filter in simpleform,the cornerfrequenciesof the two low-pass filters R3, C1 and R4, C2 is more than an order of magnitude higher in frequencythan the natural frequency ofthe PLL. Thus, the additional phase shift contributed by these filters is negligible and lowers the damping factor only slightly.AJ-FET input op amp-2001 is used to provide the low leakage required since the VCO has an input impedance under 100k ohms. Fig. 20 illustrates in detail the complete phase-locked loop circuit combining the circuits of 15,17 and 19a. An unlock indication circuit 2003 provides a signal indicating ifthe phase-locked loop fails to maintain a locking.

The choice of the VCO is often the most important part of design of a phase-locked loop. However, in this application, the PLL characteristics that the VCO determine are not critical. This includes phase noise, voltage to frequency conversion linearity, temperature sensitivity, frequency range and spectral purity.

Three differentVCO'swere investigated. All were IC designs available from multiple sources and all met the requirements necessaryforthis application. The MC4024 and 74LS1 24 are TTL multivibrator designs using an RC network to determinefrequency.These parts have very similar performance with approx imately 4 nanoseconds of phase jitter atthe phase detector. This correlates with the MC4024 specification of 120 Hz RMS (typical) frequency noise deviation at4.096 mHz. The MC1 648 VCO is an ECL IC oscillator design requiring an external varactor and coil.

Because ofthe higher Q elements, it has superior phase noise and spectral purity. At 4.096 m Hz, the RMS frequency deviation is specified at less than 20 Hz.Thiscorrespondstoa a phase jitter at the phase detector of less than 1 nanoseconds. With the test equipment available, no phasejittercould be detected.

Turning back to Fig. 12, the output of the PLL 1207 is coupled to a one shot 1209 which acts as a failure detector. If the PLL 1207 fails to be reset within 350 nanosec. it will setflip-flop 1210 and will provide a failure indication to the PLL controller 1250. Flip-flop 1210 will automatically operate the selector 1214to switch to the phase-locked loop in the other line switch module e.g. 1 b of Fig. 2. The PLL controller 1250 must however switch the PCM line clock, e.g.

CLKA, to the PLL 1207 in the other module without missing clock pulses. The 500 nanosec. delay 1208 permits switching to the other PLLwithout missing clock pulses since the delay 1208 provides clock pulses for 500 nanosec. afterthefirstPLL 1207 has failed. The selectors 1212 and 1213 are also controlled byflip4lop 121 Oto switch the source for SIG and Frameto the other line switch module.

The PLL controller 1250 includes a microcomputer 1251 and an interface circuit 1252. The microcomputer 1251 in the illustrative embodiment is an Intel 8049 microcomputer. The interface circuit comprises a protocol interface circuit (PIC) which will be described in greater detail in conjunction with the line group controller. The microcomputer comprises an INTEL 8049 and is described in INTEL COMPONENT CATA LOG 1979, INTEL CORPORATION, 1979, pp 8-27 to 8-30.

The system controller 5 selects which PCM line clock isto be initiallyselected as the master clockto which the line switch clock circuits are to be synchronised. The system controller 5 informs the line switch controllers 7 in the line switch ofthe initial selection. The line switch controllers 7 then direct the respective microcomputers 1251 ofthe initial selection. If one of the line module microcomputers 1251 detects a failure in the clock circuits, it arbitrarily switches to another line clockto be used as a master.

The failure detecting microcomputerwill send information backto the system controllers via line switch controller7 designating the newly selected system controller 5 via line switch controller 7 designating the newly selected PCM line clock. The system controller 5 will then transmit command information tothe other module microcomputer 1251 via the respective line switch control 7 directing the other modules microcom puter to selectthe same PCM line clock as master. Thus, all modules within the line switch utilise the same PCM line clock to derive the internal line switch clocks.

LINE SWITCH CONTROLLER (Figs. 9, 10b, lOe) The line switch controller7 communicates with the system controller5 of Fig. 1 via the PCM lines PCMA, PCMB. The line switch controller7transmits and received information overthe common channelling signalling bits ofthe PCM lines PCMA, PCMB.The line switchcontroller7hasaccesstothe PCM iines PCMA, PCMB via the RX and TX rate converters. More specifically, turning to Fig. 9a, each time a common channel signalling bit appears on the PCM line, PCMA or PCMB, the associated clock lead FSA or FSB will provide a pulse.The clock pulse on the lead, e.g. FSA will cause the common channel signalling bit to be loaded into a bufferflip-flop 950A or 950B. The output of bufferflip-flop 950 or 950B is presented to the line switch controller via lead CCRXA or CCRXB. Information from the line switch controller 7 is inserted into the common channel signalling bit portions on lines PCMAand PCMB under control of the clock leads FS8A, FS8B. Turning to Fig. Ob, common channel signalling information from the line switch controller 7 for PCM line PCMA is provided on lead CCTXA and for PCM line PCMB on lead CCTXB. Tri-state buffer gate 1036 is enabled by CLKA during the common channel signalling bittime and gates the data bitfrom line CCTXA into PCM line PCMA. Likewise, data from lead CCTXB is gated onto PCM line PCMB.

Turning nowto Fig. the line switch controller is shown as comprising a Protocol interface circuit PIC and a microcomputer. The microcomputer utilised in the illustrative embodiment is the MCS85TM system available from INTEL CORPORATION which is described in INTEL COMPONENTDATA CATALOG 1979. Intel Corporation, 1979, 9-79 to 9-139. More specifically,the microcomputer configuration maybe that shown in Figure 1 at page 9-78 ofthe aforemen tioned Intel reference. The 8085 microprocessor, the 8156 RAM with I/O ports and timer, the 8355 ROM and the 8185 RAM shown are all described in detail in the aforementioned Intel reference.

The protocol interface circuit PIC serves as a control data interface between the parallel data bus of the microcomputerandthe high speed, bit serial PCM bus PCM4. The line switch controller7 operates as the master in a masterslave relationship with all other circuits connected to the PCM buses PCM4, PCMLCA, PCMLCB. More specifically, only the line switch controller7 may transmit control word commands overthe PCM buses. Acircuitwill transmit a control word response on the PCM buses only after receiving a command addressing that circuit. The convention established forthe line switch contol communication specifies that commands and responses must occur in pairs, only a line switch controller 7 can initiate a command, and the response to a command always occurs a fixed number of framers after the command.

BUFFERAND DISTRIBUTOR 9 (Figs. 21,22,23) Figs. 21 and 22 illustrate the buffer and distributor circuits 9 of Fig. 2 in greaterdetail. For purposes of clarity, only one buffer and distributor 9 for each line switch module 1 a, 1b is shown in Figs. 21 and 22. If in accordance with the aforementioned security block concept each line switch module 1 a, 1 b includes more than one buffer and distributor 9, then one buffer and distributor9 of each line switch module la, lbwill include both the circuitry of Figs. 21 and 22 and the other buffer and distributor 9 of each line switch module 1 a, 1 bwill include onlythe circuitry of Fig. 21.

The circuitry of the buffer and distributor 9 for each of the line switch modules la, shown in Figs. 21 and 22 are identical and corresponding terminals ofthe bufferdistributorcircuits have identical designations.

Fig. 21 illustrates the circuitry associated with the PCM buses PCM4, PCMLCA, PCMLCB and Fig. 22 illustrates the clock distribution circuit.

BUFFER (Figs. 21 and 23) Line switch module 1 a of Fig. 21 has terminals 707 and 708 connected to PCM bus PCM4, terminals 701 and 702 connected to PCM bus PCMLCA and termin als704and 705 connected to bus PCMLCB. Interposed between terminals 707 and terminal 701 are gate 740, shift register 741 and buffer gate 742.

Interposed between terminals 702 and 703 are gates 743 and 744. A path is provided between the output of gate 744 to the lead between gate 740 and shift register 741 via gate 745 and delay circuit 746. Gates 740 and 745 are controlled by gate 747 through delay 746a. Gate 747 has one input connected to terminal 703andanotherinputconnectodtoterminal7ls.

Gates 740 and 745 are arranged such that gate 740 is normally closed and gate 745 is normally open, but when an appropriate signal state is present at terminals 703 or715 gate 740 is open and gate 745 is closed. Together, gates 740 and 745 operate as a crosspoint switch which is util ised for intra-line switch calls as described below.

Terminals 704 and 705 are respectively coupled to terminals 714 and 713 via gates 748 and 749. Terminal 706 is connected directly to terminal 712.

Thetwo line switch modules la, ibareinter- connected via intra-line switch highways IH1 and IH2 and leads ILSVand ILSA. It should be notedthatthe gates 743 and 748 include an additional input CTRL which may be individually controlled in the event of a faultto inhibit PCM transmission.

When the system controller 5 (shown in Fig. 1) determines that a subscriber connected to a line circuit has requested a connection to anothersubscri ber connected to a second line circuit within the same line switch, the system controller 5 forwards com manes to line switch controller 7 shown in Fig. 2 indicating that an intra-line switch connection is required. The line switch controller 7, in turn, provides control signals to the line circuits ofthe originating and terminating parties thereby loading status bits in the respective line circuits. The status bits in turn provide gating of control signals AILS, BILS to the crosspoint switches 740,745 of Fig. 21 associated with the originating and terminating line circuits.The respective AILS and BILS signals are active only during the time period when the transmit channels occur, which the line switch controller 7 has assigned to the originating and terminating line circuits.

Turning nowto Fig. 23, the operation of switches 740,745 is described. Fig. 23 shows the two line switch modules 1 a, 1 each connected to the corresponding interface logic 6. In line module 1 a, only two line circuits 9A and 9B are shown and in line module 6 only two line circuits and 9Dare shown.

Itshould beunderstoodthatonlytwo line circuits are shown in each line switch module 1 a, 1 bfor purposes of clarity.

Two intra-line switch call operations will now be described, with reference to Fig. 23. First, assume that the subscriber A connected to line circuit group 9A has requested a connection to subscriber Boon- nected to line circuit group 9B, i.e. to a subscriber connected to the same line module. The system controllerS of Fig. 1 provides control signals to line switch controller 7 of line switch module 1 a, that an intra-line switch call between line circuits 9A and 9B has been requested. Line circuit controller 7 transmits commands to the line circuitgroups containing line circuits 9A and 9B, indicating that an intra-line switch call connection is to be established, and that bus PCMLCA is to be used. The transmit and receive channels forthe two subscribers A and B are also assigned.When the transmit channel for subscriber A occurs, line circuit 9A provides an active signal on lead AILS which closes switch 745 and opens switch 740. The transmit lead of PCM bus PCMLCA con- nected to terminal 702 is thus connected to the receive lead of PCM bus PCMLCAconnected to terminal 701.Thus, a PCM samplefromsubscriberA transmitted by line circuit 9A on the transmit portion of bus PCMLCA is "looped back" to the receive portion of bus PCMLCA. The receive channel assigned to subscriber B line circuit 9B is assigned such that it corresponds to the transmit channel of su bscriber A of line circuit 9A. Therefore line circuit 9B receives the PCM sample transmitted by the line circuit 9A. Likewise, when the transmit channel for line circuit9B occurs, line circuit 9B will apply an active signal to line AILS. Switch 740 will again open and switch 745 will again close for the duration ofthe transmit channel. Thus, the PCM sample transmitted by line circuit9B on thetransmit portion of PCM bus PMCLCA is "looped back" to receive portion of PCM bus PCMLCA. The receive channel assigned to line circuit 9A corresponds to the transmit channel assigned to line circuit9B. Therefore, line circuit 9A will receive the PCM sample transmitted by line circuit 9B.

Second, assume thatthe subscriberA connected to line circuit 9A has requested a connection to a subscriber D connected to line circuit 9D, i.e. to a subscriber connected to a different line switch module within a line switch. The system control of Fig. 1 provides control signals to line switch controller 7 of Fig. 2 ofthe line switch module 1 athat an intra-line switch call between line circuit 9Aof line module 1 a and line circuit 9D of line switch module has been requested and bus PCMLCA is to be used.

Line switch controller7 of line switch module 1 a assigns transmit and receive channels to line circuits 9aand 9dof Fig. 23. Again, the assigned transmit channel of line circuit9a will correspond to the receive channel of line circuit 9dand the assigned transmit channel of line circuit9dwill correspond to the receive channel of line circuit9A. The crosspoint switches 740 and 745 are then operated in the same manner as described above, with the exception that line circuit9D provides active signalsto control the switches 940 and 945 instead of line circuit 9B.

DISTRIBUTOR (Figs. 22 and 24) The clock distribution circuitry of the buffer and distributor circuits 9 for two line switch modules is shown in Fig. 22. Each buffer and distributor 9 has input terminals 709,710,711 connected to lines FS, CLK4, and SIG from a corresponding interface logic 6.

Aclock generator circuit 770 generates a codec clock signal CLKT1 and a frame clock signal FSD1. The outputs FSD1 and CLKT1 are coupled to terminals 712 and 713 respectively via controlled switches 760 and 761 and are directly coupled to terminals 721 and 720.

Input terminals 718 and 719 are coupled to terminals 712 and 713 respectively via controlled switches 762 and 763. Each of the switches 760,761,762 and 763 has a control input commonly connected to lead GEN CTRLand operates such than when a signal having a first state is present on GEN CTRL, switches 760 and 761 are open and switches 762 and 763 are closed.

When a signal having a second state is present on GEN VTRLswitches760 and 761 are closed and switches 762 and 763 are open. By means of the switches 760; 761,762,763, the FSD and CLKT signals for a line switch module may be supplied either by the clock generator 770 within the line switch module or by the clock generator in another line switch module.

The GEN CTRL lead of a line switch module is connected to the line switch controller in the same line switch module.

Timing signal waveformsforthe signals FS, CLK4, FSD and CLKT are shown in Fig. 24.9 stage counter within the clock generator 770 repetitively counts 512 4.096mHz pulses before recycling.

The FS signal received from the interface logic 6 of Fig. 2 is a frame synchronisation pulse which occurs every 125 microseconds. CLK4 is a 4.096mHz clock signal from interface logic 6. SIG is likewise provided by interface logic 6 of Fig. 8 and indicates the occurrence of signalling frame, i.e. SIG is normally low and goes high the frame before a signalling frame. CLKT a CODECclockwhich generally comprises bursts of eight pulses of a 4.096mHz clock.

The relationship of CLKT to the CODEC channels is shown. When a frame bit FSD occurs, the next 32 bits received overthe PCM bus are control bits. More specifically, in a system with 10-bit channels, the next three channels are reserved for control data and channel three is extended by two bits. In a system with 8-bit channels, four channels are reserved for control.

FSD is a framing signal which will vary as shown depending on whether it occurs during a signalling frame or not.

Turning backto Fig. 22, the CLK4 lead coupled to terminal 710 is connected to outputterminal 775 via switch gate 772 and is connected directly to output terminal 773. Inputterminal 774 is coupled to output terminal 775 via switch gate 776. The terminal 774 is connected to terminal 773 of the other line module.

The switch gates 772 and 776 operate in the same manner and under control ofthe same GEN CTRL signal as the aforementioned switch gates 760,761, 762,763 so that either CLK4from line module 1 a or 1 b may be utilised as the source for4.096 mHz clock signals on lead CLK4LS.

LINE CARD OR GROUP (Fig. 25) One ofthe line groups 11 of Fig. 2 is shown in detail in Fig. 25. Each line group includes a common circuit portion 31 and eight line circuits 32 in the illustrated embodiment. In other embodiments, the common circuit portion 31 may be on a separate circuit card and a line group may have more or less than eight line circuits. The common circuit portion includes a control interface 33 which is coupled to PCM bus PCMLCAvia buffer 901 and switch gate 902, and to PCM bus PCMLCB via buffer 903 and switch gate 904.

The control interface is also coupled to the FSD and CLKT leads via buffers 905 and 906, respectively. The interface 33 extracts and inserts control data bits which are transmitted and received overPCM buses PCMLCAand PCMLCB. Control data received overthe buses are examined to determine if the address received matches the address of the line group. If the received address matches, an interrupt signal is sent via line INTto a line card processor 34 which may be a conventional microprocessor of a type well known in the art. It should be noted thatthe line group address, which the control interface 33 matches against is, in fact supplied bythe line processor34and is stored by the control interface 33. The line group address is supplied to the processor 34 by leads 35to provide a unique address to the line card.

Other control data are communicated between the processor34andthe PCM buses PCMLCA, PCMLCB via the control interface 33, which acts as a data buffer. It should be noted thatthe control interface 33 is provided because the microprocessor 34 can not operate at a high enough rate to handle 4.096 mbps serial rate on the PCM buses. In other applications, which do not utilise a high speed serial bus for control information, e.g. where control information is re ceived in parallel, or at a slower rate, the control interface 33 may not be necessary. In other words, the microprocessor 34 may be directly coupled to the bus carrying the control information.

After the processor 34 determines that an operation is required within its associated line group, it will select the appropriate line circuit, as determined by portions of the control data received over PCM, bus PCMLCAorPCMLCB.

The processor 34 is connected to the line circuits 32 via bus 36. Bus 36 includesten separate leads, specifically, a separate clock lead CLK/SWHKn (n= 1 to the number of circuits in a group) foreach ofthe line circuits, a bi-directional data lead DATA, and an address latch enable lead COMMAND. Control and data information is transferred between the line group processor 34 and the per line control interfaces over the common lead DATA. The information transfer is controlled bythe COMMAND lead and the CLK/SWHKn leads.

Additional leads connected to the line group are CLK4LS, which is the 4.096 mHzclock signal, leads AILS, BILS, and SUPVY. The lead CLK4LS is distributed to the line circuits via a buffer gate 907. The per line control interface 44 of each ofthe eight line circuits 32 generates the signals AILS, BILS and SUPVY. The AILS outputs of the line circuits are "wire-ored" to the input of buffer output gate 908.

Likewise the BILS outputs are "wire-ored" to gate 909 and the SUPVYoutputs are "wire-ored" to gate 910.

The 4.096mHz clock CLK4LS is applied to a divide by two circuit 94 which provides a 2.048 mHz clock signal CLK2for use by the line circuits.

LINE CIRCUIT (Figs. 25,26,27) Each line circuit 32 includes conventional line circuit transmission components: test and ring relays 38 and 39, a subscriber line interface circuit 40, a filter circuit 42 and a codec 43. The codec 43 is of a known type which is operable in a so called "microprocessor controlled mode" of operation, wherein the channel assigned buy a line switch or system controllertothe associated line circuit is stored by the codec and is used to determine when the codec will become active. The codec may be defined as "active" when the codec is transmitting or receiving over PCM buses. One such codex is commercially available from the INTEL Corporation and is identified as type number 291 OA.

Each linecircuit32furtherincludesa perline control interface 44 which interfaces between the commoncircuit31 andthelinecircuittransmission components. Control of portions ofthe per line control interface 44 is achieved bythe processer34 transmitting control words over bus 36. Each of these control words is 12 b its in length and arranged in format as shown in Fig. 26.Bit 0 determines whether the control operation is a read or write; bits 1-3 are address bits for the per line control interface; bit 4 is unused; bit5 is setaccording towhetherthe line card is in a system using 8 bit or 10 bit PCM words on its buses; bits 6,7 and 8 are used to control external components such as power control, device test relay, and ring relay; bit 9 enables the line circuit; bit 10 is used to signifyintraline switch calls; and bit 11 selects which ofthe two PCM buses PCMLCA or PCMLCB will be utilised by the line circuit.

One of the per line interfaces 44 of Fig. 25 is shown in greater detail in Fig. 27. The CLKISWHK lead is a dual function lead. More specifically, one function of this lead is that of a normal clock lead to clock data into or out of the line interface circuits 44. The other function ofthe CLK/SWHK lead isto return switch hook status to the line group microprocessor34 of Fig. 25. The selection as to which ofthe above two functions is provided is determined by the state of the COMMAND lead and register 48.When the COM MAND lead is high, andwhen bit 0 of the control word indicates a read, then gate 46 enables tri-state buffer 47 thereby coupling the lead SWHK, which is connected to the SLIC 40 of Fig. 25 and indicates current switch hook status, to the line card processor 34 of Fig. 25 via CLKISWHKN lead. When the COMMAND lead is low, gate 45 is enabled and control bits from the DATA lead of bus 36 are shifted into shift register 48. After the four control bits 0-3 are loaded in register 48, the COMMAN D lead goes high disabling gate 45 thereby holding the control bits in register 48. Gates 49 and 50 form a decoder circuit to gate clock pulses from the CLK/SWHKN lead to shift register 53. Similarly, gates 51 and 52 determine whether data will be stored in or read from register 53.If data isto be stored in register 53, the next eight bits, i.e. bits 4-11 ofthe control word are shifted into the register 53 from the Data lead. The A/B select lead control gates 54,55,56, 58to connect either bus PCMLCA or PCMLCB to the coded PCM bus 64A, 64B.

Flip-flop 65 provides buffer timing forthetransmit PCM signal from bus 64A.

TheTSX lead provides timing from the CODEC43 of Fig. 25. Gate 66 controls gating oftheTSXsignal into bufferflip-flop 67. The Q output of the flipJlop 67 is connected to gates 60 and 61 which are controlled bytheA/B select bit to steertheTSXsignal to leads TSXA orTSXB. The 0 output of flip-flop 67 is also coupled to gates 62 and 63 which are controlled by the A/B select bit and the ILS bit. The outputs of gates 62 and 63 are coupled respectively to leads AILS and BILS.

In some applications it may be desirableto return switch hook information at a rate fast enough to detect dial pulsing without utilising the A/B signalling bits ofthe PCM bus. To accomplish this, switch hook information from lead SWHK from the line circuit 32 is gated onto the supervisory lead SUPVY during one half ofthe channel time assigned to that circuit. The channel during which switch hook information is gated is determined by a signal on lead TSX from the CODEC 43 of Fig. 25.

A counter 74 divides each channel into two parts.

Flip-flops 82,83 provide synchronisation for counter 74. The A/B select bit controls gate 75 to determine in which ofthetwo partsofachanneltheswitch hook information is to be gated. Gates 76 and 77 gate the switch hook information from flip-flop 67 to supervisory lead 72. The line circuit enable bit controls gating ofthe lead TSX at gate 66 for maintenance purposes, i.e. if it is determined that a codec 43 of Fig. 25 is defective, the line circuit enable bit is utilised to preventthe CODEC 43 from interfering with the operation of the remainder of the system.The ring relay, test relay and power control flip-flops 80,79,78, respectively control the application of ringing signals from bus 73 of Fig. 1 4control connections to a test bus and to apply powerto the entire transmission circuit elements of Fig. 14. Register 81 delays the frame clock FSD from the buffer-distributor9 of Fig. 22 by one channel time to provide a receive frame clock which is coupled to a CODEC 43 of Fig. 25 via lead FSDRX. The Euro Select bit, i.e. bit 5 of Fig. 26, determines whether the channel delay corresponds to8orlObits.

GAIN/BALANCE (Figs 25,28,29,30,31) Turning backto Fig. 25, the gain/balance control circuit 41 provides software selection of transmit gain, receive gain and balanceforthe line circuit.

Control ofthe gain/balance circuit 41 is achieved by the line card processor 34transmitting control words overthe serial data bus 36 in a mannersimilarto that described with respect to the per line controller interface circuit 44 hereinabove. The control words are illustrated in Figs. 28 and 29. As shown in Fig. 28, a control word forthe gain/balance operations comprises 28 bits arranged as follows: a read/write bit, three address bits, a clock control bit, three unused bits,fourbitsfor line balance network selection and eight bits each for transmit and receive gain selection.

As shown in Fig. 29, a control word for CODEC control comprises 12 bits which includes a read(write bit, three address bits, two mode bits and six channel assignment bits.

The gain/balance circuit 41 is shown in detail in Fig.

30. The fi rstfour bits of a control word are loaded into and stored by register 84 in the same manner as described for register 48 of Fig. 27. Address decoders 85,86,109 and 87 decode the contents of the register 84. Decoder 85 determines if the control word is to provide gain/balance settings to be stored in register 88. Decoder 86 permits loading of assigned channel information into a register 89. Decoder 87 controls the loading of channel assignment information from register 89 into the CODEC using data clock lead CLKD.

If firstfour bits of the control word shown in Fig.

28 stored in register84as indicated above activate decoder 85, then the next 24 bits are then stored in register 88. The clock control bit stored in bit 023 of register 89 controls the state of flip-flop 92 which in turn is connected to excl usiveor gate 93 to determinewhethertheclocksignal on leadCLKDis inverted or not. The four line balance network selection bits of shift register 89 control analog solid state switches 94 to selectively connect capacitors 95 and 96, network 97 and 98, to the SLIC circuitvia the balance selection lead BAL. It should be noted that the capacitors 95 and 96 and resistor 98 may be replaced with other network components orwith entire networks.

Gain control amplifiers 103 and 105 are connected such that they are interposed in the transmission path between the SLIC 40 and Filter 42 as shown in Fig. 25.

More specifically, receive amplifier 103 has one input connected to lead RXF connected to the receive filter and an output lead RXS connected to the receive path ofthe SLIC. Amplifier 105 has one input connected to SLIC transmit lead TSX and an output connected to transmitfilter lead TXF.

The eight receive gain control bits stored in register 88 control analog solid state switches 101 to selectively connect resistors 102 to one input of amplifier 103. Likewise the 8 transmit gain control bits stored in register 88 control analog switches 104 to selectively connect resistors 106to one input of amplifier 105.

It is desirable to maintain closely controlled gain steps, e.g. less than .1 db, over a wide range of environmental conditions. Typically, gain circuits comprise a resistive laddersimilarto that formed by resistors 106, each leg of the ladder having an analog switch connected in series with a resistor. The ladder in turn forms a resistive divider with another resistor 107. The analog switches have a finite impedance which will vary from unitto unit and with environ- mental changes. Typically, analog solid state switches have impedances of nominally 50 to 150 ohms in the on state. The variation ofthe on-state impedance would thus contribute a significant changeto the ratio of the dividers previously used.

This problem is significantly reduced in the gain control circuits shown in Fig. 30. Specifically, an amplifier having an extremely high input impedance such as a FET differential input amplifier, e.g. 103 or 105, is connected in the divider network. The resistancevalues maythen be made relatively high,for example in the order of tens ofthousands of ohms, and accordingly, the impedance variations in analog switches which are on the order of a hundred ohms, will have a negligible effect on the gain through the circuit.

The gates 91 are controlled by the read/write bit of the control word to determine whether a portion of a control word is to be stored in register 88, or whether the contents of register 88 are to be read via the data bus 37.

A CODEC control word has two distinct addresses.

One address (hereinafterfirst address) will result in either the register 89 being loaded or read by the line card processor 34, and the other address (hereinafter second address) will cause the contents of register89 to be loaded into a CODEC 43. If the control word contains the first address and the read/write bit indicates a write operation, the mode and channel assignment portion of the control work is loaded into register 89 via decoder 86. If the control word contains the first address and the read/write bit indicated a read operation, the contents of register 89 are supplied to data bus 37 via gate 108, which is controlled by portion of the decoder 87. When the register 89 is read,the gates 109 will feed each bit, as read, back into the register such that after a read of the register 89, the contents of register 89 are unchanged.

If the control word contains the second address, the contents of register 89 are supplied to the CODEC over data bus 37 via gate 108. Gate 108 is controlled by portions ofthe decoder 87. Other portions of decoder 87, when enabled, supply clock pulses to a CODECvia gate 93 and line 90 to clockthe data from bus 37 into the CODEC.The gates 109 wiil again operateto loop the data bits loaded into the CODEC from register 89 back into register 89.

As noted hereinabovethe control wordstransmit- ted between the line groups and the line switch controller7 of Fig. 2 overthe buses PCMLCA and PCMLCB as shown in Figs. 2 and 6 comprise 32 bits.

Fig. 31 illustrates the format of these control words.

Each control word transmitted from the line switch controller 7 of Fig. 2 comprises four eight bit bytes, indicated as Bytes 1-4. Byte 1 may include one parity bit which is calculated overthe entire word, and includes seven address bits. Byte 2 includes five function bits which control the function that line card processor 34 isto perform, and three bits to designate which one ofthe eight line circuits on a line card isto be effected. Bytes 3 and 4 contain control data as required forthefuntion specified bythefunction bits.

After a control word is transmitted to the line card by the line switch controller7,the processor34will respond by returning the same control word backto the line switch controller 7 if the control word indicates a write operation. If the control word indicates a read operation, the line card processor 34 will return bytes 1 and 2 as originally transmitted from the line switch controller7 and will include response data in Bytes 3 and 4.

PROTOCOL INTERFACE CIRCUIT/CONTROL INTER FACE33 (Figs. 25, 32) The control interface 33 of Fig. 25 comprises the protocol interface circuit PIC and is shown in detailed blockdiagram form in Fig. 32 is connected to buses PCMLCA and PCMLCB. For purposes of clarity, single lines are used to represent multi-line buses and the number of lines in a bus is indicated atvarious points along the bus.

Initially, the line group processor 34 of Fig. 25 reads the line card address from leads 35 as shown in Fig. 25 andloadsthisaddressintothecontrol interface latch 123 of Fig. 32 in thefollowing manner. The processor 34 transmits the address to the latch 123 over the DATA/ADD lines to the control interface 33. This internal register address is buffered by buffer circuit 120 and is presented to the input of register 121. The line card processor 34 concurrently transmits a signal overthe ALE lead which causes the internal register address to be stored in register 121 The internal register address decoder 122 decodes the address to apply an enable signal WR FIXED ADDER on lead 124.

The line card processor 34 then transmits a data word which contains the line card wired address. The data word is applied to the input of register 123 via bus 125 and is gated therein via lead 124 by address decoder 122 upon receipt of a strobe signal from the processor on write enable lead WE. The register 123 then contains the wired address of the line card.

Atiming generatorcircuit 127 receives the FSDand CLK4LS clock signals from the buffer distributor 9 of Fig. 21 and generates various timing signals for controlling the operation ofthe control interface 33.

The FSD signal is used to control the timing of a clock signal on lead S/R clock. The clock signal on S/R clock controls the storing or transmitting of control words between bus PCMLCAand register 128 and between bus PCMLCB and register 129. Initially, a control word is received on one ofthe two buses e.g. PCMLCA. As the control word appears on bus PCMLCA in serial form it is gated via selector circuit 130 to shift register 128 using S/R clock.Registers 128 and 129 are 32 bit rngisters. Afterthe proper number of clock pulses have been provided by S/R clock, a strobe signal is applied to the ADDR/MATCH ENA lead thereby enabling a comparator 131 which comparesthe address portion of the control word in register 128 with the line group address stored in latch 123 and generates a signal on lead 132 if the addresses are the same. Similarly control word received on bus PCMLCB are stored in register 129 via selector 145 and the address portion thereof is compared to the line circuit address by comparator 133 which generates a signal on lead 134 ifthose addresses are the same.Gate 155 logically "or's" leads 132 and 134 and will provide a signal to the line group microprocessor 34 of Fig. 25 on its interrupt lead INT if an address match occurs for either bus PCMLCA or PCMLCB.

Afterthe line group processor 34 is interrupted it will then obtain the control word by first transmitting an address overthe DATA/ADD bus. The address is stored in latch 121 and decoded by decoder 122 which, in turn, activates the STATUS RD line. The STATUS RD line enables gates 135 and 136 which provide indications on the DATA/ADD bus as to which of the two comparators 131 or133detectedtheline card address.

The line group processor 34 will then, via a series of commands, obtain 24 bits ofthe control word from the appropriate one ofthe registers 128 or 129. If the control is obtained from register 128, then multiplexer 137 and buffer 138 are utilised. Similarly, if the control word is to be obtained from register 129 then multiplexer 139 and buffer 140 are utilised.

Response data from the line group processor 34 may be returned to the line switch controller 7 via buses PCMLCA or PCMLCB.

Response data from the line group processor 34 is stored in a preselected one ofthe registers 128,129 by a series of co mm ands fro m the processor 34 which controls the gating of data through buffer 120 via bus 125 from register 128 or 129. The response data is written into register 128 or 129 as eight bit parallel bytes. The response data is transmitted from the registers 128, 129 over the buses PCMLCA, PCMLCB respectively by the S/R clock signals in the following manner.

After the last byte of data is stored in the selected register 128, 129, the timing generator 127 will generate an enable signal at a predetermined time over leads A CONTRL or B CONTRL respectively. The outputs of gates 141 and 144 are connected to buses PCMLCA and PCMLCB respectively. The outputs of gates 142 and 143 are "wi re-ored" with the leads TSXAand TSXB respectively from the line cricuits.

The S/R clock is used to shift the response data onto PCMLCA or PCMLCB. More specifically, the S/R clock provides pulses at a 4.096mHz rate, with 42 pulses being supplied in a burst during oneframe. The first 32 clock pulses of the 42 pulse burst are used to clock the response data from the registers 128 or 129 onto busPCMLCAorPCMLCB.

The last 32 clock pulses of the 42 pulse burst are used to clock the control data from the bus PCMLCA or PCMLCB into the register 128 or 129. During the time when the middle 22 pulses are provided, control data is being stored into registers 128 or 129 while simultaneously reponse data is being read from the register 128 or 129. This arrangement is provided because system timing constraints require a 10 bit skew between the receive PCM data bus and the transmit PCM data bus.

Selector 146 is provided for maintenance purposes.

The register 147 is also provided for maintenance purposes and permits the processor 34 to disable either or both ofthe comparators 131, 133 and to control selectors 130,145 and 146.

SELFTEST(Figs. 32, 33) One feature ofthe control interface 33 is that it includes a self-test mode of operation in which the serial output of one of the shift registers 128 or 129 is selected as the serial input data sou rce for both ofthe registers 128 and 129. Selectors 145,146 and 130 provide feedback paths for the registers 128, 129 during the self-test mode. In this test mode, the shift registers 128, 129 are loaded with test data by the microprocessor and allowed to shiftfor several frames. Proper operation of the shifting function of the registers 128, 129 and the address decoder circuit 122 can thus be verified without affecting the PCM buses PCMLCA, PCMLCB.

Aself-testprogram routine is executed during power-on initialisation of the line switch. This selftest routine exercises the circuitry of the control interface 33 and produces a golno-go result.

The test initialised the control interlace by loading a code in the mode control register 147 which provides a signal on the SELFTEST ENA level to operate selection 130 and a signal on FDBKAJB operates selector 146 such that a feedback path for register 128 is enabled. A signal is provided to the timing generator 127 which responds to preventing trans mission overthe buses PCMLCA, PCMLCB, and by inhibiting the shifting of the registers 128, 129. The A comparator 131 and B comparator 133 are enabled.

Next, a register 128 is loaded with the following test data (in hexadecimal): byte 1 = 63, byte 2= Cl, byte 3 F8, byte 40 O XF. The address latch 123 is loaded with F8, i.e. the same as byte 3 on register 128. After the A register and address latch 123 have been loaded, the A and B registers 128 and 129 are allowed to shiftfor eight PCM frames. Fig. 33 illustrates the contents of the A and B registers 128,129 at the start ofthe self-test and after each frame of shifting. Note thatthe A and B registers 128 and 129 are clocked 42 times each frame as explained above. TheA and B control registers are 32 bits long.Therefore, the test data in the A register 128 will be in effect rotated left (left being defined as toward the most significant bit position) a total of 10 (42 modulo 32) places after each 42 pulse clock burst. After eightframes of shifting the test data in the A and B registers 128 and 129 will have been rotated 16(42 X 8 modulo 32) places left ofthe position of the test data at the start of the test. Since the address latch 123 contains F8 and the A and B address comparators 131 and 133 are enabled an address match should occur with comparators only during the eighth frame of shifting. If both comparators 131 and 133 do not indicate a match condition during the eighth frame, a failure has occurred.If both comparators do indicate a match,the contents of both the A and B registers 128, 129 are compared with thefollowing expected data: byte 1 = F8, byte 2 = OF, byte 3 = 63 and byte 4 = Cl. Any mismatch ofthe data in the A and B registers 128 and 129 with the expected data indicates a failure.

AUTOMA TIC GAIN SETTING (Figs. 25,30,32,35) The control interface 33 of Fig. 32 includes a voice channel data sampling register 189 which permits the microprocessorto monitor channel data appearing on one ofthe PCM buses PCMLCA. This channel sampling feature allows the line group processorto measure and thus provide automatic gain setting of the line circuits. Register 189 is an 8 bit shift register that is serially loaded everyframe with data appearing on a predetermined channel of bus PCMLCA. The PCM SAMPLE SHlFTclockfrom timing generator 127 clocks the serial data from PCMLCA into the register 189. Between the 8-pulse clock bursts, data in register 189 can be read bythe microprocessor sending an appropriate command to the control interface.Note thatfor clarity, the connection from the address decoder 122 to the register 189 has not been shown.

The above described variable gain circuit permits adjustment ofthe gain ofthe amplifiers 103 and 105 to a predetermined value without costly hand seiection of parts. The analog switches 101, 104 respectiveliy control portions of a resistance divider 102,106 to changethe gain of amplifiers 103,105 respectively.

In the embodiment shown, the predetermined value-k--or amplifier 103 is set such that the overall loss in the receive path ofthe line circuit is -.25dB. The predetermined value for amplifier 105 is set such that the overall gain in the transmit path of the line circuit is 0dub. The accuracy of these settings is made to within +0.1dB. The incremental difference between adjacent steps of PCM representations representing the peak required signal Icveis (of around OdBm) is approximately 0.4dB for mu-law encoding.As shown below, itis possible to use the PCM representations to measure analog signals peaks wiLh an accuracy greater than thatofthe PCM steps.

Thefrequencyfora reference signal used in measuring the gain of the transmission circuit is chosen as 1.024kHz sampling rate. By choosing the freq uency of the reference signal in this manner, the reference signal will be sampled at or near its peak amplitude a predictable number of times over a predetermined number of cycles.

For a 1.024kHz signal sampled at an 8kHz rate, 16 cycles are required before the PCM representations are repeated. During a 16 cycle period, 125 PCM representations are generated.

From mu-lawtablesitcan be determined thatthe maximum linear level of a signal that can be encoded is 8159 linear units and, by definition, corresponds to the peak of a signal having an r.ms. level of +3.17dBm. The peak value ofthe OdBm reference signal can be calculated by reducing 8159 by 3.17dB.

In this manner, the peakvalue of OdBm signal is determinedtobe5664.l785linearunits. From mu-law tables it can be determined that 5664.1785 linear units lies between level 118 which represents 5599 linear units and level 119 which represents 5855 linear units It can be calculated that levels 118 and 119 are approximately 0.4dB apart.

If 125 successive PCM samples are monitored and at least one sample correspondsto level 119 or a higher level, the signal represented by that group of 125 samples is 9 reater than OdBm by more than 0.278dB.

If all samples in a group of 125 successive PCM samplesarelessthanlevel 1 18 then the signal represented is loss than OdBm by more than 0.1dB.

Fora OdBm signal, the number of samples N out of 125 successive PCM sample that are at level 1.18 either positive and negative polarity is determined as follows: The reference signal may be represented as A sin cot If decision level 118 is represented by A' then A'=Asin(Tl ~Q) (1) 2 where Tl - Q representsthe angular displace 2 mentfromzerodegreewherethe reference signal reaches level 118.

Solving equation (1)for0yields 0= n - since A (2) 2 A The probabilitythat any one PCM sample in a group of 125 successive samples will be above level 118 is p 40 = 20 (3) 2n rt Substituting equation 2 in equation 3 yields p = 2 using' A' = 1 - Isin-l A (4) rr 2 A n A The numberofPCM samples in a group of 125 successive samples which will be at level 118 for a OdBm signal is N=125P (5) For a OdBm signal A=5664 A' = 5599 and N may be caiculated as 12.08.

Equations 1-5 may be used to determinethe signal levels corresponding to the number of occurrences N of level 118samples in a successivegroup of 125 PCM samples yielding the results shown in the table below: TABLE N A(dBm) N A (dBm) N A(dBm) 1 -.0998 9 -.0447 16 +.0762 2 -.0978 10 -. 032 17 +.0992 3 -.0944 11 -.0173 18 +.1236 4 -.0896 12 -.0014 19 +.1494 5 -.0834 13 +.0159 20 +.1767 6 -.0758 14 +.0346 21 +.2055 7 -.0669 15 +.0547 22 +.2357 8 - .0565 In the illustrative embodiment, if 9 to 16 level 118 samplesoccurduring 125 successive PCM samples, it is assumed that the sam ples represent a signal of OdBm.From the above table it is seen that this sample range represents OdBm over a range of -.0447dBm to +.762dBm.

Advantageous use ofthe variable gain circuitry is made to permit automatic adjustment ofthe gain setting. Each line circuit shown in Fig. 25 is connected via a test relay 38to a test bus test bus is multiplied to all the test relays of a line group and may also be multiplied to all line groups in a line switch module. Alternatively, the serial test buses may be utilised within a line switch module, each test bus being multiplied to one or more line groups. To set the TX gain of a line circuit, i.e. the gain of amplifier 105,the line switch controllerwillconnectananalog milliwatt generator to the propertestbus.

Fig. 35 illustrates the arrangementfor setting the transmit gain in a line circuit, the line switch controller 7 will connect a milliwatt generator 3601 to the proper test bus. The line group processor 34 of the line circuit which is to have its transmit gain set will then actuate the test relay 38 of the line circuit. By means ofthe sample register 189 of the control interface 33 shown in Fig. 32, the line group processor will monitorthe PCM outputofthe line circuit. The line group processorwill then incrementally change the gain of thetransmit amplifier 105 in Fig. 30 of gain and balance circuit 41 by selectively actuating actuation of the analog switches 104 shown in Fig. 30. After each incremental change in the gain, the line group controller will monitor the PCM date.The iterative process will continue untii the monitored PCM signals representa signal of OdBm +0.1 dBm. The line group processor 34 will then release the test relay 38 and signal the line switch controller7thatthe transmit gain has been set. The line switch controller 7 can direct a line group processor34to setthe transmit gain of other line circuits. To set the receive gain, i.e. that of amplifier 103 in Fig. 30, the line switch controllerwill cause a digital signal representing a signal 0.25dB greaterthan 1 milliwatt to be applied on a PCM channel that can be used for testing.One way in which this may be done is for the line switch controller7to connectthe milliwattsource 3601 providing a 0.25dB signal to a test bus 3602 and direct the line group processor 34to connect a line circuit, e.g. line C, which has had its transmit gain adjusted to the desired level connected to the test bus 3602. The line circuit C will then provide PCM signals representative ofthe milliwatt source on a predetermined channel of the PCM bus PCMLCA or PCMLCB. If it is assumed that line circuit A is to have its recieve gain set, then line group processor 34will actuate test relay 38 connecting the output of line circuitAto the test bus 3603.Another line circuit B which has previously had its transmit gain set will be connected to the same test bus 3603 by actuating its test relay 38.

Thus, the analog output of line circuitA will be connected to the analog input of line circuit B. The line circuit B will be directed by the line group processor 34 to receive the PCM channel which is carrying the digital PCM tone signal from line circuit C.

The PCM output of the line circuit Awill be monitored by its line group processor34again utilising the sample register 189 ofthe control interface 33.

The line group processorwill incrementally change the gain ofthe receive amplifier in line circuitA until the output is again OdBm +O.1dB.Thusthetransmit gain of any circuit can be set to O -f 1 db and the receive gain of any circuit can be set to 0.25 dB + 0.1dB.

OTHER LINE CARD ARRANGEMENTS (Figs. 35, 36, 37 and40) The detailed drawing of Fig. 25 may be redrawn in general block diagram form with various leads grouped into buses as shown in Fig. 38. Bus 1701 includes PCMLCA, PCMLCB, AILS and BILS. Bus 1702 includes CLK4LS, FSD, CLKT and CLK2.

The line card control interface 33 as described hereinabove interfaces between the line group processor34 and the PCM buses PCMLCA and PCMLCB forthe interchange of control information over the PCM buses.

In another embodiment of the invention shown in Fig. 39, a separate control bus 1801 is provided and the line group control interface 33 is not connected to the PCM bus 1701. In this arrangement, control information may be exchanged between the line card control interface 33 and a line switch control 7 in the system control 5 over a control bus 1801.

In yet another embodiment ofthe invention shown in Fig. 40, the line group processor 34 may directly communicate via bus 1901 with the line switch control 7 orthe system control 5.

CALL SET-UP (Figs. 1,2, 14) When a subscriber line (A) goes of T-hook, the line switch controller7 of Fig. 2transmits a common channel command to the system control 5 of Fig. 1 informing the system control 5 of a new sequence.

The system control 5 responds by transmitting a common channel command to the line switch controller7 and assigning a PCM channel A and providing dial tone.

The line switch controller7 transmits a channel assignment command (32 bit control word) to a line group processor34 of Fig. 14.The line group processor 34 activates power to the line circuit for A, assigns transmit and receive channels atthe CODEC forA, and updates the status of the line circuit. The system control Swill then monitor dial pulses from A.

When the system control 5 determines the called line (B), the system control 5 will Swill transmit a common channel commandtothe line switch controller7 of the line switch to which B is terminated. The line switch controller7 will request the busylidle status of Bfromthe line group processor34 associated with the group of lines including B. The line group processor 34 responds by transmitting B's busy/idle status to the line switch controller 7. If B is idle, the line switch controller7transmitsthe channel assignmentto the line group processor 34. The line group processor34then enables powerto B's line circuit, assigns the transmit and receive channels to B's CODEC, and updates the line circuit status.

RINGING AND CALL CONNECT (Figs. 1,2 and 14) The system control 5 sends a common channel command to the second line switch controller7 to connect ringing to B, and tu rns on a ring-back tone generator to provide ring-backtoneto A. If A and B are both terminated at the same line switch, the system control 5 may also indicate an intra-line switch call. The second line switch controller 7 sends ring commands to a ring circuit B of Fig. 2 and to the line group processor 34for B. The line group processor 34 begins a ringing routine.

When B answers, the system control 5 sends a stop ringing command to the line switch controller 7. The line switch controller7 in turn sends ring terminate commands to the ring circuit 13 and line group processor 34. The line group processor 34terminates the ring routine.

If the call is an intra-line switch call, the receive channels for A and B are switches upon commands from the line switch controller7to the line group processors 34.

CALL DlSCONNECT(Figs. 1, 2and 14) When A and B go on-hook, the system control 5 sends a common channel command to one ofthe line switch controllers7to releasethe line. The line switch controller in turn sends a discon nect command to the line group processor 34. The line group processor 34 removes powerfrom the line circuit and updates the line circuit status. This procedure is repeated forthe other party.

Claims (24)

1. An interface circuitfor coupiing a line circuit to a control processor and to at least one PCM bus, said interface circuit including: (a) a first set of terminals coupled to said one PCM bus; (b) a second set of terminals coupled to said control processor and including a control terminal, a data terminal and a clock terminal; (c) a third set of terminals coupled to said line circuit and including a pair of PCM terminals coupled to the PCM signal input and output of said line circuit; (d) first means coupledtosaid second set of terminals for receiving command information at said data terminal andforstoring said command information in responseto said control terminal having a predetermined state;; (e) a second means coupled to said data terminal and responsive to said first means for storing control received at said data terminal; and (f) third means responsive to said control information stored in said second means for coupling said PCM terminals to said first set of terminals.

2. An interface circuit in accordance with claim 1, including a fourth set ofterminals coupled to a second PCM bus; said third means being responsive to said stored control information to couple said PCM terminals to said fourth setofterminals.

3. An interface circuit in accordance with claim 2, wherein said third set of terminals includes a first terminal for receiving timing signalsfrom said line circuit, said timing signals indicating a predetermined PCM channel on saidfirstorsecond PCM bus, said interface circuit comprising further means re sponsive to said control information for coupling said firstterminal to a third or a fourth terminal, and wherein said timing signals at said third terminal determine a PCM channel on said first PCM bus and said timing signals at said fourth terminal determines a PCM channel on said record PCM bus.

4. An interface circuit in accordance with claim 3, including afifthterminal coupled to a supervisory lead, a sixth terminal in said third setofterminals coupled to said line circuit for receiving switch hook information, and fifth means responsive to said control information for coupling said fifth terminal to said sixth terminal whereby said switch hook in formation is transferred to saidsupervisorylead.

5. An interface circuit in accordance with claim 4, wherein said fifth means isfurther responsive to said timing signal such that said switch hook information is transferred to said supervisory lead during said predetermined channel.

6. An interface circu it for interfacing a line circuit, a PCM bus and a control processorwherein the line circuit includes a pairofterminals connected to a PCM line, the control processor includes a data line, a control line and a clock line and the PCM bus includes a bidirectional PCM bus, and a clock lead, wherein the interface circuit includes:: (a) a first set ofterminals coupled to said PCM bus including a first pair of PCM terminals coupled to said bidirectional PCM bus and PCM clockterminal coupled to said clock lead; (b) a second set ofterminals coupled to said control processor, said first set ofterminals including a data terminal coupled to said data line, a control terminal coupled to said control line, and a clock terminal coupled to said clock line; (c) a third set ofterminals coupled to said line circuit including a second pair of PCM terminals coupled to said PCM line;; (d) first register means coupled to said data, control and clockterminalsfor receiving and storing first control information transm itted by said processor over said data line when said control line has a predetermined state; (e) second register means coupled to said data terminal and responsive to said stored first control information for receiving and storing second control information transmitted by said processor over said data line; and (f) circuit means responsive to certain of said stored second control information for coupling said first pair of PCM terminals to said second pair of PCM terminals.

7. An interface circuit in accordance with claim 6, wherein the line circuit includes a terminal coupled to a timing signal line, the line circuit providing timing signals on said timing signal line to indicate a predetermined one of a plurality of PCM channels, wherein the third set of terminals includes a timing terminal coupled to said timing signal line, wherein the interface circuit includes second circuit means coupled to said timing terminal and responsive to said timing signals for supplying gating signals to said circuit means, and wherein said circuit means is further responsive to said gating signals for coupling said first pairof PCM terminals to said second pair of PCM terminals.

8. An interface circuit in accordance with claim 7, further including third circuit means responsive to said stored second control information for enabling or inhibiting said timing signals.

9. An interface circuit in accordance with claim 6, wherein said second register means is further re sponsive to said stored first control information for transmitting said stored second control information to said processor via said data line.

10. An interface circuit in accordance with claims 6 or7, including forth circuit means coupled to said PCM clockterminal and to said circuit means for synchronising PCM signals from said line circuit to clock signals a said clock lead.

11. An interface circuit in accordance with claims 6 or7, wherein said line circuit includes a ring relay terminal coupled to a ring relay, said interface circuit comprises a first relay terminal coupled to said ring relayterminal; and fifth circuit means coupled to said ring relay terminal and responsive to said stored second control information for supplying control signals a said ring relay.

12. An interface circuit arrangement interfacing a processor to one or more time division multiplexed buses carrying PCM information and control information, said processor having a bidirectional data bus, and interrupt input, and control outputs, the interface circuit including: (a) a first set ofterminals coupled to one of said time division multiplexed buses; (b) a first clock terminal for receiving bit clock signals; (c) a second clock terminal for receiving framing clock signals; (d) a data terminal coupled to said data bus; (e) an interruptterminal coupled to said interrupt input; (f) control terminals coupled to said control outputs;; (g) first timing means coupled to said first and second clock terminals for generating first control signals in response to said framing clock signals and said bitclocksignals; (h) first register means coupled to said first set of terminals and responsive to said first control signals for storing said control information; (i) address match means coupled to said first register means for comparing said stored control information to a predetermined address information and coupled to said interruptterminal for generating an interrupt signal when said stored control information corresponds to said predetermined address information;; (j) means responsive to first predetermined control signals at said control terminals and first predetermined command information at said data terminal for coupling said first register means to said data terminal whereby said stored control information is transmitted to said processor.

13. Anarrangementinaccordancewithclaim 12, including means responsive to control signals at said control terminals and second predetermined command information received at said data terminal for coupling said first register means to said data terminal for receiving and storing information subse quentiy received at said data terminal and means for coupling said first register means to said first set of terminals fortransmitting said stored information over said one time division multiplexed bus.

14. An arrangement in accordance with claim 13, wherein said time division multiplexed buses each include a first path for carrying PCM information and control information to said interface circuit and a second path for carrying PCM and control information from said interface circuit and wherein the arrangement also includes means for controlling said first register means whereby said first register means receives and stores said control information from said first path while concurrentlytransmitting said stored information over said second path.

15. An arrangement in accordance with claim 14, wherein said first register means comprises a shift register, and said controlling means provides clock pulses to said shift register.

16. An arrangement in accordance with claim 15, wherein said control information comprises "x" bits of data, said stored information comprises "x" bits of data, and the shift register has "x" storage cells, wherein said controlling means provides a burst of y clock pulses, andy = x + n and wherein said shift register is responsive to the firstx clock pulses of said burst of y clock pulsesfortransmitting said x bits of stored information, and responsive after the first n clock pulses of said burst of y clock pulses for receiving and storing said control information.

17. An arrangement in according to claim 12, including a second set of terminals coupled to a second one of said time division multiplexed buses, second register means coupled to said second set of terminals and responsive to said first control signals for storing said control information, address match means coupled to said second registermeansfor comparing said control information stored in said second register means to said predetermined address information and for generating said interrupt signal when said control information stored in said second register means corresponds to said prede termined address information, and means respon siveto saidfirst predeterrnined control signals and second predetermined command information at said dataterminalforcoupling said second register meansto said data terminal whereby said control information stored in said second register means is transmitted to said processor.

18. An arrangement in accordance with claim 17, including means responsive to control signals at said control terminals and second predetermined command information received at said data terminal to couple one or the other of said register means to said data terminal for receiving and storing information subsequently received thereat and means for coupling said first register means to said first set of terminalsfortransmitting the information stored in said first register means over said one time division multiplexed bus and for coupling said second register means to said second set ofterminalsfortransmitting said information stored in said second register means over said second time division multiplexed bus.

19. An arrangement in accordance with claim 18, wherein said one and said second time division multiplexed buses each include a first path for carrying PCM information and control information to said interface circuit and a second pathforcarrying PCM information and control information from said interface circuit and wherein the arrangement also includes means for controlling said register means such that said first register means receives and stores the control information from said first path of said one time division multiplexed bus while concurrently transmitting said information stored in said first register means over said second path of said one time division multiplexed bus and such that said second register means receives and stores said control information from said first paths of said second time division multiplexed bus while concurrently transmit ting said information stored in said second register means over said second path of said second time division multiplexed bus.

20. An arrangement in accordance with claim 12, 13,14,15,16,17, 8 or 19, including feedback means responsive to control signals at said control terminals and third predetermined command information re ceived at said data terminal for providing a feedback path for said first register means whereby said stored control information is concurrently transmitted from said first register means over said feedback path and is restored in said first register means.

21. A line switch, which includes one or more time division multiplexed buses carrying PCM information and control information, a plurality of processors, each of said processors having a bidirectional data bus, in interrupt input, and control outputs and a plurality of interface circuits, each of said interface circuits coupling a corresponding one of said plurality of processors to all of said one or more time division multiplexed buses whereby said plurality of processors exchange control information over said one or more time division multiplexed buses, each of said interface circuits including:: (a) a first set ofterminals coupled to one of said time division multiplexed buses; (b) a firstclockterminal for receiving bit clock signals; (c) a second clock terminal for receiving framing clock signals; (d) a data terminal coupled to said data bus; (e) an interruptterminal coupled to said interrupt input; (f) control terminals coupled to said control outputs; (g) first timing means coupling to said first and second clockterminalsfor generating first control signals in response to said framing clock signals and said bit clock signals; (h) first register means coupled to said first set of terminals and responsive to said first control signals for storing said control information;; (i) address match means coupled to said first register means for comparing said stored control information to a predetermined address information and coupled to said interruptterminal for generating an interrupt signal when said stored control information corresponds to said predetermined address information; and (j) means responsive to first predetermined control signals at said control terminals and first predetermined command information at said data terminal for coupling said first register means to said data terminal whereby said stored control information is transmitted to said processor

22.A line switch in accordance with claim 21, including means responsive to control signals at said control terminals and second predetermined command information received at said data terminal for coupling said first register means to said data terminal for receiving and storing information subse quently received at said data terminal and means for coupling said first register means to said first set of terminals for transmitting said stored information over said onetime division multiplexed bus.

23. A line switch in accordance with claim 22, including feedback means responsive to control signals at said control terminals and third predetermined command information received at said data terminal for providing a feedback path for said first register means whereby said stored control inform an tion is concurrently transmitted from said first register means over said feedback path and is restored in saidfirst register means.

24. A line switch in accordance with claim 22 including feedback means responsive to control signals at said control terminals and third predetermined command information received at said data terminal such that a selected one of said first or second register means has an output selectively coupled to the input of either or both of said first and second register means whereby information stored in said selected one register is transmitted through said feedback means and is received and stored in said either or both of said first or second register means.