GB2119188A - Digital phase-locked loop - Google Patents

Abstract

A phase locked loop system for receiving a data input DIN with a predetermined bit frequency f includes a source (10, D1 D2) of clock signals with a frequency nominally equal to f, means (14-16) for dividing each clock period into three regions corresponding to early, normal and late arrival of the data signal relative to the clock signal and means (D3 D4 D5) for deciding which region the data signal occurs in and for respectively advancing or retarding the phase of the clock signal if the data signal occurs in the early or late region. A frequency 4f provided by crystal oscillator 10 is fed to D-type bistables D1, D2 forming a divide-by-four counter, which can be advanced or retarded by 90 DEG by placing or holding D2 in its inset state. Bistable D6 provides a data output RxD in synchronism with the re-timed clock signal RxC. <IMAGE>

Description

SPECIFICATION Digital phase-locked-loop Background to the invention This invention relates to digital phase-locked loops. A phase-locked loop (PLL) is a device which is arranged to receive an input data signal and to produce an output clock signal having the same frequency and locked in phase to the input data. Such devices find application, for example, in data transmission systems or in magnetic recording.

One previously proposed digital PLL comprises a divide-by-n counter which is driven by an oscillator at n times the bit frequency of the input data, and produces one output clock pulse for each complete cycle of the counter.

The clock signal is locked in phase to the incoming data by causing the data pulses to reset the counter to a predetermined state.

However, one problem with this form of PLL is that if the incoming data gets significantly out of phase with the clock signal (i.e.

in the region of 180 out of phase), the PLL may fail to operate correctly since it may not be able to decide whether the data is early or late with respect to the clock. One object of the present invention is to provide a novel digital PLL in which this problem is overcome.

Summary of the invention According to the invention, a digital phaselocked loop for receiving an input data signal having a predetermined bit frequency, comprises: (a) means for producing a clock signal having a frequency nominally equal to the bit frequency of the input data signal, (b) means for producing three control pulses in each clock period, thereby dividing each clock period into three regions corresponding to early, normal and late arrival of the input data signal relative to the clock signal, and (c) means for deciding which region the input data signal occurs in, and for respectively advancing or retarding the phase of the clock signal if the input data signal occurs in the early or late region.

It will be seen that dividing the clock cycle into three regions in this way ensures that there is never any ambiguity as to whether the data signal is early or late.

One embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings.

Brief description of the drawings Figure 1 is a circuit diagram of a digital PLL, and Figures 2 and 3 show the waveforms of various signals illustrating the operation of the PLL.

Description of an embodiment of the invention Referring to Fig. 1, the PLL receives an input data signal DIN having a bit frequency of 1 MHz, each bit period containing either a positive-going pulse representing a binary zero, or no pulse, representing a binary one.

The PLL produced an output clock signal RXC of the same frequency, locked in phase to the data signal. The PLL also re-times the data signal DIN to synchronise it with output clock signal RXC, producing an output data signal RXD.

The circuit includes a crystal oscillator 10 producing a square wave input clock signal CLK and its inverse CLK having a frequency of 4MHz, i.e. four times the bit frequency of the input data signal.

The clock signal CLK is applied to the clock inputs of two D-type bistables D1 and D2, so that each bistable is triggered by the rising edge of a pulse of the input clock signal CLK.

The normal output 11 of bistable D1 is connected to the data input of bistable D2, while the inverse output 1 2 of bistable D2 is connected to the data input of bistable D1. The two bistables D1 and D2 thus form a divideby-four counter (Dt D2) with a cycle of four periods of the input clock signal CLK. The clock signal CLK and the states of the bistables D1, D2 are shown in Fig. 2. The inverse output 1 2 of bistable D2 provides the output clock signal RXC.

The normal output 1 3 of bistable D2 is combined with the inverse clock signal CLK in a NAND gate 14, while the inverse output 1 2 of the bistable D2 is combined with the normal output 11 of bistable D1 in a NAND gate 1 5. The outputs of these two gates are combined in a further NAND gate 16 to form a control signal CON obeying the equation: CON = (D1 AND RXC) OR (D2 AND CLK).

The resulting waveform of the control signal CON is shown in Fig. 2. It can be seen that the control signal CON contains three pulses for every cycle of the counter D1 D2 and hence divides each period of output clock signal RXC into three regions E, N and L, the boundaries of which are defined by the rising edges of the pulses of the control signal CON.

These three regions correspond respectively to early, normal and late arrival of the leading edge of a data poulse with respect to the output clock signal RXC.

The PLL also includes three further D-type bistables D3, D4 and D5 connected in series.

Bistable D3 receives the data signal DIN at its clock input and has a constant high logic level applied to its data input. Bistable D4 is clocked by the control signal CON, while bistable D5 is clocked by the inverse of the input clock signal CLK. The inverse output 1 7 of bistable D5 is connected to the CLEAR inputs of bistables D2, D3 and D4 so that whenever bistable D5 is set, the low logic level at the output 1 7 forces bistables D2, D3 and D4 into their unset states.

The operation of the PLL is illustrated in Fig. 3. Whenever a data pulse is received, bistable D3 is set immediately, and bistable D4 is set at the first rising edge of control signal CON after this. Bistable D5 is then set at the next rising edge of the inverse clock signal CLK. The setting of bistable D5 unsets bistables D3 and D4, and bistable D4 then causes bistable D5 to be unset again one period of the inverse clock signal CLK later.

The set state of bistable D5 also forces bistable D2 into the unset state i.e. forces the output clock signal RXC to the high level.

Fig. 3A shows the normal situation in which the output clock signal RXC is substantialiy synchronised with the data input signal DIN, such that the leading edge of each data pulse falls somewhere in the normal region N. It can be seen that in this case the set state of bistable D5 fall entirely within the unset state of bistable D2. Hence, the low level from the output 1 7 of bistable D5 has no effect on bistable D2, since bistable D2 is already unset. Thus, there is no adjustment of the phase of the counter D1, D2 in this case.

Fig. 3B shows what happens if the output clock signal RXC gets out of phase with the incoming data signal DIN such that the leading edge of a data pulse falls somewhere within the early region E. It can be seen that in this case the set state of bistable D5 occurs one period of CLK earlier than in the normal case. The low level from the inverse output 1 7 of bistable D5 therefore forces bistable D2 into its unset state. This effectively steps counter D1, D2 forward by one state, and thus advances the phase of the output clock signal RXC by 90 , bringing it more closely into synchronism with the incoming data.

Fig. 3C shows what happens if the leading edge of a data pulse falls somewhere within the late region L. it can be seen that in this case the set state of bistable D5 occurs one period of the input clock signal CLK later than in the normal case. The low level from the inverse output 1 7 of bistable DD5 thus holds bistable D2 in the unset state. This effectively prevents the counter D1, D2 from advancing one state, and therefore retards the phase of output clock signalk RXC by 90 , bringing it more closely into synchronism with the incoming data.

The data output signal RXD is obtained from the inverse output of a further D-type bistable D6. This bistable has the signal output clock signal RXC connected to its clock input, the normal output 1 8 of bistable D4 connected to its data input, and the inverse output 1 7 of bistable D5 connected to its PRESET input.

The effect of this is shown in Fig. 3. It can be seen that in each case, whether the data arrives in the normal, early or late regions, the bistable D6 converts the incoming pulsed input data signal DIN into the output data signal RXD which has a low level for each positive-going pulse in data signal DIN and a high level for each bit period in which no pulse is received. The output clock signal RXC provides the necessary timing information for sampling this signal, the falling edge of the output clock signal RXC occurring at or near the mid-point of each bit period of output data signal RXD. Thus the output clock signal may be used on the clock signal for demodulators or other arrangements for operating upon or using the output data signal RXD.

Claims (8)

1. A digital phase-locked loop for receiving an input data signal having a predetermined bit frequency, comprising: (a) means for producing a clock signal having a frequency nominally equal to the bit frequency of the input data signal, (b) means for producing three control pulses in each clock period, thereby dividing each clock period into three regions corresponding to early, normal and late arrival of the data signal relative to the clock signal, and (c) means for deciding which region the data signal occurs in, and for respectively advancing or retarding the phase of the clock signal if the data signal occurs in the early or late region.

2. A phase-locked loop according to Claim 1, wherein the phase of the clock signal is advanced by 90D if the data signal occurs in the early region, and retarded by 90 if the data signal occurs in the late region.

3. A phase-locked loop according to Claim 1 and in which the clock signal means comprises a counter having a cycle of n states, the counter being driven by a periodic signal having a frequency nominally equal to n times the bit frequency of the input data and producing one output clock pulse for every cycle of the counter.

4. A phase-locked loop according to Claim 3, wherein the clock signal is advanced by stepping the counter forward by one state and is retarded by preventing the counter from stepping forward.

5. A phase-locked loop according to Claim 3 or 4, wherein the counter comprises first and second bistables each having a data input, a normal output and a reverse output, the bistables being so connected that the normal output of the first bistable is connected to the data input of the second bistable and the inverse output of the second bistable is connected to the data input of the first bistable whereby the counter has a cycle of four states.

6. A phase-locked loop according to Claim 5, wherein the means for producing the con trol pulses comprises gating means for producing a control pulse when the first bistable is set and the second bistable unset, or when the second bistable is set and the periodic signal which drives the counter is at a low logic level.

7. A phase-locked loop according to Claim 5 or 6, wherein the clock signal is advanced or retarded by clearing the second bistable to the unset state at respective first or second points in the cycle of the counter.

8. A digital phase-locked loop substantially as hereinbefore described with reference to Fig. 1 of the accompanying drawings.