GB2115962A - Decimal arithmetic system - Google Patents

Abstract

A decimal arithmetic system comprises an end-around carry type adder (4) for performing arithmetic addition or subtraction of two numbers in binary coded decimal representation after a first correction for the decimal arithmetic operation to output the result of the arithmetic operation (4a) and a one's complement (4b) thereof, a first discriminator circuit (6) for determining whether to select the complement of the result of the arithmetic operation as the adder output, and a second discriminator circuit (5) for determining the presence or absence of carry signals to next higher-order digits for each of digits. When the complement of the result of the arithmetic operation is selected as the adder output, a second correction for the decimal arithmetic operation is effected for those of the digits for which respective carry signals were present at the time of the arithmetic operation. When the complement of the result of the arithmetic operation is not selected as the adder output, the second correction is effected for those of the digits for which the respective carry signals were absent at the time of the arithmetic operation. <IMAGE>

Description

SPECIFICATION Decimal arithmetic system The present invention relates to a decimal arithmetic system and more particularly to such a system which is designed to be capable of performing arithmetic operations at a higher speed.

In a hitherto known decimal arithmetic operation for two numbers in decimal representation each consisting of a sign and an absolute value, processing for addition is carried out after correction has been made by adding a value "+6" to every decimal digit of either one of two corresponding numbers in binary boded decimal representation, if the arithmetic operation substantially concerns addition (namely, if the signs of both numbers are same and the arithmetic operation to be effected is addition or if the signs are different but the arithmetic operation is subtraction. The result of the addition is outputted intact when a carry signal is produced from the digit.

On the other hand, when no carry signal is derived from the digit in concern, recorrection processing is performed by adding "-6" to the aforementioned result of the arithmetic operation.

More particularly, the processing for addition of two corresponding decimal digits each consisting of four bits can be classified into three schemes illustrated in (a), (b) and (c) of Figure 1, that is, a first case where the result of addition is not greater than 9 (i.e. no carry is produced in addition of "+6" and no carry is necessary in the decimal representation of the result of addition), as is illustrated in (a) of Figure 1, a second case where the result of addition is in the range from 10 to 15 (i.e. no carry is produced unless "+6" is added and carry is necessary in the decimal representation of the result of addition), as is illustrated at in (b) of Figure 1, and a third case where the result of addition is not smaller than 16 (i.e. carry is in addition of "+6" and carry is necessary in the decimal representation of the result of addition), as is illustrated in (c) of Figure 1. In the case of the addition illustrated in (a) of Figure 1, no correction is required. However, when the aforementioned correction by adding "+6" is automatically done, recorrection of adding "-6" has to be made. In the case of the addition shown in (b) of Figure 1, the binary coded decimal representation "0001 0110" should be obtained as the processing of addition.

When the correction of adding "+6" to one of the numbers is automatically made, the recorrection of adding "-6" is unnecessary because the "+6" correction results in the value mentioned above (see the righthand column of Figure 1(b)). In the case of the addition illustrated in (c) of Figure 1,the binary boded decimal representation "0001 0110" should be obtained. However, when the correction of adding "+6" is automatically performed, recorrection of "-6" is unnecessary because the addition of "+6" results in the above mentioned value (see the righthand column of Figure 1 (c)).

On the other hand, when the arithmetic operation of two numbers in binary coded decimal representation substantially concerns subtraction (namely, when the signs of both numbers are same and the arithmetic operation is addition or when the signs are different and the arithmetic operation is addition), the processing of addition is executed after the correction in which a two's (2's) complement of either one of the two numbers is formed (hereinafter, the number for which the 2's complement is formed is referred to as the minuent). The result of addition is outputted intact when a carry signal is produced from the digit in concern, while the recorrection processing is performed by adding "-6" to the result of addition unless no carry signal is produced from the digit in concern.

More specifically, reference is to be made to (d) of Figure 1. In this case, it is assumed that arithmetic operation for realizing "7 - 3 = 4" is to be carried out. Since the addition of the number represented by "0111" in the binary coded decimal notation and the two's complement "1101" or "0011" results in the appearance of a carry signal, the result "0100" of outputted intact. On the other hand, in the case of arithmetic operation for realizing "3 - 7 = -4", addition of "0011" with the two's complement "1001" of "0111 " results in "1100"without being accompanied with any carry signal. Therefore, recorrection is carried out by adding "-6", whereby the ten's complement "0110" of the difference "-4" is outputted as the result of the arithmetic operation.

Subsequently, the ten's complement of "0110" is again formed to produce the final output of "-(4)10".

As will be understood from the above, when the absolute value of the minuent is smaller than that of the subtrahend in the case where the arithmetic operation substantially concerns subtraction, the arithmetic operation results in the number represented by its ten's complement. Accordingly, in order to obtain the number represented in the binary coded decimal notation, extra processing is required for the recomplementation of the result of the arithmetic operation, giving rise to a problem that the time required for the overall arithmetic processing is increased.

It is an object of the present invention to eliminate the drawback of the hitherto known decimal arithmetic operation scheme mentioned above and to provide a decimal arithmetic system which allows a binary boded decimal number to be always derived in the sign and absolute value representation in the same arithmetic operation cycle independent of whether the decimal arithmetic operation is substan tiaily addition or subraction.

According to the present invention, there is provided a decimal arithmetic system comprising an end-around carry type adder for performing arithmetic addition or subtraction of two numbers in binary coded decimal representation after a first correction for the decimal arithmetic operation to output the result of the arithmetic operation and a one s complement of said result, first discriminating means for determining whether to select the complement of the result of the arithmetic operation as the output of said adder, and second discriminating means for determining the presence or absence of carry signals to next higher-order digits for each of digits, wherein when said first discriminating means determines that the complement of the result of the arithmetic operation is to be selected as the output of said adder, a second correction for the decimal arithmetic operation is effected for those of the digits for which respective carry signals were present at the time of the arithmetic operation, while said second correction is effected for those of the digits for which the respective carry signals were absent at the time of the arithmetic operation, when said first discriminating means determines the complement of the result of the arithmetic operation is not to be selected as the output of said adder.

The above object of the present invention will now be apparent when reading the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 7 is a view for illustrating schemes of addition and subtraction of two corresponding decimal digits; Figure 2 is a block diagram showing an arrangement of a decimal arithmetic system according to an embodiment of the present invention; Figures 3a and 3b show logic arrangements of a first discriminator circuit and a logic circuit shown in Figure 2; and Figure 4, 5 and 6 are views for illustrating, respectively, examples of decimal arithmetic operations executed by the decimal arithmetic system according to the invention.

Referring to Figure 2 which shows an arrangement of the decimal arithmetic system according to an embodiment of the invention, a first number in binary coded decimal representation is placed in a first register 1,while a second number in binary coded decimal representation is placed in a register 2. Further, an instruction code (hereinafter represented by F) is loaded in a register 12, a sign (hereinafter represented by S1 ) of the first number in binary coded decimal representation is placed in a register 13, and a sign (hereinafter represented by S2) of the second number in binary coded decimal representation is placed in a register 14. A reference numeral 6 denotes a first discriminator circuit for determining whether or not to take a complement of the result of arithmetic operation as the output of an adder 4, as will be described below in more detail.

The output of the register 1 which holds the first number is coupled to a first input of the adder 4, which is of end-around carry (EAC) type, and at the same time to an input of a second discriminator circuit 5. The end-around carry type adder 4 has an output at which the result (4a) of the arithmetic operation performed by the adder 4 is produced and the other output at which a one's complement (4b) of the result of the arithmetic operation is produced.

The second discriminator circuit 5 serves to determine the presence of absence of a signal representative of carry to the next higher-order position for every digit at the time of the arithmetic operation.

The output of the register 2 which holds the second number is applied to a second input of the adder 4 and to the second discriminator circuit 5, respectively, through a decimal arithmetic operation correcting circuit 3.

The output of the register 12 which holds the instruction code F, the output of the register 13 which holds the sign S1 of the first number, and the output of the register 14 which holds the sign S2 of the second number are inputted to a third discrimi nator circuit 15 which functions to determine whether the arithmetic operation in concern is substantially addition or subtraction.As the inputs to the decimal arithmetic operation correcting circuit 3 and the first disciminator circuit 6 determining whether or not to take the complement of the result of the arithmetic operation executed through the adder 4, the third discriminator circuit 15 produces on an output line 1 5a thereof a signal indicating that the arithmetic operation is substantially addition when the instruction code F is indicative of addition with the signs S1 and S2 being same or when the code F is indicative of substraction with the signs S1 and S2 being different from each other, and produces on the other output line 1 5b thereof a signal indicating that the arithmetic operation is substantially subtraction when the instruction code F is indicative of subtraction with the signs S1 and S2 being same or when the code F is indicative of addition with the signs S1 and S2 being different.

The output of the register 13 which holds the sign S1 is also supplied to a sign determinator circuit 16 which serves to determine a sign for the result of the arithmetic operation upon completion thereof.

When the arithmetic operation in concern is substantially addition, the decimal arithmetic operation correcting circuit 3 functions to add a value "+6" to every digit of the second number supplied from the register 2. On the other hand, when the arithmetic operation is substantially subtraction, the decimal arithmetic operation correcting circuit 3 functions to produce a one's complement of the output of the register 2.

The second discriminator circuit 5 operates on the basis of the carry look-ahead principle (refer to Kai Hwang: "Computer Arithmetic PRINCIPLES ARCHTECTURE AND DESIGN" published by John Wiley & Sons, Inc. (Copyright 1979)) to determine whether there is present or absent a signal indicating carry to the next higher-order position for every digit upon arithmetic operation. When the result of the determination is logically true, a signal indicative of this fact is supply from the second discriminator 5 through an output line 5a to a logic circuit 7 composed of elementary logic circuits each provided in correspondence to each of the digits. On the other hand, when the result of the determination has proven logically false, a signal indicating this fact is supplied to the logic circuit 7 through an output line 5b. In this connection, it should be mentioned that the signal "true" corresponds to the presence of the carry signal while the signal "false" represents the absence of the carry signal. Additionally, the second discriminator circuit 5 also serves to determine the presence or absence of the carry signal from the highest-order (most significant) digit or position, that is the presence or absence of the end-around carry, and supply to the first discriminator circuit 6 the signal indicating that the result of the determination is true or false through the output line 5a or 5b.

When the arithmetic operation is substantially addition or when there occurs the end-around carry, the first discriminator circuit 6 supplies to the logic circuit 7 through the output line 6a a signal indicating that a complement of the result of the arithmetic operation is not to be selected as the output of the adder 4. On the other hand, provided that the arithmetic operation is substantially subtraction and that the end-around carry is absent, the first discriminator circuit 6 supplies to the logic circuit 7, a selector 8 and the sign determinator circuit 16 through the output line 6b a signal which indicates that the complement of the result of the arithmetic operation is to be taken as the output of the adder 4.

In this connection, it also should be mentioned that the output of the first discriminator circuit 6 is true when the complement is to be selected while it is false when the complement is not to be selected.

Referring to Figure 3Awhich shows a logic arrangement of the first discriminator circuit 6, the signal indicating the addition in the intrinsic sense and the signal indicative of the presence of the end-around carry are applied to the inputs of an OR gate 61 through the lines 15a and 5a, respectively, while the signal indicating the subtraction in the intrinsic sense and the signal indicative of the absence of the end-around carry are applied to the inputs of an AND gate 62 through the lines 15b and 5b, respectively. The logical sum signal output from the OR gate 61 and the logical product signal output from the AND gate 62 are produced on output lines 6a and 6b, respectively.

Figure 3b shows a circuit configuration of a zero-th elementary logic circuit 70 of the logical circuit 7.

More specifically, the logic circuit 7 includes a number of the elementary logic circuits of the same circuit configuration as the one shown in Figure 3b which are provided for the digits in one-to-one correspondence. When the complement output is selected as the output of the adder 4, each of the elementary logic circuits 70 produces a signal which indicates that correction is to be made on the decimal arithmetic operation for those associated digits at which carry signals to the respective next higher-order digits are present, while producing a signal indicating the correction of the decimal arithmatic operation for those associated digits at which carry signals to the respective next higher-order digits are absent, when the result of the arithmetic operation is selected intact as the output of the adder 4.

In the elementary logic circuit 70 (referto Figure 3b), the signal indicating that the complement of the result of the arithmetic operation is selected as the output of the adder 4 and the signal indicating that the carry to the next higher-order digit or position is produced at the associated digit are supplied to the inputs of an AND gate 701 through the output line 6b and 5a, respectively. Further, the signal indicating that the complement of the result of arithmetic operation is not selected as the output of the adder 4 and the signal indicating that the carry to the next higher-order digit is absent at the digit associated with this elementary logic circuit 70 are supplied to the inputs of an AND gate 702 through the respective output lines 6a and 5b. The outputs of the AND gate 701 and 702 are ORed through an OR gate 703.

Next, description will be briefly made of the selector 8, the decimal arithmetic operation correcting circuit 9, the selector 10 and an output register 11 provided at the output of the first discriminator.

When the output of the first discriminator circuit 6 is ture, the selector 8 selects the one's (l's) complement of the result of arithmetic operation executed by the adder 4 supplied thereto through the input line 4b and supplies the one's complement thus selected to the decimal arithmetic operation correcting circuit 9 and hence to the selector 10. On the other hand, in case the output of the first discriminator circuit 6 is false, the selector 8 selects the result of the arithmetic operation executed by the output of the adder 4 and outputs it as it is.

The decimal arithmetic operation correcting circuit 9 serves for the correcting operation by adding a value "-6" to every digit outputted from the selector 8.

The selector 10 serves to select the output of the selector 8 corrected through the decimal arithmetic operation correcting circuit 9 for those digits for which the outputs of the logic circuit 7 are true, while the selector 10 selects the intact output of the selector 8 for those digits for which the outputs of the logic circuit 7 are false.

Further, the sign determinator circuit 16 inverts the sign S1 to be outputted therefrom when the output of the first discriminator circuit 6 is true. When the latter is false, the sign determinator circuit 16 allows the sign S1 to pass therethrough as it is (i.e. without inversion). The output sign signal from the sign determinator circuit 16 is loaded in the register 17.

In the following, a few examples of operation of the system shown in Figure 2 will be described.

(1) ADDITION OFTWO NUMBERS IN BINARY CODED DECIMAL REPRESENTATION Operation for "0456 + 0725 = 1181" is illustrated in Figure 4. It is assumed that the adder 4 is adapted to perform the addition of numbers represented in hexadecimal notation.

At first, the two numbers "0456" and "0725" in binary coded decimal representation are set in the registers 1 and 2, respectively.

The content "0456" of the register 1 is supplied to the adder 4 as it is. Thus, the first input value of the adder 4 is "0456".

On the other hand, the content "0725" of the register 2 is corrected by adding "+6" to every digit through the decimal arithmetic operation correcting circuit 3 before being supplied to the adder 4, because the arithmetic operation in concern is substantially addition. Accordingly, the second input value to the adder 4 is "6D8B". The result of the arithmetic operation effected by the adder 4 is thus "71 El", as shown in Figure 4. Here, it should be recalled that the output of the first discriminator circuit 6 is false whenever the arithmetic operation in concern is substantially addition. Accordingly, the output of the selector 8 is "71E1".

On the other hand, for those digits for which the carry signal is absent, i.e. for the first and the third significant digits in the case of the example shown in Figure 4, the signals indicating that the result of determination made by the second discriminator circuit 3 is false is supplied to the inputs of the elementary logic circuits 70 associated with the first and the third digits over the output line 5b, resulting in that the outputs of the elementary logic circuits 70 associated with the first and the third digits are false.

On the other hand, for those digits for which the carry signal is present from the respective next lower-order digits, i.e. for the second and the fourth significant digits in the case of the example shown in Figure 2, the outputs of the associated elementary logic circuits 70 are false. On these conditions, the values "1" and "8" resulted from the correction made by the decimal arithmetic operation correcting circuit 9 in which the value "-6" is added to the values "7" and "E" outputted from the selector 8 for the first and the third digits are produced from the selector 10, while for the second and the fourth digits the output values "1" and "1" of the selector 8 are outputted from the selector 10. As the result, the value "1181" is placed in the output register 11.

Further, since the output of the first discriminator circuit 6 is false, the sign S1 placed in the register 13 is outputted as it is (i.e. without being inverted) through the sign determinator circuit 16, whereby the sign S1 being positive or plus is placed in the register 17. In this way, the output value "+1181" is obtained, whereupon the arithmetic operation comyes to an end.

(2) SUBTRACTION OFTWO NUMBERS IN BINARY CODED DECIMAL REPRESENTATION (EXAMPLE 1) Operation for "0725 - 0456 = 0269 will be described by referring to Figure 5.

At first, two numbers "0725" and "0456" in binary coded decimal representation are loaded in the registers 1 and 2, respectively. Since the content "0725" of the register 1 is fed to the adder 4 as it is, the first input value of the adder 4 is "0725".

On the other hand, because the arithmetic operation in concern is substantially subtraction, the content "0456" of the register 2 is converted its one's (l's) complement by means of the decimal arithmetic operation correcting circuit 3 in precedence to the entry to the adder 4. Accordingly, the second input value of the adder 4 is "FBA9". The result of the arithmetic operation performed by the adder 4 is "02CF", because the end-around carry is "1", as shown in Figure 5.

It should be recalled that the output of the first discriminator circuit 6 is false, when the arithmetic operation is substantially subtraction and the endaround carry is "1". Accordingly, the output of the selector 8 is "02CF".

On the other hand, for the digits for which the carry signals from the relevant digits are absent, i.e.

for the third and fourth significant digits in the case of the example illustrated in Figure 5, the signal indicating that the result of determination made by the second discriminator circuit 5 is false is inputted to the elementary logic circuits 70 associated with these digits through the output line 5b, resulting in that the output signals of the logic circuit 7 are true for the third and the fourth digits, respectively. To the contrary, for the digits for which the carry signal is present from the relevant digits, i.e. for the first and second significant digits in the case of the example illustrated in Figure 5, the output of the logic circuit 7 is false.Under the circumstances, the output values "C" and "F" of the selector 8 for the third and fourth digits are corrected by adding thereto the value "-6" through the decimal arithmetic operation correcting circuit 9, resulting in that the corrected values "6" and "9" are outputted from the selector 10 for the third and the fourth digits, while the output values "0" and "2" are produced at the output of the selector 10 for the first and the second digits, respectively.

Thus, the value placed in the output register 11 is "0269". Further, since the output of the first discriminator circuit 6 is false, the sign S1 set in the tregister 13 is outputted as it is (i.e. being positive or plus) from the sign determinator circuit 16 to be placed in the register 17. The final result is "+0269". The arithmetic operation then comes to an end.

(3) SUBTRACTION OFTWO NUMBERS IN BINARY CODED DECIMAL REPRESENTATION (EXAMPLE 2) Finally, operation for "0456 - 0725 = -0269" will be described by referring to Figure 6.

At first, two numbers "0456" and "0725" in binary coded decimal representation are placed in the registers 1 and 2, respectively. Since the content "0456" of the register 1 is transferred intact to the adder 4, the first input value of the adder 4 is "0456".

In contrast, the content "0725" of the register is converted to its one's complement through the decimal arithmetic operation correcting circuit 3 in precedence to the supply to the adder 4, because the arithmetic operation in concern is substantially subtration. Accordingly, the second input value of the adder 4 is "F8DA". The result of the arithmetic operation performed by the adder4forthese input values is "FD30", because the end-around carry is "0". Thus, the one's complement of the result of this arithmetic operation is "02CF".

Here, it should be recalled that the output of the first discriminator circuit 6 is true for the reasons that the arithmetic operation is substantially subtraction and that the end-around carry is "0". Accordingly, the output value of the selector 8 is "02CF".

On the other hand, for those digits for which the carry signals are present from the relevant digits, i.e.

for the third and the fourth significant digits in the case of the example illustrated in Figure 6, the signal indicating that the result of determination made by the second discriminator circuit 5 is true is inputted to the elementary logic circuits 70 corresponding to the third and fourth digits through the line 5a, resulting in that the output of the logic circuit 7 is true for the thrid and fourth digits.

To the contrary, for those digits for which the carry signals from the relevant digits are absent, i.e. for the first and the second significant digits in the case of the example illustrated in Figure 6, the output of the logic circuit 7 is false. On these conditions, the values "6" and "9" resulted from the correction performed through the decimal arithmetic operation correcting circuit 9 by adding "-6" to the values "C" and "F" outputted from the selector 8 for the third and the fourth digits are outputted from the selector 10, while the latter outputs the values "0" and "2" supplied from the selector 8, as they are, for the first and the second digits, respectively.

As the result, the value "0269" is obtained in the output register 11. Further, since the output of the first discriminator circuit 6 is true, the sign S1 placed in the register 13 is inverted by the sign determinator circuit 16 to be set at the register 17 as the negative or minus sign.

In this way, the value "-0269" is finally obtained in the output register 11, whereupon the arithmetic operation is finished.

As will be appreciated from the foregoing, the decimal arithmetic operation which is substantially substraction can be executed to obtain a binary coded decimal number represented by an absolute value in the same cycle as of the arithmetic operation which is substantially addition, without requiring the recomplementation cycle in succession to the execution of the arithmetic operation, whereby the decimal arithmetic operation which is substantially subtraction can be executed at an increased speed.

Claims (3)

1. A decimal arithmetic system comprising an end-around carry type adder for performing arithmetic addition or subtraction of two numbers in binary coded decimal representation after a first correction for the decimal arithmetic operation to output the result of the arithmetic operation and a one's complement of said result, first discriminating means for determining whether to select the complement of the result of the arithmetic operation as the output of said adder, and second discriminating means for determining the presence or absence of carry signals to next higher-order digits for each of digits, wherein when said first discriminating means determines that the complement of the result of the arithmetic operation is to be selected as the output of said adder, a second correction for the decimal arithmetic operation is effected for those of the digits for which respective carry signals were present at the time of the arithmetic operation, while said second correction is effected for those of the digits for which the respective carry signals were absent at the time of the arithmetic operation, when said first discriminating means determines the complement of the result of the arithmetic operation is not to be selected as the output of said adder.

2. A decimal arithmetic system according to Claim 1, wherein said second correction is made for the selected output of said adder.

3. A decimal arithmetic system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.